edge sync on done signals so we only fill/empty one buffer

2 files changed, 32 insertions, 2 deletions

diff --git a/usrp2/gpmc/edge_sync.v b/usrp2/gpmc/edge_sync.v
new file mode 100644
index 000000000..5d9417c08
--- /dev/null
+++ b/usrp2/gpmc/edge_sync.v
@@ -0,0 +1,22 @@
+
+
+module edge_sync
+  #(parameter POSEDGE = 1)
+   (input clk,
+    input rst,
+    input sig,
+    output trig);
+   
+   reg [1:0] delay;
+   
+   always @(posedge clk)
+     if(rst)
+       delay <= 2'b00;
+     else
+       delay <= {delay[0],sig};
+   
+   assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10);
+   
+endmodule // edge_sync
+
+
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 91d02bfec..831df3b4c 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -32,7 +32,11 @@ module gpmc
    // ////////////////////////////////////////////
    // Write path
    wire 	read_sel_in, write_sel_in, clear_in;
-   wire 	write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF);
+   wire 	write_done_in;
+   
+   edge_sync #(.POSEDGE(0)) 
+   edge_sync_wdi(.clk(wb_clk), .rst(wb_rst), 
+		 .sig(~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF)), .trig(write_done_in));
    
    ram_2port_mixed_width buffer_in
      (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(),
@@ -47,7 +51,11 @@ module gpmc
    // ////////////////////////////////////////////
    // Read path
    wire 	read_sel_out, write_sel_out, clear_out;
-   wire 	read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF);
+   wire 	read_done_out;
+      
+   edge_sync #(.POSEDGE(0)) 
+   edge_sync_rdo(.clk(wb_clk), .rst(wb_rst), 
+		 .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_out));
    
    ram_2port_mixed_width buffer_out
      (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram),