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* connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | be read/controlled from SW
* Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * Merge branch 'master' into udpMatt Ettus2010-03-252-3/+1
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| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
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| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
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| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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| * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
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| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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| * | copied over from quad radioMatt Ettus2010-02-081-0/+60
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-254-34/+43
| | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| * | just debug pin changesMatt Ettus2010-01-252-1/+12
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| * | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
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| * | moved into subdirJosh Blum2010-01-22653-0/+1558662
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* | connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
* | debug pinsMatt Ettus2010-02-251-2/+3
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* | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
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* | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
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* | gpmc debug pinsMatt Ettus2010-02-252-4/+14
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* | point to the new filesMatt Ettus2010-02-251-0/+2
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* | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
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* | loopback and testMatt Ettus2010-02-252-7/+38
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* | corrected logicMatt Ettus2010-02-251-17/+7
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* | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
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* | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
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* | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
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* | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
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* | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
|\| | | | | | | | | Conflicts: .gitignore
| * proper initialization of the ramMatt Ettus2010-02-231-1/+1
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* | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-233-6/+63
| | | | | | | | ISE chokes on the unequal size ram
* | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
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* | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
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* | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
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* | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
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* | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
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* | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
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* | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
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* | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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* | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵Matt Ettus2010-02-182-4/+7
| | | | | | | | global set and reset module.
* | speed up the presentation of registered wb data to the gpmcMatt Ettus2010-02-172-13/+20
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* | wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-168-11/+121
| | | | | | | | timing and handle wait states.
* | first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-166-34/+159
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* | copied over from safe_u1eMatt Ettus2010-02-164-0/+553
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* | block ram interface to GPMCMatt Ettus2010-02-161-2/+6
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* | basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
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* | reorg pin defsMatt Ettus2010-02-141-94/+102
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* | connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
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* | organized the pins in the ucf by functionMatt Ettus2010-02-091-56/+72
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* | builds a successful led blinkerMatt Ettus2010-02-093-2/+4
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* | first cut at blinking ledsMatt Ettus2010-02-094-345/+237
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