| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | remove port which is no longer there | Matt Ettus | 2010-05-11 | 1 | -1/+1 | |
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| | * | | | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 | |
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| | * | | | allow settings bus to cross to a new clock domain, should help timing, but ↵ | Matt Ettus | 2010-05-11 | 9 | -0/+534 | |
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| | * | | Update config to all eight clock buffers to be used. | Johnathan Corgan | 2010-03-29 | 1 | -1/+1 | |
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| | * | | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 | |
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| | * | | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 | |
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| | * | | | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 | |
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| | * | | | Remove some warnings in dsp_core_rx | Johnathan Corgan | 2010-02-23 | 1 | -3/+7 | |
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| | * | | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 | |
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| | * | | | Change bit width of CORDIC constants to remove meaningless warning | Johnathan Corgan | 2010-02-23 | 1 | -24/+24 | |
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| | * | | | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs | |||||
| * | | | | packet generator and verifier, to test gpmc and other data transfer stuff | Matt Ettus | 2010-05-12 | 4 | -0/+153 | |
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| * | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵ | Matt Ettus | 2010-05-10 | 8 | -561/+9 | |
| | | | | | | | | | | | | | | | | | safe_u1e necessary. | |||||
| * | | | | proper signal level for 24 bit data | Matt Ettus | 2010-05-10 | 1 | -2/+7 | |
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| * | | | | SPI passthru for programming clock gen chip on brand new boards | Matt Ettus | 2010-05-07 | 3 | -0/+391 | |
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| * | | | | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 3 | -18/+63 | |
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| * | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 | |
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| | * | | | | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 | |
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| * | | | | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 | |
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| * | | | | have_space and have_packet now stay high even while busy, | Matt Ettus | 2010-05-03 | 3 | -4/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO | |||||
| * | | | | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 | |
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| * | | | | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 | |
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| * | | | | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 | |
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| * | | | | Only allow new packets if we can fit the largest possible packet (2KB) | Matt Ettus | 2010-04-23 | 1 | -1/+1 | |
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| * | | | | Register outputs to omap to prevent runt pulses from falsely triggering ↵ | Matt Ettus | 2010-04-23 | 3 | -7/+20 | |
| | | | | | | | | | | | | | | | | | interrupts | |||||
| * | | | | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 | |
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| * | | | | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 | |
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| * | | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 2 | -10/+18 | |
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| * | | | | async seems to work with packet lengths now. Still need to do wishbone regs ↵ | Matt Ettus | 2010-04-15 | 5 | -37/+72 | |
| | | | | | | | | | | | | | | | | | for gpmc | |||||
| * | | | | async gpmc progress | Matt Ettus | 2010-04-15 | 4 | -18/+173 | |
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| * | | | | change time parameters because Xilinx IP has a 1ps timescale | Matt Ettus | 2010-04-15 | 1 | -14/+27 | |
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| * | | | | add bus error reporting | Matt Ettus | 2010-04-15 | 1 | -3/+9 | |
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| * | | | | correct name of module | Matt Ettus | 2010-04-15 | 1 | -2/+2 | |
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| * | | | | progress on synchronous gpmc, but it may not be possible due to the limited ↵ | Matt Ettus | 2010-04-15 | 3 | -43/+45 | |
| | | | | | | | | | | | | | | | | | number of clock edges | |||||
| * | | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 3 | -3/+100 | |
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| * | | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 3 | -6/+8 | |
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| * | | | | more sync progress. This is just a skeleton for now, with junk content | Matt Ettus | 2010-04-14 | 1 | -0/+56 | |
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| * | | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 4 | -26/+95 | |
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| * | | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 2 | -3/+3 | |
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| * | | | | make timing diagrams for bus transactions. Still need to do reads | Matt Ettus | 2010-04-14 | 5 | -0/+46 | |
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| * | | | | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 | |
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| * | | | | probably won't be using this, and it hasn't been tested | Matt Ettus | 2010-04-14 | 1 | -0/+46 | |
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| * | | | | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 2 | -1/+4 | |
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| * | | | | lengthened delay between cycles, added more transactions on the data bus | Matt Ettus | 2010-04-12 | 1 | -2/+7 | |
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| * | | | | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 3 | -120/+117 | |
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| * | | | | split out gpmc to wishbone interface to make gpmc top level cleaner | Matt Ettus | 2010-04-12 | 1 | -0/+57 | |
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| * | | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 5 | -47/+117 | |
| | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | |||||
| * | | | | 16 bit wide spi core | Matt Ettus | 2010-03-27 | 1 | -0/+182 | |
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| * | | | | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 | |
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| * | | | | remove timescale junk | Matt Ettus | 2010-03-26 | 5 | -21/+19 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get rid of asynchronous resets fix spelling error corrected comment | |||||
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