uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	get rid of old CVS linkage	Matt Ettus	2010-05-18	221	-315/+0
*	settings bus to dsp_clk now uses clock crossing fifo	Matt Ettus	2010-05-16	2	-8/+15
*	remove files for old prototypes, they were confusing people	Matt Ettus	2010-05-13	10	-2076/+0
*	revert commit 9899b81f920 which should have improved timing but didn't	Matt Ettus	2010-05-13	1	-5/+13
*	remove port which is no longer there	Matt Ettus	2010-05-11	1	-1/+1
*	cleaned up the logic, this is copied over from quad radio	Matt Ettus	2010-05-11	1	-13/+5
*	allow settings bus to cross to a new clock domain, should help timing, but no...	Matt Ettus	2010-05-11	9	-0/+534
*	Update config to all eight clock buffers to be used.	Johnathan Corgan	2010-03-29	1	-1/+1
*	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
*	Merge commit 'upstream/master'	Johnathan Corgan	2010-03-09	1	-1/+1
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\| *	proper initialization of the ram	Matt Ettus	2010-02-23	1	-1/+1
* \|	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
* \|	Remove some warnings in dsp_core_rx	Johnathan Corgan	2010-02-23	1	-3/+7
* \|	Fix missing item on sensitivity list	Johnathan Corgan	2010-02-23	1	-1/+1
* \|	Change bit width of CORDIC constants to remove meaningless warning	Johnathan Corgan	2010-02-23	1	-24/+24
* \|	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
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*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	633	-0/+1556369