| Commit message (Expand) | Author | Age | Files | Lines |
* | modernize the testbench | Matt Ettus | 2010-11-19 | 1 | -18/+30 |
* | get rid of extraneous U messages when we actually had an ACK | Matt Ettus | 2010-11-18 | 2 | -7/+10 |
* | fix problem with consecutive timed packets on tx | Matt Ettus | 2010-11-18 | 1 | -2/+0 |
* | simplify time comparison to speed up logic and meet fpga timing | Matt Ettus | 2010-11-13 | 2 | -4/+27 |
* | we're still on version 12.1 | Matt Ettus | 2010-11-13 | 2 | -2/+2 |
* | Add flow control and other small vrt fixes to u2p, minor cleanups | Matt Ettus | 2010-11-11 | 2 | -34/+38 |
* | reset properly | Matt Ettus | 2010-11-11 | 1 | -0/+1 |
* | compiles with new file locations | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | handle zero-length packets properly | Matt Ettus | 2010-11-11 | 3 | -55/+76 |
* | clear out the vita tx chain and the tx fifo. need to check the fifo | Matt Ettus | 2010-11-11 | 5 | -24/+25 |
* | added ability to truly clear out the entire rx chain. also removed old style... | Matt Ettus | 2010-11-11 | 3 | -29/+27 |
* | gray code address for emi | Matt Ettus | 2010-11-11 | 1 | -1/+7 |
* | fifo randomizer for emi | Matt Ettus | 2010-11-11 | 5 | -4/+108 |
* | now handles frames larger than the vita packet (i.e. with padding) | Matt Ettus | 2010-11-11 | 1 | -6/+16 |
* | don't clear out following packets on an eob ack | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | don't flag an error on eob ack | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | proper triggering for interrupts generated on the dsp_clk | Matt Ettus | 2010-11-11 | 1 | -1/+8 |
* | cleanup for 32 bit seqnum | Matt Ettus | 2010-11-11 | 1 | -4/+3 |
* | increase compatibility number for flow control | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate | Matt Ettus | 2010-11-11 | 3 | -14/+16 |
* | send message on eob to ack the end of transmission | Matt Ettus | 2010-11-11 | 1 | -1/+6 |
* | typo which isn't caught by xilinx | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | separated flow control and error reporting on tx path. should work with and ... | Matt Ettus | 2010-11-11 | 4 | -25/+43 |
* | go to the correct state | Matt Ettus | 2010-11-11 | 1 | -3/+3 |
* | add a fifo to the end of the mux to help in timing. | Matt Ettus | 2010-11-11 | 1 | -6/+13 |
* | add trigger to makefile | Matt Ettus | 2010-11-11 | 1 | -0/+1 |
* | assign setting reg addresses | Matt Ettus | 2010-11-11 | 1 | -2/+2 |
* | declarations | Matt Ettus | 2010-11-11 | 1 | -2/+3 |
* | checkpoint in flow control packet generation | Matt Ettus | 2010-11-11 | 5 | -42/+147 |
* | these got dropped during the rebase | Matt Ettus | 2010-11-11 | 4 | -31/+37 |
* | Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl... | Ian Buckley | 2010-11-11 | 1 | -49/+4 |
* | 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu... | Ian Buckley | 2010-11-11 | 11 | -11/+555 |
* | 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ | Ian Buckley | 2010-11-11 | 4 | -11/+17 |
* | Defaulted all SRAM pins to LVCMOS25 8mA FAST | Ian Buckley | 2010-11-11 | 1 | -67/+67 |
* | Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default | Ian Buckley | 2010-11-11 | 2 | -7/+23 |
* | Added external RAM FIFO to u2plus. | Ian Buckley | 2010-11-11 | 20 | -100/+4498 |
* | revert unneeded changes and incorrect comments | Matt Ettus | 2010-11-11 | 2 | -34/+34 |
* | reconnect GPIOs, remove debug pins, meets timing now | Matt Ettus | 2010-11-11 | 1 | -5/+3 |
* | Modified phase shift of DCM1 to -64 which is intended to give more timing mar... | Ian Buckley | 2010-11-11 | 1 | -1/+1 |
* | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S... | Ian Buckley | 2010-11-11 | 1 | -12/+12 |
* | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-11-11 | 4 | -5/+100 |
* | Enhanced test bench to be more like real world application | Ian Buckley | 2010-11-11 | 2 | -7/+14 |
* | hangedddddddextrnal fifo size to use full NoBL SRAM | ianb | 2010-11-11 | 1 | -1/+1 |
* | Corrected extfifo code so that all registers that are on SRAM signals are pac... | ianb | 2010-11-11 | 5 | -46/+59 |
* | capacity logic fix | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
* | Added capacity to the module pinout | Ian Buckley | 2010-11-11 | 1 | -3/+4 |
* | Added a bunch of debug signals. | Ian Buckley | 2010-11-11 | 4 | -9/+19 |
* | Regenerated FIFO with lower trigger level for almost full flag to reflect log... | Ian Buckley | 2010-11-11 | 8 | -236/+113 |
* | Regenerated FIFO's for extfifo. | Ian Buckley | 2010-11-11 | 11 | -726/+15 |
* | Edited FIFO instance to delete port that was not regenerated after reconfigur... | Ian Buckley | 2010-11-11 | 1 | -1/+0 |