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| author | Ian Buckley <ianb@server2.ionconcepts.com> | 2010-09-30 15:54:03 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:35 -0800 |
| commit | 84b42223ce7d119ef89ffa4030c904c1b8efc243 (patch) | |
| tree | 0c5f770c1336ae92407290a7bdf054b73674a593 /usrp2 | |
| parent | 60a22a5273b58da49aec5c66f46738be2b7499ba (diff) | |
| download | uhd-84b42223ce7d119ef89ffa4030c904c1b8efc243.tar.gz uhd-84b42223ce7d119ef89ffa4030c904c1b8efc243.tar.bz2 uhd-84b42223ce7d119ef89ffa4030c904c1b8efc243.zip | |
Modified phase shift of DCM1 to -64 which is intended to give more timing margin on reads from the SRAM at the expense of Writes to the SRAM.
Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer.
Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index faf35d12f..4f7f9bf1a 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -412,7 +412,7 @@ module u2_rev3 defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = -12; + defparam DCM_INST1.PHASE_SHIFT = -64; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), |