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* e100: tighten timing - less routing on EM_AJosh Blum2012-07-192-2/+2
* u1plus: added sr misc hook for clock syncJosh Blum2012-07-181-1/+8
* e100: renamed top level for E100/E110 to E1x0Josh Blum2012-07-175-9/+9
* E100: squash E100/E110 top level workJosh Blum2012-07-166-531/+84
* gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-161-15/+11
* Merge branch 'master' into nextJosh Blum2012-07-161-1/+1
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| * Merge branch 'maint'Josh Blum2012-07-161-1/+1
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| | * e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-151-1/+1
* | | B100: squash B100 top level workJosh Blum2012-07-024-406/+348
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* | b100: removed unused proto filesJosh Blum2012-06-133-390/+0
* | Merge branch 'maint'Josh Blum2012-05-101-1/+1
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| * e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
* | e100/b100: bumped compat number for timed commands mergeJosh Blum2012-04-252-2/+2
* | b100: implement packet-end/flush cycle timeoutJosh Blum2012-04-241-1/+1
* | N2x0: updated the bootloader w/ latest from fwJosh Blum2012-04-201-390/+390
* | usrp2: remove settings_fifo_ctrl, meets timingJosh Blum2012-04-201-2/+11
* | usrp: work on meeting timing constraintsJosh Blum2012-04-102-16/+16
* | Merge branch 'master' into nextJosh Blum2012-04-093-2/+62
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| * | Merge branch 'maint'Josh Blum2012-04-094-5/+5
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| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-094-5/+5
| * | Merge branch 'maint'Josh Blum2012-04-021-1/+1
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| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-011-1/+1
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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* | Merge branch 'master' into nextJosh Blum2012-03-261-1/+1
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| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-241-1/+1
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-162-2/+2
* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-162-28/+28
* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-163-3/+3
* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-163-320/+320
* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-163-351/+394
* | spi: created simple spi core (sr based)Josh Blum2012-03-162-383/+397
* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-162-2/+2
* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-161-5/+10
* | srb: created command queue, in and out state machinesJosh Blum2012-03-162-4/+2
* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-161-4/+38
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* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-064-4/+4
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-044-62/+51
* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
* b100: connect all clears for gpifJosh Blum2012-02-031-1/+1
* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0210-28/+61
* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-014-11/+21
* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-013-20/+27
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| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-121-2/+2
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