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authorJosh Blum <josh@joshknows.com>2012-03-01 15:58:34 -0800
committerJosh Blum <josh@joshknows.com>2012-03-16 11:29:17 -0700
commit74ceca35897d46e5a2a314c22259c84ae2201f73 (patch)
treeb3b3ba0a419f526a4c8f6a95b51d29def4976e8d /usrp2/top
parent54e09f3936dfff28fb8c06bfb783806762bfde66 (diff)
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srb: created command queue, in and out state machines
Diffstat (limited to 'usrp2/top')
-rw-r--r--usrp2/top/N2x0/u2plus_core.v3
-rw-r--r--usrp2/top/USRP2/u2_core.v3
2 files changed, 2 insertions, 4 deletions
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 3459bbc6f..6b915698a 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -443,7 +443,6 @@ module u2plus_core
//compatibility number -> increment when the fpga has been sufficiently altered
localparam compat_num = {16'd9, 16'd0}; //major, minor
- wire [31:0] churn = 0; //tweak churn until timing meets!
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -508,7 +507,7 @@ module u2plus_core
wire [31:0] srb_debug;
settings_readback_bus_fifo_ctrl #(.PROT_DEST(3)) srb
(
- .clock(dsp_clk), .reset(dsp_rst),
+ .clock(dsp_clk), .reset(dsp_rst), .clear(0),
.vita_time(vita_time),
.in_data(srb_rd_data), .in_valid(srb_rd_valid), .in_ready(srb_rd_ready),
.out_data(srb_wr_data), .out_valid(srb_wr_valid), .out_ready(srb_wr_ready),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 6bf60fe58..9b26b98e1 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -443,13 +443,12 @@ module u2_core
//compatibility number -> increment when the fpga has been sufficiently altered
localparam compat_num = {16'd9, 16'd0}; //major, minor
- wire [31:0] churn = 0; //tweak churn until timing meets!
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
- .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+ .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(compat_num),.word13({20'b0, clk_status, serdes_link_up, 10'b0}),