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* slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emiMatt Ettus2010-10-211-43/+43
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
* increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-10-101-1/+2
* revert unneeded changes and incorrect commentsMatt Ettus2010-10-071-32/+32
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
* Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-062-7/+10
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| * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| * clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
| * Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-252-5/+5
* | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
* | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
* | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
* | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
* | Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-08-252-37/+42
* | Added a bunch of debug signals.Ian Buckley2010-08-191-4/+5
* | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-191-1/+2
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| * | Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-08-191-1/+2
* | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-161-2/+5
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| * | added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
* | | Matt's attempt at mergingMatt Ettus2010-08-161-27/+23
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| * | connect the demuxMatt Ettus2010-07-281-1/+1
| * | fix a typoMatt Ettus2010-07-281-1/+1
| * | tx error packets now muxed into the ethernet stream back to the hostMatt Ettus2010-07-281-27/+22
* | | Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-161-8/+9
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| * move declaration ahead of useMatt Ettus2010-07-191-5/+5
| * put run_tx and run_rx on the displayed LEDsMatt Ettus2010-07-191-3/+4
* | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-07-314-140/+226
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* barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-142-52/+51
* produces good bin filesMatt Ettus2010-06-112-12/+20
* first attempt at cleaning up the build systemMatt Ettus2010-06-103-414/+65
* get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
* move u2_core into u2_rev3 directory to simplify directory structure and save ...Matt Ettus2010-06-084-2/+1657
* report ise version in buildMatt Ettus2010-06-071-1/+1
* proper name for directoryMatt Ettus2010-06-071-1/+1
* name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
* from UDP branch, changed names because I want these separate from the non-udp...Matt Ettus2010-05-271-0/+267
* new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-271-1/+1
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| * ignoresMatt Ettus2010-05-181-1/+1
| * move dsp settings regs to reclocked setting bus. Works, gets us to within 18...Matt Ettus2010-05-121-0/+3
| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-263-4/+15
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-251-2/+1
| * | moved into subdirJosh Blum2010-01-224-0/+1085
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* / settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-161-0/+3
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* Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
* Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
* Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
* Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-224-0/+1068
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