| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | invert led signals because they are active low | Matt Ettus | 2010-11-09 | 1 | -1/+1 |
| | | |||||
| * | duh | Matt Ettus | 2010-11-04 | 1 | -1/+1 |
| | | |||||
| * | watch the ethernet chip select on our debug bus | Matt Ettus | 2010-09-23 | 3 | -6/+8 |
| | | |||||
| * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ↵ | Matt Ettus | 2010-09-21 | 2 | -50/+25 |
| | | | | | 90 degree phase shift | ||||
| * | updated pins to match rev2, removed dip switch, etc. seems to compile ok. | Matt Ettus | 2010-09-09 | 3 | -137/+130 |
| | | |||||
| * | add register to tell host about compatibility level and which image we are using | Matt Ettus | 2010-08-30 | 1 | -5/+14 |
| | | |||||
| * | move declaration to make loopback compile | Matt Ettus | 2010-08-27 | 1 | -1/+2 |
| | | |||||
| * | no need for protocol headers since we're not doing ethernet | Matt Ettus | 2010-08-24 | 1 | -1/+1 |
| | | |||||
| * | match the signal names in this design | Matt Ettus | 2010-08-23 | 1 | -3/+3 |
| | | |||||
| * | debug pins cleanup | Matt Ettus | 2010-08-23 | 1 | -3/+3 |
| | | |||||
| * | properly integrate the new tx chain | Matt Ettus | 2010-08-19 | 1 | -31/+27 |
| | | |||||
| * | attach run_tx and run_rx to leds | Matt Ettus | 2010-08-17 | 1 | -1/+1 |
| | | |||||
| * | connect atr | Matt Ettus | 2010-08-17 | 1 | -1/+1 |
| | | |||||
| * | delay the q channel to make the channels line up on the AD9862 | Matt Ettus | 2010-08-17 | 1 | -1/+6 |
| | | |||||
| * | this is necessary for some reason | Matt Ettus | 2010-08-13 | 1 | -1/+2 |
| | | |||||
| * | connect the setting reg to the real clock and reset | Matt Ettus | 2010-08-11 | 1 | -1/+1 |
| | | |||||
| * | enlarge loopback fifo | Matt Ettus | 2010-08-10 | 1 | -4/+1 |
| | | |||||
| * | make loopback compile | Matt Ettus | 2010-07-14 | 1 | -0/+3 |
| | | |||||
| * | added ability to clear out fifos of tx and rx. | Matt Ettus | 2010-06-17 | 1 | -12/+21 |
| | | |||||
| * | Merge branch 'master' into u1e_newbuild | Matt Ettus | 2010-06-14 | 1 | -206/+39 |
| | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v | ||||
| * | debug pins | Matt Ettus | 2010-06-10 | 1 | -3/+6 |
| | | |||||
| * | much bigger fifos | Matt Ettus | 2010-06-10 | 1 | -2/+2 |
| | | |||||
| * | proper overrun, underrun connections, debug pins. | Matt Ettus | 2010-06-10 | 1 | -4/+8 |
| | | |||||
| * | debug pins | Matt Ettus | 2010-06-08 | 1 | -1/+2 |
| | | |||||
| * | remove double declaration | Matt Ettus | 2010-06-06 | 1 | -1/+1 |
| | | |||||
| * | use fifo19 not fifo18 in makefile | Matt Ettus | 2010-06-06 | 1 | -1/+1 |
| | | |||||
| * | use same version as usrp2-udp, so regs are same place in memory map | Matt Ettus | 2010-06-01 | 2 | -2/+2 |
| | | |||||
| * | connect the rx run lines so it doesn't get optimized out | Matt Ettus | 2010-06-01 | 1 | -1/+4 |
| | | |||||
| * | use DDR regs instead of a 2nd clock | Matt Ettus | 2010-06-01 | 1 | -8/+46 |
| | | |||||
| * | assign addresses for the settings regs | Matt Ettus | 2010-06-01 | 1 | -5/+6 |
| | | |||||
| * | vita49 tx and rx added in, all sample rates now at main system clock rate. | Matt Ettus | 2010-06-01 | 4 | -107/+220 |
| | | |||||
| * | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 1 | -2/+2 |
| | | |||||
| * | put over/underrun on debug bus, remove high order address bits | Matt Ettus | 2010-05-20 | 1 | -1/+2 |
| | | |||||
| * | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-20 | 1 | -4/+2 |
| |\ | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v | ||||
| | * | better debug pins | Matt Ettus | 2010-05-17 | 1 | -6/+4 |
| | | | |||||
| * | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 2 | -34/+24 |
| |/ | |||||
| * | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵ | Matt Ettus | 2010-05-12 | 2 | -22/+43 |
| | | | | | packet gen and test | ||||
| * | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵ | Matt Ettus | 2010-05-10 | 1 | -1/+1 |
| | | | | | safe_u1e necessary. | ||||
| * | proper signal level for 24 bit data | Matt Ettus | 2010-05-10 | 1 | -2/+7 |
| | | |||||
| * | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 3 | -18/+63 |
| | | |||||
| * | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
| |\ | |||||
| | * | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
| | | | |||||
| * | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 |
| |/ | |||||
| * | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 |
| | | |||||
| * | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 |
| | | |||||
| * | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 |
| | | |||||
| * | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 |
| | | |||||
| * | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 |
| | | |||||
| * | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 1 | -6/+14 |
| | | |||||
| * | async seems to work with packet lengths now. Still need to do wishbone regs ↵ | Matt Ettus | 2010-04-15 | 1 | -3/+3 |
| | | | | | for gpmc | ||||
 |
index : uhd | |
| Ettus' UHD Repository |
| aboutsummaryrefslogtreecommitdiffstats |