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* u1e: incremented compat # to 4 for vita length changeJosh Blum2011-05-201-1/+1
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* u1e: get dsp_framer36 from u1p so it can skip the protocol headerMatt Ettus2011-05-091-1/+1
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* u1e: switch to vita_rx_chain module just like other toplevelsMatt Ettus2011-05-092-20/+11
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* u1e: use icarus verilog for lintMatt Ettus2011-03-161-0/+2
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* clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-161-5/+6
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* u1e: removed old directory from makeMatt Ettus2011-03-151-1/+0
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* u1e: keep up with fixes made for u2/u2p, make it compile againMatt Ettus2011-03-151-1/+0
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* timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-251-0/+4
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* u1e: hook up tester controlsMatt Ettus2011-02-171-4/+6
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* hook up under/overruns for debug purposesMatt Ettus2011-02-161-3/+7
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* e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-161-74/+1
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* separate clear for tx and rx, and add a global reset from the hostMatt Ettus2011-02-021-10/+19
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* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-1/+2
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* usrp-e100: added 32bit test read/write register, fixes to get buildingJosh Blum2011-01-251-7/+17
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* reorganized u1e register space to make room for 64 settingregsMatt Ettus2011-01-251-12/+15
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* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-141-4/+16
| | | | | created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
* invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
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* duhMatt Ettus2010-11-041-1/+1
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* watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
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* fix timing issue on DAC outputs with rev 2. This puts the whole system on a ↵Matt Ettus2010-09-212-50/+25
| | | | 90 degree phase shift
* updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
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* add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
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* move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
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* no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
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* match the signal names in this designMatt Ettus2010-08-231-3/+3
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* debug pins cleanupMatt Ettus2010-08-231-3/+3
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* properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
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* attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
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* connect atrMatt Ettus2010-08-171-1/+1
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* delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
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* this is necessary for some reasonMatt Ettus2010-08-131-1/+2
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* connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
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* enlarge loopback fifoMatt Ettus2010-08-101-4/+1
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* make loopback compileMatt Ettus2010-07-141-0/+3
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* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
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* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-206/+39
| | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
* debug pinsMatt Ettus2010-06-101-3/+6
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* much bigger fifosMatt Ettus2010-06-101-2/+2
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* proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
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* debug pinsMatt Ettus2010-06-081-1/+2
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* remove double declarationMatt Ettus2010-06-061-1/+1
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* use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
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* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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* connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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* use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
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* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
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