| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'master' into u1e_newbuild | Matt Ettus | 2010-06-14 | 1 | -0/+27 |
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| | * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 1 | -0/+28 |
| * | | Merge branch 'ise12_exp' into u1e | Matt Ettus | 2010-06-01 | 2 | -11/+21 |
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| | * | | removes the icache and pipelines the reads | Matt Ettus | 2010-05-20 | 2 | -11/+21 |
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| * | | Merge branch 'master' into u1e_merge_with_master | Matt Ettus | 2010-05-27 | 222 | -318/+6 |
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| | * | added pragmas suggested by Ian Buckley to help ISE12 synthesis | Matt Ettus | 2010-05-18 | 1 | -3/+6 |
| | * | get rid of old CVS linkage | Matt Ettus | 2010-05-18 | 221 | -315/+0 |
| * | | 16 bit wide spi core | Matt Ettus | 2010-03-27 | 1 | -0/+182 |
| * | | remove timescale junk | Matt Ettus | 2010-03-26 | 5 | -21/+19 |
| * | | remove the #1 delay in all the regs. They just slow down sims. | Matt Ettus | 2010-02-22 | 4 | -96/+90 |
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| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 331 | -0/+1515024 |
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