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* first cut at new buffer interface for CPU. Like old buffer_int plusMatt Ettus2010-12-281-0/+169
| | | | a single buffer.
* unused lineMatt Ettus2010-12-281-1/+0
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* packet_router: use the mode register to reset hs control and cpu smsJosh Blum2010-12-271-22/+13
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* packet_router: all non ip/udp should also go to bothJosh Blum2010-12-131-7/+5
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* packet_router: harmless logic tweaksJosh Blum2010-12-122-11/+8
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* packet_router: reverted enable change to dsp framer, it was already correctJosh Blum2010-12-121-2/+1
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* packet_router: raise enable for bram reads the cycle before as wellJosh Blum2010-12-112-2/+4
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* packet_router: added fifo before cpu_out, tweaked inspection logicJosh Blum2010-12-101-25/+29
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* packet_router: gave the inspector a 4th output which is CPU onlyJosh Blum2010-12-101-83/+123
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* packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-0/+1
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* packet_router: split the control register into misc, cpu hs out, cpu hs inpJosh Blum2010-11-241-10/+24
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* packet_router: modification for sequence number and vrt header offsetJosh Blum2010-11-231-1/+1
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* packet_router: it makes more sense to connect the control flags this way nowJosh Blum2010-11-231-13/+6
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* packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-31/+33
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* packet_router: mux the crossbar input after the protocol framerJosh Blum2010-11-231-2/+12
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* packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-2/+42
| | | | udp_wrapper in top level with some fifo conversion stuff
* packet_router: moved dsp framer into a module, added clr to splitter and renamedJosh Blum2010-11-234-93/+110
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* packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-232-45/+65
| | | | module
* packet valve. will drop incoming data if shut off.Matt Ettus2010-11-231-0/+28
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* abstract out the crossbar functionalityMatt Ettus2010-11-231-0/+40
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* packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-231-7/+16
| | | | packet router to be muxed to com out
* packet_router: added a way to program in the ip and mac addrs, and added ↵Josh Blum2010-11-231-2/+17
| | | | inspector check
* packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-9/+41
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* packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-12/+22
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* packet_router: added splitter and mux for slow path stuff (also fixed typo ↵Josh Blum2010-11-232-10/+95
| | | | in crossbar input)
* packet_router: renamed inspector output signals and connected (for now) to ↵Josh Blum2010-11-232-22/+52
| | | | cpu, dsp, crs
* packet_router: use BRAM enables to perform pipelined readsJosh Blum2010-11-231-26/+21
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* packet_router: use control register bit for master mode flagJosh Blum2010-11-231-2/+1
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* packet_router: swapped comm mux for a crossbar, serdes crossbar out now ↵Josh Blum2010-11-231-27/+62
| | | | muxed into the comm output
* packet_router: used registered valid signal for BRAM read cycle delayJosh Blum2010-11-231-16/+15
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* packet_router: created dsp framer for rx pathJosh Blum2010-11-231-6/+100
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* packet_router: added lines for com crossbar and com output muxJosh Blum2010-11-231-13/+35
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* packet_router: collapsed inspector states, fixed terminology for cpu inp vs outJosh Blum2010-11-231-163/+161
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* packet_router: some tweaks, dsp output routing seems to work but has wrong ↵Josh Blum2010-11-231-4/+10
| | | | offset
* packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-231-6/+19
| | | | muxes (in and out)
* packet_router: created com signals (device IO lines that may be ethernet or ↵Josh Blum2010-11-231-79/+100
| | | | serdes)
* packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-231-4/+133
| | | | logic does not enable it yet)
* packet_router: connected and created CPU read from interface (slow path in ↵Josh Blum2010-11-231-47/+153
| | | | place)
* packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-232-0/+121
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* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
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* moved forward from the old branchMatt Ettus2010-11-112-4/+30
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* occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
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* catch up with tx_policyMatt Ettus2010-08-193-5510/+23
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* Merge branch 'ise12' into u1eMatt Ettus2010-07-193-0/+109
|\ | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
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| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
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| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
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* | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-145-78/+49
|/ | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
* first attempt at cleaning up the build systemMatt Ettus2010-06-1022-0/+7551
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