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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:17:47 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 19:06:59 -0800 |
| commit | ffdb0ba08887e9bf9df600138d1e209e37d043db (patch) | |
| tree | 3b530fd02d67522c0f96ec4b5afbb9c41fea633d /usrp2/fifo | |
| parent | a9390f66b72453adefa642919e5a56056bc28655 (diff) | |
| download | uhd-ffdb0ba08887e9bf9df600138d1e209e37d043db.tar.gz uhd-ffdb0ba08887e9bf9df600138d1e209e37d043db.tar.bz2 uhd-ffdb0ba08887e9bf9df600138d1e209e37d043db.zip | |
packet_router: mux the crossbar input after the protocol framer
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/packet_router.v | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 0ccf665f9..810d0aada 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -209,7 +209,7 @@ module packet_router fifo36_mux _com_output_combiner1( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), + .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); @@ -564,6 +564,9 @@ module packet_router wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid; wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready; + wire [35:0] _com_out_data; + wire _com_out_valid, _com_out_ready; + fifo36_to_fifo19 udp_fifo36_to_fifo19 (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), @@ -590,7 +593,14 @@ module packet_router fifo19_to_fifo36 udp_fifo19_to_fifo36 (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(com_out_data), .f36_src_rdy_o(com_out_valid), .f36_dst_rdy_i(com_out_ready) ); + .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + + fifo36_mux com_out_mux( + .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready), + .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready), + .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready) + ); //////////////////////////////////////////////////////////////////// // Assign debugs |