Merge branch 'ise12' into u1e

* ise12:
  move declaration ahead of use
  put run_tx and run_rx on the displayed LEDs
  remove warnings
  add mux and demux to build
  mux multiple fifo streams into one.  Allows priority or round robin
  split fifo into 2 streams based on first line in each packet
  precompute udp checksums
  barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok

3 files changed, 109 insertions, 0 deletions

diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index 22867da7e..c66979132 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -20,4 +20,6 @@ fifo19_to_ll8.v \
 ll8_to_fifo19.v \
 fifo36_to_fifo19.v \
 fifo19_to_fifo36.v \
+fifo36_mux.v \
+fifo36_demux.v \
 ))
diff --git a/usrp2/fifo/fifo36_demux.v b/usrp2/fifo/fifo36_demux.v
new file mode 100644
index 000000000..a54759d4d
--- /dev/null
+++ b/usrp2/fifo/fifo36_demux.v
@@ -0,0 +1,50 @@
+
+// Demux packets from a fifo based on the contents of the first line
+//  If first line matches the parameter and mask, send to data1, otherwise send to data0
+
+module fifo36_demux
+  #(parameter match_data = 0,
+    parameter match_mask = 0)
+   (input clk, input reset, input clear,
+    input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+    output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+    output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+   localparam DMX_IDLE = 0;
+   localparam DMX_DATA0 = 1;
+   localparam DMX_DATA1 = 2;
+   
+   reg [1:0] 	  state;
+
+   wire 	  match = |( (data_i ^ match_data) & match_mask );
+   wire 	  eof = data_i[33];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= DMX_IDLE;
+     else
+       case(state)
+	 DMX_IDLE :
+	   if(src_rdy_i)
+	     if(match)
+	       state <= DMX_DATA1;
+	     else
+	       state <= DMX_DATA0;
+	 DMX_DATA0 :
+	   if(src_rdy_i & dst0_rdy_i & eof)
+	     state <= DMX_IDLE;
+	 DMX_DATA1 :
+	   if(src_rdy_i & dst1_rdy_i & eof)
+	     state <= DMX_IDLE;
+	 default :
+	   state <= DMX_IDLE;
+       endcase // case (state)
+
+   assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i;
+   assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0;
+   assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0;
+
+   assign data0_o = data_i;
+   assign data1_o = data_i;
+   
+endmodule // fifo36_demux
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
new file mode 100644
index 000000000..04ec5abe8
--- /dev/null
+++ b/usrp2/fifo/fifo36_mux.v
@@ -0,0 +1,57 @@
+
+// Mux packets from multiple FIFO interfaces onto a single one.
+//  Can alternate or give priority to one port (port 0)
+//  In prio mode, port 1 will never get access if port 0 is always busy
+
+module fifo36_mux
+  #(parameter prio = 0)
+   (input clk, input reset, input clear,
+    input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+    input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+    output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   localparam MUX_IDLE0 = 0;
+   localparam MUX_DATA0 = 1;
+   localparam MUX_IDLE1 = 2;
+   localparam MUX_DATA1 = 3;
+   
+   reg [1:0] 	  state;
+
+   wire 	  eof0 = data0_i[33];
+   wire 	  eof1 = data1_i[33];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= MUX_IDLE0;
+     else
+       case(state)
+	 MUX_IDLE0 :
+	   if(src0_rdy_i)
+	     state <= MUX_DATA0;
+	   else if(src1_rdy_i)
+	     state <= MUX_DATA1;
+
+	 MUX_DATA0 :
+	   if(src0_rdy_i & dst_rdy_i & eof0)
+	     state <= prio ? MUX_IDLE0 : MUX_IDLE1;
+
+	 MUX_IDLE1 :
+	   if(src1_rdy_i)
+	     state <= MUX_DATA1;
+	   else if(src0_rdy_i)
+	     state <= MUX_DATA0;
+	   
+	 MUX_DATA1 :
+	   if(src1_rdy_i & dst_rdy_i & eof1)
+	     state <= MUX_IDLE0;
+	 
+	 default :
+	   state <= MUX_IDLE0;
+       endcase // case (state)
+
+   assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
+   assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
+   assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
+   assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i;
+   
+endmodule // fifo36_demux