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* packet_router: added all input/output signals to module, created the comm mux...Josh Blum2010-11-231-6/+19
* packet_router: created com signals (device IO lines that may be ethernet or s...Josh Blum2010-11-231-79/+100
* packet_router: created inspector and added dsp output (however inspection log...Josh Blum2010-11-231-4/+133
* packet_router: connected and created CPU read from interface (slow path in pl...Josh Blum2010-11-231-47/+153
* packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-232-0/+121
* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
* moved forward from the old branchMatt Ettus2010-11-112-4/+30
* occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
* catch up with tx_policyMatt Ettus2010-08-193-5510/+23
* Merge branch 'ise12' into u1eMatt Ettus2010-07-193-0/+109
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| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
* | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-145-78/+49
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* first attempt at cleaning up the build systemMatt Ettus2010-06-1022-0/+7551