uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: added setting regs based simple_i2c_core	Josh Blum	2012-05-30	2	-0/+117
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*	fpga: added some parameterization to settings_fifo_ctrl	Josh Blum	2012-05-30	1	-3/+6
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*	fifo ctrl: Nseries timing meets with a single shortfifo	Josh Blum	2012-04-17	1	-3/+2
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*	usrp: work on meeting timing constraints	Josh Blum	2012-04-10	1	-5/+7
\| \| \| \| \| \|	* fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage
*	spi core: ready logic low one cycle earlier	Josh Blum	2012-03-16	1	-1/+1
\| \| \| \| \| \| \|	FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
*	fifo ctrl: parameterize having a proto header	Josh Blum	2012-03-16	1	-5/+9
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*	fifo ctrl: rename fifo ctrl module and add sid ack param	Josh Blum	2012-03-16	2	-9/+12
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*	fifo ctrl: minor fixes for spi core, swap time define	Josh Blum	2012-03-16	2	-7/+7
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*	fifo ctrl: simplified perfs, added spi clock idle phase	Josh Blum	2012-03-16	2	-13/+21
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*	fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support	Josh Blum	2012-03-16	2	-19/+35
\| \| \| \| \| \| \| \|	Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
*	spi: created simple spi core (sr based)	Josh Blum	2012-03-16	2	-0/+196
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*	fifo ctrl: simplified result packets (no tsf or sid)	Josh Blum	2012-03-16	1	-16/+7
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*	fifo_ctrl: switched to medfifo and separate result fifo	Josh Blum	2012-03-16	1	-90/+120
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*	fifo_ctrl: clear settings reg, and flow control	Josh Blum	2012-03-16	2	-5/+7
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*	fifo ctrl: added time compare for timed commands	Josh Blum	2012-03-16	1	-3/+7
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*	srb: created command queue, in and out state machines	Josh Blum	2012-03-16	1	-95/+160
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*	usrp2: added vrt pack/unpacker to fifo ctrl	Josh Blum	2012-03-16	1	-40/+107
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*	usrp2: first pass implementation of fifo control	Josh Blum	2012-03-16	2	-0/+222
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*	dsp_rework: testbench enhancements	Matt Ettus	2012-02-02	1	-11/+34
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*	dsp_rework: more thorough test	Matt Ettus	2012-01-31	1	-8/+20
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*	dsp: 8 to 16 bit conversion for tx side. believed to be functional	Matt Ettus	2012-01-29	1	-12/+36
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*	dsp rework: integrated custom dsp module shells	Josh Blum	2012-01-27	1	-1/+1
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*	dsp rework: implemented dsp changes for other top levels	Josh Blum	2012-01-27	2	-1/+65
\| \| \| \|	added user registers into each toplevel (not used yet)
*	forgot to add gpio atr to makefile source list	Josh Blum	2011-10-26	1	-0/+1
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*	u2/u2p: use new setting_reg based gpios, gets it off of wb	Matt Ettus	2011-10-26	1	-0/+71
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*	dsp_engine fix rst -> reset, default to read address	Matt Ettus	2011-10-26	1	-2/+2
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*	dspengine: insert into the rx chain	Matt Ettus	2011-10-26	2	-1/+3
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*	dsp_engine: new way of doing DSP operations on VITA packets. Example does ↵	Matt Ettus	2011-10-26	3	-0/+556
\| \| \| \|	16 to 8 bit conversion
*	fix warning on dat_o in atr_controller16.v	Josh Blum	2011-08-29	1	-3/+2
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*	fix typo	Matt Ettus	2011-08-26	1	-21/+21
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*	all: tie unused ram inputs to 1 instead of zero, helps routing	Matt Ettus	2011-08-26	1	-21/+21
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*	usrp2: reconnect frontend calibration, timing meets	Josh Blum	2011-08-26	1	-2/+2
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*	connect unused BRAM inputs to 1s to save routing logic	Josh Blum	2011-08-15	1	-1/+1
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*	u2: redo the atr gpio pins, remove some old cruft	Matt Ettus	2011-07-27	1	-45/+31
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*	appease the ISE gods	Matt Ettus	2011-07-19	2	-2/+2
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*	removed wb readback of ATR, allowing it to be synthesized as luts	Matt Ettus	2011-07-19	2	-4/+10
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*	added copyrights	Josh Blum	2011-06-07	60	-0/+1020
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*	u1p: fix bus widths and other warnings	Matt Ettus	2011-05-26	1	-11/+11
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*	modernize the make files, it now compiles. not tested.	Matt Ettus	2011-05-26	1	-0/+1
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*	select bus is 2 bits wide	Nick Foster	2011-05-26	1	-1/+1
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*	add padding into gpif response path	Matt Ettus	2011-05-26	1	-1/+7
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*	pad out packets to a minimum length	Matt Ettus	2011-05-26	1	-1/+10
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*	fixed length command packets	Matt Ettus	2011-05-26	1	-1/+1
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*	give response packets the same format as tx packets	Matt Ettus	2011-05-26	1	-1/+13
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*	successful test	Matt Ettus	2011-05-26	1	-0/+104
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*	old and unused	Matt Ettus	2011-05-26	1	-151/+0
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*	fifo to wb should be functionally complete, needs testing	Matt Ettus	2011-05-26	1	-21/+141
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*	added a loopback control port, will do full wishbone interface later	Matt Ettus	2011-05-26	1	-0/+34
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*	N210: bootram expanded to 16KB (8 BRAMs) and UDP bootloader added	Nick Foster	2011-04-21	1	-98/+143
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*	Merge branch 'master' into next	Matt Ettus	2011-03-27	2	-2/+2
\|\ \| \| \| \| \| \| \| \| \| \| \| \|	* master: u2p: N200 Makefile u1e: use icarus verilog for lint clean up a bunch of warnings and incorrect bus widths