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| author | Matt Ettus <matt@ettus.com> | 2010-10-15 15:47:51 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:20 -0700 | 
| commit | 9ff35c8e1e6b04e191c83ce21e10772969ea4b64 (patch) | |
| tree | 102784a7646624c2d1266608eded71cfdf9b9c37 /usrp2/control_lib | |
| parent | 3a244ca4b5a8d330958882936e8f74fbcf81f0e5 (diff) | |
| download | uhd-9ff35c8e1e6b04e191c83ce21e10772969ea4b64.tar.gz uhd-9ff35c8e1e6b04e191c83ce21e10772969ea4b64.tar.bz2 uhd-9ff35c8e1e6b04e191c83ce21e10772969ea4b64.zip | |
give response packets the same format as tx packets
Diffstat (limited to 'usrp2/control_lib')
| -rw-r--r-- | usrp2/control_lib/fifo_to_wb.v | 14 | 
1 files changed, 13 insertions, 1 deletions
| diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index 21d3945da..5be865a83 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -39,7 +39,9 @@ module fifo_to_wb     localparam RESP_WAIT_READ = 6;     localparam RESP_RCMD = 7;     localparam RESP_RLEN = 8; -   localparam RESP_READ = 9; +   localparam RESP_RADDR_LSW = 9; +   localparam RESP_RADDR_MSW = 10; +   localparam RESP_READ = 11;     reg [3:0] 	  resp_state;     reg 		  rd, wr; @@ -111,6 +113,12 @@ module fifo_to_wb  	     resp_state <= RESP_RLEN;  	 RESP_RLEN :  	   if(resp_dst_rdy) +	     resp_state <= RESP_RADDR_LSW; +	 RESP_RADDR_LSW : +	   if(resp_dst_rdy) +	     resp_state <= RESP_RADDR_MSW; +	 RESP_RADDR_MSW : +	   if(resp_dst_rdy)  	     resp_state <= RESP_READ;  	 RESP_READ :  	   if(resp_dst_rdy & wb_ack_i) @@ -127,6 +135,8 @@ module fifo_to_wb       case(resp_state)         RESP_RCMD : resp_data <= { 2'b01, 8'hAA, seqnum };         RESP_RLEN : resp_data <= { 2'b00, length }; +       RESP_RADDR_LSW : resp_data <= { 2'b00, base_addr }; +       RESP_RADDR_MSW : resp_data <= { 2'b00, 16'd0 };         default : resp_data <= { (count==1), 1'b0, wb_dat_miso };       endcase // case (resp_state) @@ -139,6 +149,8 @@ module fifo_to_wb     assign resp_src_rdy = (resp_state == RESP_RCMD) |  			 (resp_state == RESP_RLEN) | +			 (resp_state == RESP_RADDR_LSW) | +			 (resp_state == RESP_RADDR_MSW) |  			 ((resp_state == RESP_READ) & wb_ack_i);     assign wb_dat_mosi = ctrl_data[15:0]; | 
