| Commit message (Collapse) | Author | Age | Files | Lines |
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This class is a remnant of UHD 3, and is no longer used anywhere. SID is
no longer used at all in UHD, in fact, which means the class did not
represent a valid data structure.
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This change adds detection for setting the correct internal
fpga CHDR IP address when using embedded mode.
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Add an entry for the internal NIC to E320.
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Instead of using hard-coded values, detect the number of liberio
channels, and only offer liberio links if they exist.
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The Python code contained a typo which would cause a call to
get_gpio_srcs() to throw an exception.
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This enables the *gpio_src* APIs for the E320 and the E31x.
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Many small cleanups:
- Fix copyright headers
- Fix superfluous imports
- Pull some constants out of classes where appropriate
- Fix formatting
- Improve/fix some docstrings
- Disable specific Pylint warnings where appropriate
- Global catches use BaseException instead of Exception
- Don't use len() for empty checks
- Make sure to declare all self attributes in __init__ (note: this is
particularly of interest for E310, becuase its regular init happens
outside of __init__)
- Compacted some E310 code that had multi-DB checks
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This assumes an existence of mboard_regs_control in PeriphManagerBase
and implements most TK controls there. All the *_periphs.py files can
now use a common class for registers, including the TK access, but also
git hash, build date, and device ID access.
This also fixes two issues:
- set_timekeeper_time() and set_tick_period() had a bug that would
incorrectly calculate the upper 32 bits of their respective registers.
- N3xx had a bug that would swap around set time now and next PPS. This
got auto-fixed because the common code never had this bug.
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Ethernet now uses the same serialization of the RFNoC stream as all
the other transports.
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Co-Authored-By: Alex Williams <alex.williams@ni.com>
Co-Authored-By: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-Authored-By: Brent Stapleton <brent.stapleton@ettus.com>
Co-Authored-By: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
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Increase to currently shipping rev.
Signed-off-by: michael-west <michael.west@ettus.com>
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This value should be 9 to correspond with the rev J motherboards.
This property was renamed to mboard_last_rev_compat in a previous commit.
But mboard_max_rev is actually a more accurate description,
since it specifies the latest hardware revision that the software
is aware of. I renamed all references back to mboard_max_rev.
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Newer revisions of the E320 and N3xx motherboards use EEPROM version 3,
and store a rev_compat field. The rev_compat is the last revision that
this hardware is compatible with. We now use that instead of simply the
revision.
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- No driver changes required
Signed-off-by: michael-west <michael.west@ettus.com>
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Fixes uhd_usrp_probe FPGA version githash to report the
correct hash and not 'UNKNOWN'.
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Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
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gps_locked should be a bool not int.
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N3xx and E320 were registering GPSDIface names as get_*_sensor instead
of just the sensor name. Fixing this to now register the sensor name.
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- E320 will support only 3.3 V for the front panel GPIO
- Remove other voltage options
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Adding the following sensors:
- Catalina temperature, RSSI, and LO Lock sensors
- GPS lock, time, TPV, and SKY sensors
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
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Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
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