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| author | Brent Stapleton <brent.stapleton@ettus.com> | 2018-08-28 10:15:08 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-09-06 15:59:25 -0700 |
| commit | ec0bf1add38e56381293f7a69f6f02447ed9746d (patch) | |
| tree | ced4af6c2558fdf7d6644c24abcc2a1df761d275 /mpm/python/usrp_mpm/periph_manager/e320.py | |
| parent | 77631f36033c774d5b253d9c8ce8d5cbce569182 (diff) | |
| download | uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.tar.gz uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.tar.bz2 uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.zip | |
e320: Get RFNoC crossbar baseport from FPGA
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/e320.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index 37ed280e1..7c8cd6893 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -32,7 +32,7 @@ E320_DEFAULT_CLOCK_SOURCE = 'internal' E320_DEFAULT_TIME_SOURCE = 'internal' E320_DEFAULT_ENABLE_GPS = True E320_DEFAULT_ENABLE_FPGPIO = True -E320_FPGA_COMPAT = (3, 0) +E320_FPGA_COMPAT = (3, 1) E320_MONITOR_THREAD_INTERVAL = 1.0 # seconds E320_DBOARD_SLOT_IDX = 0 @@ -90,7 +90,6 @@ class e320(ZynqComponents, PeriphManagerBase): 'temp_main_power' : 'get_main_power_temp_sensor', } max_num_dboards = 1 - crossbar_base_port = 2 # It's 2 because 0,1 are SFP,DMA # We're on a Zynq target, so the following two come from the Zynq standard # device tree overlay (tree/arch/arm/boot/dts/zynq-7000.dtsi) @@ -265,6 +264,7 @@ class e320(ZynqComponents, PeriphManagerBase): self.mboard_regs_control.get_build_timestamp() self._check_fpga_compat() self._update_fpga_type() + self.crossbar_base_port = self.mboard_regs_control.get_xbar_baseport() # Init peripherals self.enable_gps( enable=str2bool( |