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path: root/mpm/python/usrp_mpm/periph_manager/e320.py
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* mpm: Factor out transport API into PeriphManagerBaseMartin Braun2022-07-201-48/+0
| | | | | | | | | | | | | All MPM devices use identical implementations of the transport API. Minor differences between the actual lines of code in the various transport adapters are due to minor optimizations, such as hard-coding 'udp' as the only valid transport type for the N3xx series. This change moves the implementation of the transport API calls (get_chdr_link_options() and get_chdr_link_types()) into PeriphManagerBase. The class attributes _xport_adapter_mgrs is also declared in that class, but defining them is left up to the individual device implementations.
* mpm: e3xx: Fix get_sync_sources() APIMartin Braun2022-03-281-0/+19
| | | | | | | | | | | | | | get_sync_sources() was not implemented for E31x and E320. Because UHD assumes this exists, calling this would cause an error like this: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=e3xx") >>> U.get_sync_sources(0) Traceback (most recent call last): File "<input>", line 1, in <module> U.get_sync_sources(0) RuntimeError: rpc::timeout: Timeout of 2000ms while calling RPC function 'get_sync_sources'
* mpm: Make default clock/time source values state-lessMartin Braun2022-03-281-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the default clock/time source is whatever the user configured in the last session. This fixes the scenario were you have any MPM device and do this: $ benchmark_rate --args $args,clock_source=external But whoops! You forgot to attach an external 10 MHz. PLL lock fails, nothing works. No worries, you run it again: $ benchmark_rate --args $args With the previous behaviour, this would retain the setting to 'external', because there's nothing to overwrite it. You would need to append `clock_source=internal` to get a working device again. Calling multi_usrp::set_clock_source("internal"), or a similar API call, might not be sufficient because the PLL lock failure might crash the program before updating the clock source is possible. The problem with this is twofold: - All non-MPM devices behave differently, i.e., they have a fixed default ('internal') which is always applied if no other option is given. This is an internal inconsistency. - Some applications (like gr-uhd's GRC bindings) simply don't set a clock/time source when selecting a "default", or they try and update the clock/time source using the API calls. Therefore, we align the behaviour of MPM devices with the other devices, and fall back to an internal source if nothing else is provided.
* mpm: e3xx: Simplify code referring to self.dboardsMartin Braun2022-03-281-28/+17
| | | | | | | | | | | | The E31x and E320 devices have one virtual daughterboard, and it is always present. This is different from N3xx, which is where the MPM code for these devices is based upon. During the E3xx initialization, we make sure that our single "daughterboard" exists and is responsive. That means we can remove some code that tests for the availability and number of daughterboards, which we need on N3xx (which works with zero, one, or two daughterboards). This also allows us some minor deduplication of code.
* mpm: e3xx: Fix Pylint warnings in periph_mgr classesMartin Braun2022-03-171-6/+4
| | | | | | - Whitespace - Long lines - Superfluous imports
* e320: mpm: Remove monitor threadMartin Braun2022-02-241-34/+0
| | | | | This thread is a vestige from copy & pasting N310 code, it does absolutely nothing but occupy resources.
* mpm: eeprom: Improve E320 and N3x0 EEPROM code/commentsMartin Braun2022-02-161-0/+5
| | | | | | - Fix some Pylint warnings in eeprom.py - Improve comments in n3xx.py and e320.py regarding rev_compat values in EEPROM
* mpm: Remove SID classMartin Braun2020-08-071-1/+0
| | | | | | This class is a remnant of UHD 3, and is no longer used anywhere. SID is no longer used at all in UHD, in fact, which means the class did not represent a valid data structure.
* mpm: Default virtual NIC CHDR IP selectionSteven Koo2020-07-301-1/+5
| | | | | This change adds detection for setting the correct internal fpga CHDR IP address when using embedded mode.
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-241-1/+1
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* uhd: remove liberioRobertWalstab2020-07-201-3/+0
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* mpm: remove class E320XportMgrLiberioRobertWalstab2020-07-161-12/+5
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* mpm: support forwarding CHDR packetsRobertWalstab2020-07-161-0/+4
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* mpm: Enable internal NIC on the E320Alex Williams2020-07-161-0/+4
| | | | Add an entry for the internal NIC to E320.
* mpm: Add support for internal Ethernet interfaceAndrew Lynch2020-07-161-0/+1
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* mpm: Detect number of liberio channelsAlex Williams2020-07-161-4/+5
| | | | | Instead of using hard-coded values, detect the number of liberio channels, and only offer liberio links if they exist.
* e320/e310: Fix get_gpio_srcs() MPM API callMartin Braun2020-02-261-1/+1
| | | | | The Python code contained a typo which would cause a call to get_gpio_srcs() to throw an exception.
* fixup! mpm: e320/e310: Expose APIs to drive GPIO source via UHDMartin Braun2020-01-281-1/+1
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* mpm: e320/e310: Expose APIs to drive GPIO source via UHDMartin Braun2020-01-231-34/+67
| | | | This enables the *gpio_src* APIs for the E320 and the E31x.
* mpm: Clean up code, improve Pylint scoreMartin Braun2019-11-261-4/+10
| | | | | | | | | | | | | | | | Many small cleanups: - Fix copyright headers - Fix superfluous imports - Pull some constants out of classes where appropriate - Fix formatting - Improve/fix some docstrings - Disable specific Pylint warnings where appropriate - Global catches use BaseException instead of Exception - Don't use len() for empty checks - Make sure to declare all self attributes in __init__ (note: this is particularly of interest for E310, becuase its regular init happens outside of __init__) - Compacted some E310 code that had multi-DB checks
* mpm: Move common mboard regs code to common locationMartin Braun2019-11-261-70/+0
| | | | | | | | | | | | | This assumes an existence of mboard_regs_control in PeriphManagerBase and implements most TK controls there. All the *_periphs.py files can now use a common class for registers, including the TK access, but also git hash, build date, and device ID access. This also fixes two issues: - set_timekeeper_time() and set_tick_period() had a bug that would incorrectly calculate the upper 32 bits of their respective registers. - N3xx had a bug that would swap around set time now and next PPS. This got auto-fixed because the common code never had this bug.
* rfnoc: Unify endianness of transportsAlex Williams2019-11-261-1/+1
| | | | | Ethernet now uses the same serialization of the RFNoC stream as all the other transports.
* x300/mpmd: Port all RFNoC devices to the new RFNoC frameworkMartin Braun2019-11-261-68/+120
| | | | | | | Co-Authored-By: Alex Williams <alex.williams@ni.com> Co-Authored-By: Sugandha Gupta <sugandha.gupta@ettus.com> Co-Authored-By: Brent Stapleton <brent.stapleton@ettus.com> Co-Authored-By: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
* MPM: Increase E320 max rev to 4michael-west2019-09-241-1/+1
| | | | | | Increase to currently shipping rev. Signed-off-by: michael-west <michael.west@ettus.com>
* mpm: fixed mboard_max_revision valueMatthew Crymble2019-09-241-1/+1
| | | | | | | | This value should be 9 to correspond with the rev J motherboards. This property was renamed to mboard_last_rev_compat in a previous commit. But mboard_max_rev is actually a more accurate description, since it specifies the latest hardware revision that the software is aware of. I renamed all references back to mboard_max_rev.
* mpm: Change SW/HW compat check to use last_rev_compatTrung Tran2019-05-101-1/+1
| | | | | | | Newer revisions of the E320 and N3xx motherboards use EEPROM version 3, and store a rev_compat field. The rev_compat is the last revision that this hardware is compatible with. We now use that instead of simply the revision.
* E320: Add support for rev Emichael-west2019-05-021-1/+1
| | | | | | - No driver changes required Signed-off-by: michael-west <michael.west@ettus.com>
* e320: add fpga_version_hash to e320 device infoSugandha Gupta2019-02-191-0/+2
| | | | | Fixes uhd_usrp_probe FPGA version githash to report the correct hash and not 'UNKNOWN'.
* n3xx: init peripherals before loading FPGATrung Tran2019-02-011-1/+3
| | | | | | | | | Issue: Current code loads FPGA too early while many essential peripherals such as net clocks are not brought up. This change will make sure those are got init before FPGA loaded. Signed-off-by: Trung Tran<trung.tran@ettus.com>
* mpm: n3xx: e320: Add bridge mode supportRyan Marlow2019-01-171-1/+1
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* mpm:e320: fixup gps_locked typeTrung Tran2018-11-131-1/+1
| | | | gps_locked should be a bool not int.
* n3xx: e320: fixing GPSDIface sensor namesBrent Stapleton2018-09-261-1/+1
| | | | | N3xx and E320 were registering GPSDIface names as get_*_sensor instead of just the sensor name. Fixing this to now register the sensor name.
* e320: Get RFNoC crossbar baseport from FPGABrent Stapleton2018-09-061-2/+2
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* e320: Add all 5 temp sensors, fan sensor and rssi sensors per channelSugandha Gupta2018-08-091-17/+40
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* e320: Fix front panel gpio to support 3.3VSugandha Gupta2018-07-311-9/+9
| | | | | - E320 will support only 3.3 V for the front panel GPIO - Remove other voltage options
* e320: Add 'ref_locked' sensor to mboard sensorsSugandha Gupta2018-07-311-0/+14
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* e320: mpm: Add dboard and mboard sensorsSugandha Gupta2018-07-181-17/+60
| | | | | | | | Adding the following sensors: - Catalina temperature, RSSI, and LO Lock sensors - GPS lock, time, TPV, and SKY sensors Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
* mpm: initial commit of E320 codeBrent Stapleton2018-07-181-0/+671
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-01 18:52:12 +0000