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* Merge branch 'maint'Martin Braun2015-07-148-35/+66
|\ | | | | | | | | | | | | | | | | | | Conflicts: fpga-src host/CMakeLists.txt host/cmake/Modules/UHDVersion.cmake host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * 3.8.5 Release CandidateMartin Braun2015-07-142-3/+3
| | | | | | | | | | | | - Updated fpga-src - Updated version strings - Updated images package
| * x300: Added max hw rev checkingMartin Braun2015-07-142-0/+11
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| * e3xx: Fixup for idle image to follow naming convention.Moritz Fischer2015-07-141-2/+2
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * examples: Improved tx_waveform multi-channel syncMartin Braun2015-07-141-8/+18
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| * e3xx: Bump compat number from 6 -> 8.Moritz Fischer2015-07-141-1/+1
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * e3xx: Increase TX buffer size to PAGE_SIZE.Moritz Fischer2015-07-141-1/+1
| | | | | | | | | | | | | | | | This was originally limited because it performed poor, however, with refactoring that has been done since release, this now gives better performance. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * e3xx: Load idle image on shutdown.Moritz Fischer2015-07-142-23/+33
| | | | | | | | | | | | | | | | | | | | This commit will have UHD load the idle fpga image on destruction of e300_impl. Note: This requires usrp_e310_idle_fpga.bit to be present in the UHD images directory. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
| * b200: Bumped FPGA compat number to 8 for releaseAshish Chaudhari2015-07-141-1/+1
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* | x300: Added retry mechanism to ADC capture delay self-calAshish Chaudhari2015-07-141-47/+65
| | | | | | | | | | - If the self-cal fails, UHD waits for 2 sec for the ADC temp to stabilize and retries the self-cal
* | x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
| | | | | | | | - Characterized over process and temperature
* | b2xx: Added side-channel utility for FX3 debuggingBalint Seeber2015-07-141-0/+644
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* | octoclock: fixed install directory for relevant headersNicholas Corgan2015-07-141-2/+2
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* | e3xx: Bump compat number to match change on maint.Moritz Fischer2015-07-131-1/+1
| | | | | | | | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* | ad9361: Update Tx Quad Cal to match current gain tablesTom Tsou2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes issue #828 "B200: Tx quadrature calibration regression in master" Following commit added new gain table settings to reflect updated values from ADI. Gain indices used by Tx Quad Cal were not matched to accommodate the new tables. 2b06c38 "b2xx: dc offset and iq imbalance correction control" Requirement for Tx Quad Cal is for TIA gain and analog LPF gain to be set at 0 dB, or 0x20 in the gain table. Final effect is a dramatic decrease in Tx DC offset and quadrature image. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | ad9361: Prevent positive loop gain on Rx quadrature trackingTom Tsou2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch fixes a portion of #807 "B210: severe distortion on In-phase data for some gain settings" ADI recommends that the "Prevent Pos Loop Gain" setting be enabled to prevent the Rx quadrature tracking loop from becoming unstable at low power levels. ADI Linux kernel driver also reflects this setting. We do not follow the ADI recommendation. Adjust accordingly. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | ad9361: Invert phase on Rx LNA bypass pathTom Tsou2015-07-131-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch resolves issue #823 "B200: Receive RF DC calibration makes calibration worse below 34 dB" According to ADI reference documents, enabling any of the 3 LNA's in the receive path causes a 180 degree phase shift. Correspondingly, we invert the LNA bypass path (gain indices below 34 dB) to match. Testing, however, reveals that one of these statements or the polarity inversion setting itself is false. Disabling the switch results in expected behavior and proper phase alignment. Overall effect is up to 60 dB of DC offset suppression ahead of the Rx analog LPF. This reduces the problematic dependency on active baseband tracking and may resolves multiple tracking stability issues. Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
* | x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
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* | OctoClock bugfixesNicholas Corgan2015-07-094-54/+77
| | | | | | | | | | | | * Bumped compatibility version to 3 * firmware: Ethernet, clkdist bugfixes * lib: fixed invalid rev detection
* | Merge branch 'master' into x300/rev7_supportAshish Chaudhari2015-07-093-8/+17
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| * | Merge branch 'maint'Martin Braun2015-07-082-3/+3
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| | * B200: New AD9361 I/O timing programming to work with new b200_io.v logic design.Ian Buckley2015-07-082-3/+3
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| * | Merge branch 'maint'Martin Braun2015-07-081-5/+14
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| | * docs: tweak OSX build from source advice to have more obvious NOTEs, per uhd ↵Michael Dickens2015-07-061-5/+14
| | | | | | | | | | | | issue #37
* | | Merge branch 'master' into x300/rev7_supportAshish Chaudhari2015-07-0714-288/+47
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| * | Merge branch 'maint'Martin Braun2015-07-012-6/+7
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| | * b200: Codec loopback test now throws on failure.Martin Braun2015-07-011-5/+6
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| | * docs: Minor manual updateMartin Braun2015-06-301-1/+1
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| * | uhd: Removed the ORC dependencyMartin Braun2015-07-018-252/+6
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| * | ad9361: brought in Boost.Assign std::map workaround for MSVC 2013Nicholas Corgan2015-06-291-4/+11
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| * | Merge branch 'maint'Martin Braun2015-06-291-1/+1
| |\| | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.cpp
| | * b200: Modify initialization sequence to avoid warningsMartin Braun2015-06-292-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will set the actual default rate to an integer factor of whatever the tick rate is, but leave the property tree value at zero. This avoids warnings if the chosen tick rate is not a multiple of the previous default rate, but also returns a zero value for the rate when it has not been initialized, allowing the user to probe if the value has not yet been set.
| | * msvc: fixed default DLL resource templateNicholas Corgan2015-06-251-1/+1
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| * | b200: Modify initialization sequence to avoid warningsMartin Braun2015-06-293-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will set the actual default rate to an integer factor of whatever the tick rate is, but leave the property tree value at zero. This avoids warnings if the chosen tick rate is not a multiple of the previous default rate, but also returns a zero value for the rate when it has not been initialized, allowing the user to probe if the value has not yet been set.
| * | Merge branch 'maint'Martin Braun2015-06-238-31/+424
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| | * docs: Fixed FPGA manual auto-buildingMartin Braun2015-06-232-3/+2
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| | * doc: Integrated install instructions into manualMartin Braun2015-06-237-28/+422
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* | | x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
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* | | x300: Bumped FPGA compat number to 11Ashish Chaudhari2015-07-071-1/+1
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* | | x300: Added self-cal to tune ADC source-sync data delaysAshish Chaudhari2015-07-073-50/+160
| | | | | | | | | | | | | | | | | | | | | - Self-calibration routine steps through various values of IDELAY taps on the SS data bits to detect metastability in the capture interface and computes an ideal delay tap value - Self calibration is triggered at device creation
* | | x300: Added self-cal to tune ADC clk delay at startupAshish Chaudhari2015-07-013-33/+239
| | | | | | | | | | | | | | | | | | | | | | | | - Self-calibration routine steps through various values of LMK delay to detect metastability in the SSCLK -> radio_clk crossing and computes an ideal delay for the ADC clock. - Self calibration is triggered at startup if the self_cal_adc_delay device arg is specified
* | | x300: Added set/get_clock_delay to x300_clock_ctrlAshish Chaudhari2015-07-013-18/+245
| | | | | | | | | | | | | | | | | | | | | - This function allows delaying divider pairs using the digital and analog delay blocks in the LMK divider - ctrl object caches delay for later retrieval - Minor fixes to LMK regmap
* | | uhd: Added soft_register header-only util libraryAshish Chaudhari2015-06-291-0/+312
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* | | docs: Fixed FPGA manual auto-buildingMartin Braun2015-06-292-3/+2
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* | | doc: Integrated install instructions into manualMartin Braun2015-06-297-28/+422
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* | Merge branch 'maint'Martin Braun2015-06-232-3/+4
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| * docs: added missing parameter descriptionsNicholas Corgan2015-06-222-3/+4
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* | multi_usrp: doxygen fixesNicholas Corgan2015-06-221-4/+2
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* | cmake: allow for custom DLL resource fileNicholas Corgan2015-06-221-1/+17
| | | | | | | | | | * Use -DCUSTOM_RC_FILE=(filepath) option to use custom RC file * Defaults to host/lib/uhd.rc.in if none specified
* | Merge branch 'maint'Martin Braun2015-06-221-3/+4
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