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These APIs will be moved to a non-public API in the future and should no
longer be used in user applications.
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For invalid dboard revisions stored in the EEPROM, provide a better
error message.
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The function was directly accessing the error message cache, bypassing
locks, and thus could be faulty if being called the same time as another
UHD component would update the error string.
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Specifically, remove set_tx_dc_offset() and set_tx_iq_balance() calls
that require doubles, and were given bools.
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This adds a zero copy transport using the liberio library.
Currently supported API version for liberio is 0.3, this might
still very much break, since the library is still in development.
So far nobody uses it UHD so we might as well merge it.
Signed-off-by: Alex Williams <alex.williams@ni.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The file was missing a .cpp suffix for the dma_fifo_block_ctrl_impl
file, somehow CMake was being smart and inferring the filetype.
Be explicit.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The existence of SSSE3 intrinsic headers is not a sufficient
condition that SSSE3 support is available, which may lead to
'illegal instruction' runtime failuire on some platforms. Major
OS distributions (Ubuntu, Fedora, etc.) include x86_64
intrinsic headers, though the underlying architecture may or
may not support the instruction set.
Assuming SSE2 availability is safe as instructions are present on
all x86_64 architectures for which instrinsic headers would be
present. The same cannot be said for SSSE3.
Issue: #1761
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Implementation uses SSSE3 intructions to perform 12-bit
sample pack/unpack operations to/from standard 16 and 32
bit host values. Input/output shuffle orderings for a
single 128-bit SSE register with 16-bit integers shown
below.
16-bit interleaved I/Q
---------------------------------------
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 | Input
---------------------------------------
| 127 0 |
12-bit packed I/Q byteswapped
-----------------------
| I0 | Q0 | I1 | 0
|-----------------------|
| I1 | Q1 | I2 | Q2 | Output
|-----------------------|
| Q2 | I3 | Q3 |
|-----------------------|
| Unused | 3
-----------------------
31 0
Fixes: #1740, #966
Related: #1739
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- Updated version string
- Updated fpga-src submodule
- Updated CHANGELOG
- Updated images package
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Create missing sc12-sc16 and sc16-sc12 type converters. To avoid
replicating the full sc12 converter class object, overload the
converter calls with C++11 std::enable_if metafunctions. When
used with std::is_floating and std::is_integral templates, this
allow a single template interface with compile time function
selection and static type checking.
Note the below std::enable_if interface is confusing, but quite
effective in this case.
typename enable_if<is_floating_point<type>::value>::type* = NULL
Fixes: #966
Related: #967, #1721
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for acceptable rounding
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Setting daughterboard clock rate while using UBX on X300 caused an error. Added handling, now throws a warning that the phase will vary.
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Loopback FIFOs ("SRAM FIFOs") only have a single channel, unlike the
DRAM FIFOs (and that's also the reason why we have full bandwdith
between all channels using those). We thus need to ensure that every TX
stream gets its own SRAM FIFO.
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One does not simply free() stack / automatic variables.
Please `man 3 strdup()`.
Signed-off-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Disable halfband HB3 (shortest and closest filter to the ADC) and
enable HB2 (larger and second closest filter to the ADC). This
significantly reduces HB excess bandwidth rolloff and reduces
the effective noise floor by ~20 dB at rates above 58 MHz.
The filter change has no effect at clock rates below 58 MHz.
Fixes #1542 "Significant raise in noise floor using MCR above 58MHz"
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USRP1 and USRP2 used tasks that relied on Boost thread interruption
mechanisms. These were replaced with explicit atomics.
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daughterboard selection/compatibility.
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