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authorMartin Braun <martin.braun@ettus.com>2015-07-14 14:51:14 -0700
committerMartin Braun <martin.braun@ettus.com>2015-07-14 14:51:14 -0700
commit7c6bc34f625e3945458a0a2a281850513a02ef08 (patch)
tree0e34c196d4aceae4cae6d7e22708ded67f558c31 /host
parentbb940ccabb94daa685b4869f44c00844eeeb905b (diff)
parent5f4470a8fb340677f2d0b557f4670bc7506fc38a (diff)
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Merge branch 'maint'
Conflicts: fpga-src host/CMakeLists.txt host/cmake/Modules/UHDVersion.cmake host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
Diffstat (limited to 'host')
-rw-r--r--host/CMakeLists.txt4
-rw-r--r--host/examples/tx_waveforms.cpp26
-rw-r--r--host/lib/usrp/b200/b200_impl.hpp2
-rw-r--r--host/lib/usrp/e300/e300_defaults.hpp2
-rw-r--r--host/lib/usrp/e300/e300_impl.cpp51
-rw-r--r--host/lib/usrp/e300/e300_impl.hpp5
-rw-r--r--host/lib/usrp/x300/x300_fw_common.h1
-rw-r--r--host/lib/usrp/x300/x300_impl.cpp10
8 files changed, 66 insertions, 35 deletions
diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index 31ca0172c..dfe2e4f6b 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -284,8 +284,8 @@ UHD_INSTALL(FILES
#{{{IMG_SECTION
# This section is written automatically by /images/create_imgs_package.py
# Any manual changes in here will be overwritten.
-SET(UHD_IMAGES_MD5SUM "492f47ed0705b6b63238307f6e20e2a3")
-SET(UHD_IMAGES_DOWNLOAD_SRC "uhd-images_003.009.git-184-gf2337d6f.zip")
+SET(UHD_IMAGES_MD5SUM "eb2d694e0444f02752a988d14488064e")
+SET(UHD_IMAGES_DOWNLOAD_SRC "uhd-images_003.008.005-rc1.zip")
#}}}
########################################################################
diff --git a/host/examples/tx_waveforms.cpp b/host/examples/tx_waveforms.cpp
index 9254c3b24..942b5df7b 100644
--- a/host/examples/tx_waveforms.cpp
+++ b/host/examples/tx_waveforms.cpp
@@ -178,15 +178,17 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
std::vector<std::complex<float> > buff(spb);
std::vector<std::complex<float> *> buffs(channel_nums.size(), &buff.front());
- //setup the metadata flags
- uhd::tx_metadata_t md;
- md.start_of_burst = true;
- md.end_of_burst = false;
- md.has_time_spec = true;
- md.time_spec = uhd::time_spec_t(0.1);
-
std::cout << boost::format("Setting device timestamp to 0...") << std::endl;
- usrp->set_time_now(uhd::time_spec_t(0.0));
+ if (channel_nums.size() > 1) {
+ // This is the worst-case setup scenario, because this example has to
+ // work for all configurations. set_time_now() and set_time_next_pps()
+ // might also work, depending on what USRPs are being used, and can
+ // accelerate the setup. To keep this example generic, we use
+ // set_time_unknown_pps() to guarantee synchronization.
+ usrp->set_time_unknown_pps(uhd::time_spec_t(0.0));
+ } else {
+ usrp->set_time_now(uhd::time_spec_t(0.0));
+ }
//Check Ref and LO Lock detect
std::vector<std::string> sensor_names;
@@ -211,6 +213,14 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
std::signal(SIGINT, &sig_int_handler);
std::cout << "Press Ctrl + C to stop streaming..." << std::endl;
+ // Set up metadata. We start streaming a bit in the future
+ // to allow MIMO operation:
+ uhd::tx_metadata_t md;
+ md.start_of_burst = true;
+ md.end_of_burst = false;
+ md.has_time_spec = true;
+ md.time_spec = usrp->get_time_now() + uhd::time_spec_t(0.1);
+
//send data until the signal handler gets called
while(not stop_signal_called){
//fill the buffer with the waveform
diff --git a/host/lib/usrp/b200/b200_impl.hpp b/host/lib/usrp/b200/b200_impl.hpp
index 57c68be71..1cc01f8a6 100644
--- a/host/lib/usrp/b200/b200_impl.hpp
+++ b/host/lib/usrp/b200/b200_impl.hpp
@@ -47,7 +47,7 @@
#include "recv_packet_demuxer_3000.hpp"
static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 7;
static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0;
-static const boost::uint16_t B200_FPGA_COMPAT_NUM = 7;
+static const boost::uint16_t B200_FPGA_COMPAT_NUM = 9;
static const double B200_BUS_CLOCK_RATE = 100e6;
static const double B200_DEFAULT_TICK_RATE = 32e6;
static const double B200_DEFAULT_FREQ = 100e6; // Hz
diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp
index 7a8d49719..41e8453c4 100644
--- a/host/lib/usrp/e300/e300_defaults.hpp
+++ b/host/lib/usrp/e300/e300_defaults.hpp
@@ -41,7 +41,7 @@ static const std::string DEFAULT_CLOCK_SRC = "internal";
static const size_t DEFAULT_RX_DATA_FRAME_SIZE = 4096;
static const size_t DEFAULT_RX_DATA_NUM_FRAMES = 32;
-static const size_t DEFAULT_TX_DATA_FRAME_SIZE = 2048;
+static const size_t DEFAULT_TX_DATA_FRAME_SIZE = 4096;
static const size_t DEFAULT_TX_DATA_NUM_FRAMES = 32;
static const size_t DEFAULT_CTRL_FRAME_SIZE = 64;
diff --git a/host/lib/usrp/e300/e300_impl.cpp b/host/lib/usrp/e300/e300_impl.cpp
index 231816fe8..de2357100 100644
--- a/host/lib/usrp/e300/e300_impl.cpp
+++ b/host/lib/usrp/e300/e300_impl.cpp
@@ -284,32 +284,36 @@ e300_impl::e300_impl(const uhd::device_addr_t &device_addr)
// load the fpga image
////////////////////////////////////////////////////////////////////
if (_xport_path == AXI) {
- if (not device_addr.has_key("no_reload_fpga")) {
+ _do_not_reload = device_addr.has_key("no_reload_fpga");
+ if (not _do_not_reload) {
// Load FPGA image if provided via args
- if (device_addr.has_key("fpga")) {
- common::load_fpga_image(device_addr["fpga"]);
- // Else load the FPGA image based on the product ID
- } else {
- //extract the FPGA path for the e300
- const boost::uint16_t pid = boost::lexical_cast<boost::uint16_t>(
+ const boost::uint16_t pid = boost::lexical_cast<boost::uint16_t>(
device_addr["product"]);
- std::string fpga_image;
- switch(e300_eeprom_manager::get_mb_type(pid)) {
- case e300_eeprom_manager::USRP_E310_MB:
- fpga_image = find_image_path(E310_FPGA_FILE_NAME);
- break;
- case e300_eeprom_manager::USRP_E300_MB:
- fpga_image = find_image_path(E300_FPGA_FILE_NAME);
- break;
- case e300_eeprom_manager::UNKNOWN:
- default:
- UHD_MSG(warning) << "Unknown motherboard type, loading e300 image."
+
+ std::string fpga_image;
+
+ //extract the FPGA path for the e300
+ switch(e300_eeprom_manager::get_mb_type(pid)) {
+ case e300_eeprom_manager::USRP_E310_MB:
+ fpga_image = device_addr.cast<std::string>("fpga",
+ find_image_path(E310_FPGA_FILE_NAME));
+ _idle_image = find_image_path(E310_FPGA_IDLE_FILE_NAME);
+ break;
+ case e300_eeprom_manager::USRP_E300_MB:
+ fpga_image = device_addr.cast<std::string>("fpga",
+ find_image_path(E300_FPGA_FILE_NAME));
+ _idle_image = find_image_path(E300_FPGA_IDLE_FILE_NAME);
+ break;
+ case e300_eeprom_manager::UNKNOWN:
+ default:
+ UHD_MSG(warning) << "Unknown motherboard type, loading e300 image."
<< std::endl;
- fpga_image = find_image_path(E300_FPGA_FILE_NAME);
- break;
- }
- common::load_fpga_image(fpga_image);
+ fpga_image = device_addr.cast<std::string>("fpga",
+ find_image_path(E300_FPGA_FILE_NAME));
+ _idle_image = find_image_path(E300_FPGA_IDLE_FILE_NAME);
+ break;
}
+ common::load_fpga_image(fpga_image);
}
}
@@ -623,7 +627,8 @@ uhd::sensor_value_t e300_impl::_get_fe_pll_lock(const bool is_tx)
e300_impl::~e300_impl(void)
{
- /* NOP */
+ if (_xport_path == AXI and not _do_not_reload)
+ common::load_fpga_image(_idle_image);
}
void e300_impl::_enforce_tick_rate_limits(
diff --git a/host/lib/usrp/e300/e300_impl.hpp b/host/lib/usrp/e300/e300_impl.hpp
index 21aef215d..c530a5d72 100644
--- a/host/lib/usrp/e300/e300_impl.hpp
+++ b/host/lib/usrp/e300/e300_impl.hpp
@@ -51,6 +51,9 @@ namespace uhd { namespace usrp { namespace e300 {
static const std::string E300_FPGA_FILE_NAME = "usrp_e300_fpga.bit";
static const std::string E310_FPGA_FILE_NAME = "usrp_e310_fpga.bit";
+static const std::string E300_FPGA_IDLE_FILE_NAME = "usrp_e300_fpga_idle.bit";
+static const std::string E310_FPGA_IDLE_FILE_NAME = "usrp_e310_fpga_idle.bit";
+
static const std::string E300_TEMP_SYSFS = "iio:device0";
static const std::string E300_SPIDEV_DEVICE = "/dev/spidev0.1";
static const std::string E300_I2CDEV_DEVICE = "/dev/i2c-0";
@@ -285,6 +288,8 @@ private: // members
e300_eeprom_manager::sptr _eeprom_manager;
uhd::transport::zero_copy_xport_params _data_xport_params;
uhd::transport::zero_copy_xport_params _ctrl_xport_params;
+ std::string _idle_image;
+ bool _do_not_reload;
gpio_t _misc;
gps::ublox::ubx::control::sptr _gps;
};
diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h
index 00eafe091..e8b178f20 100644
--- a/host/lib/usrp/x300/x300_fw_common.h
+++ b/host/lib/usrp/x300/x300_fw_common.h
@@ -29,6 +29,7 @@
extern "C" {
#endif
+#define X300_MAX_HW_REV 6
#define X300_FW_COMPAT_MAJOR 4
#define X300_FW_COMPAT_MINOR 0
#define X300_FPGA_COMPAT_MAJOR 11
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index ded7e9408..070a5c276 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -622,6 +622,16 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
mb.hw_rev = X300_REV("D");
}
+ UHD_VAR(mb.hw_rev)
+ if (mb.hw_rev > X300_MAX_HW_REV) {
+ throw uhd::runtime_error(str(
+ boost::format("Unsupported board revision number: %d.\n"
+ "The maximum board revision number supported in this version is %d.\n"
+ "Please update your UHD version.")
+ % mb.hw_rev % X300_MAX_HW_REV
+ ));
+ }
+
//Create clock control. NOTE: This does not configure the LMK yet.
initialize_clock_control(mb);
mb.clock = x300_clock_ctrl::make(mb.zpu_spi,