| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
| |
This adds a new option to the "AXI-Stream Data" (axis_data) FPGA
interface type. The new option, "sideband_at_end", can be added to the
output port of a block's YAML description to control whether the
sideband information should be sampled at the end (sideband_at_end: 1)
or the beginning (sideband_at_end: 0) of the AXI-Stream packet.
|
| | |
|
| | |
|
| |
|
|
|
|
|
|
|
|
| |
- Fix mako paths to run from anywhere
- Correct code errors and clean up generated code
- Add support for port parameters
- Add support for axis_data interface
- Fix NoC shell reset handling
- Replace Python functions with Verilog $clog2
- Allow input and output to share port name
|
|
|
This is an initial generator for eRFNoC block.
The script generates the top level block, the shell module, a testbench, and a
Makefile as well as a Makefile.srcs.
To build a block from a yml file one has to invoke
python -c <config> -d <destination folder>
destination folder should be an in tree module folder located in
uhd-fpga/usrp3/lib/erfnoc/blocks
The build tool supports all interface types for control as well as data.
For each interface type there are three templates to generate the variable
block in the top level block and the shell
* declare the wires
* connect the wires
* instantiate the modules
The first two are used in the shell module as well as in the top level block.
The last is for the shell only.
|
