utils: blocktool: Fix blocktool

- Fix mako paths to run from anywhere
- Correct code errors and clean up generated code
- Add support for port parameters
- Add support for axis_data interface
- Fix NoC shell reset handling
- Replace Python functions with Verilog $clog2
- Allow input and output to share port name

18 files changed, 851 insertions, 319 deletions

diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
index ff619b6d9..e866dc210 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
@@ -1,15 +1,22 @@
-<%page args="num_inputs, num_outputs"/>
-
-%for idx, input in enumerate(config['data']['inputs']):
-  .m_${input}_chdr_tdata(${input}_chdr_tdata),
-  .m_${input}_chdr_tlast(${input}_chdr_tlast),
-  .m_${input}_chdr_tvalid(${input}_chdr_tvalid),
-  .m_${input}_chdr_tready(${input}_chdr_tready)${"," if (idx < num_inputs -1) or (num_outputs > 0) else ""}
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXIS-CHDR Clock and Reset
+    .axis_chdr_clk (axis_chdr_clk),
+    .axis_chdr_rst (axis_chdr_rst),
+    // AXIS-CHDR to User Logic
+%for idx, port_name in enumerate(config['data']['inputs']):
+    .m_${port_name}_chdr_tdata  (m_${port_name}_chdr_tdata),
+    .m_${port_name}_chdr_tlast  (m_${port_name}_chdr_tlast),
+    .m_${port_name}_chdr_tvalid (m_${port_name}_chdr_tvalid),
+    .m_${port_name}_chdr_tready (m_${port_name}_chdr_tready)${"," if (idx < num_inputs -1) or (num_outputs > 0) else ""}
 %endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  .s_${output}_chdr_tdata(${output}_chdr_tdata),
-  .s_${output}_chdr_tlast(${output}_chdr_tlast),
-  .s_${output}_chdr_tvalid(${output}_chdr_tvalid),
-  .s_${output}_chdr_tready(${output}_chdr_tready)${"," if (idx < num_outputs -1) else ""}
+    // AXIS-CHDR from User Logic
+%for idx, port_name in enumerate(config['data']['outputs']):
+    .s_${port_name}_chdr_tdata  (s_${port_name}_chdr_tdata),
+    .s_${port_name}_chdr_tlast  (s_${port_name}_chdr_tlast),
+    .s_${port_name}_chdr_tvalid (s_${port_name}_chdr_tvalid),
+    .s_${port_name}_chdr_tready (s_${port_name}_chdr_tready)${"," if (idx < num_outputs -1) else ""}
 %endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
index bcb23dff6..299d8d7c5 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
@@ -1,41 +1,114 @@
-%for idx, input in enumerate(config['data']['inputs']):
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_chdr_data #(
+      .CHDR_W (CHDR_W)
+    ) chdr_to_chdr_data_in_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_chdr_tdata  (m_${port_name}_chdr_tdata[i*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_${port_name}_chdr_tlast[i]),
+      .m_axis_chdr_tvalid (m_${port_name}_chdr_tvalid[i]),
+      .m_axis_chdr_tready (m_${port_name}_chdr_tready[i]),
+      .flush_en           (data_i_flush_en),
+      .flush_timeout      (data_i_flush_timeout),
+      .flush_active       (data_i_flush_active[${port_index}+i]),
+      .flush_done         (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
   chdr_to_chdr_data #(
-    .CHDR_W(CHDR_W)
-  ) chdr_to_chdr_data_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .s_axis_chdr_tdata(s_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .s_axis_chdr_tlast(s_rfnoc_chdr_tlast[${idx}]),  
-    .s_axis_chdr_tvalid(s_rfnoc_chdr_tvalid[${idx}]),
-    .s_axis_chdr_tready(s_rfnoc_chdr_tready[${idx}]),
-    .m_axis_chdr_tdata(m_${input}_chdr_tdata),
-    .m_axis_chdr_tlast(m_${input}_chdr_tlast),
-    .m_axis_chdr_tvalid(m_${input}_chdr_tvalid),
-    .m_axis_chdr_tready(m_${input}_chdr_tready),
-    .flush_en(data_i_flush_en),
-    .flush_timeout(data_i_flush_timeout),
-    .flush_active(data_i_flush_active[${idx}]),
-    .flush_done(data_i_flush_done[${idx}])
+    .CHDR_W (CHDR_W)
+  ) chdr_to_chdr_data_in_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_chdr_tdata  (m_${port_name}_chdr_tdata),
+    .m_axis_chdr_tlast  (m_${port_name}_chdr_tlast),
+    .m_axis_chdr_tvalid (m_${port_name}_chdr_tvalid),
+    .m_axis_chdr_tready (m_${port_name}_chdr_tready),
+    .flush_en           (data_i_flush_en),
+    .flush_timeout      (data_i_flush_timeout),
+    .flush_active       (data_i_flush_active[${port_index}]),
+    .flush_done         (data_i_flush_done[${port_index}])
   );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
 %endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
 
-%for idx, output in enumerate(config['data']['outputs']):
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    chdr_to_chdr_data #(
+      .CHDR_W (CHDR_W)
+    ) chdr_to_chdr_data_out_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_chdr_tdata  (s_${port_name}_chdr_tdata[i*CHDR_W+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_${port_name}_chdr_tlast[i]),
+      .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid[i]),
+      .s_axis_chdr_tready (s_${port_name}_chdr_tready[i]),
+      .flush_en           (data_o_flush_en),
+      .flush_timeout      (data_o_flush_timeout),
+      .flush_active       (data_o_flush_active[${port_index}+i]),
+      .flush_done         (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
   chdr_to_chdr_data #(
-    .CHDR_W(CHDR_W)
-  ) chdr_to_chdr_data_o${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .m_axis_chdr_tdata(m_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .m_axis_chdr_tlast(m_rfnoc_chdr_tlast[${idx}]),    
-    .m_axis_chdr_tvalid(m_rfnoc_chdr_tvalid[${idx}]),
-    .m_axis_chdr_tready(m_rfnoc_chdr_tready[${idx}]),
-    .s_axis_chdr_tdata(s_${output}_chdr_tdata),
-    .s_axis_chdr_tlast(s_${output}_chdr_tlast),
-    .s_axis_chdr_tvalid(s_${output}_chdr_tvalid),
-    .s_axis_chdr_tready(s_${output}_chdr_tready),
-    .flush_en(data_o_flush_en),
-    .flush_timeout(data_o_flush_timeout),
-    .flush_active(data_o_flush_active[${idx}]),
-    .flush_done(data_o_flush_done[${idx}])
+    .CHDR_W (CHDR_W)
+  ) chdr_to_chdr_data_out_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_chdr_tdata  (s_${port_name}_chdr_tdata),
+    .s_axis_chdr_tlast  (s_${port_name}_chdr_tlast),
+    .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid),
+    .s_axis_chdr_tready (s_${port_name}_chdr_tready),
+    .flush_en           (data_o_flush_en),
+    .flush_timeout      (data_o_flush_timeout),
+    .flush_active       (data_o_flush_active[${port_index}]),
+    .flush_done         (data_o_flush_done[${port_index}])
   );
-%endfor
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
\ No newline at end of file
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
index 9453c8fd1..39c1a33f7 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
@@ -1,5 +1,4 @@
-<%page args="mode, num_inputs, num_outputs"/>\
-
+<%page args="mode"/>\
 <%
   if mode == "shell":
     sl_pre = "s_"
@@ -8,23 +7,48 @@
     out_wire = "output "
     term = ","
   elif mode == "block":
-    sl_pre = ""
-    ma_pre = ""
+    sl_pre = "s_"
+    ma_pre = "m_"
     in_wire = ""
     out_wire = ""
-    term=";"
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
 %>\
 %for idx, port in enumerate(config['data']['inputs']):
-  // Payload Stream to User Logic: ${port}
+<%
+  port_info = config['data']['inputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+  // Framework to User Logic: ${port}
+%if num_ports != 1:
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0]  ${ma_pre}${port}_chdr_tdata${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_inputs -1) or (num_outputs > 0) else ""}
+%else:
   ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_chdr_tdata${term}
   ${out_wire}wire               ${ma_pre}${port}_chdr_tlast${term}
   ${out_wire}wire               ${ma_pre}${port}_chdr_tvalid${term}
   ${in_wire}wire               ${ma_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_inputs -1) or (num_outputs > 0) else ""}
+%endif
 %endfor
-
 %for idx, port in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+  // User Logic to Framework: ${port}
+%if num_ports != 1:
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0]  ${sl_pre}${port}_chdr_tdata${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
+%else:
   ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_chdr_tdata${term}
   ${in_wire}wire               ${sl_pre}${port}_chdr_tlast${term}
   ${in_wire}wire               ${sl_pre}${port}_chdr_tvalid${term}
   ${out_wire}wire               ${sl_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
+%endif
 %endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
index cefc97a22..5c36f4a9e 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
@@ -1,8 +1,13 @@
-  .m_axis_ctrl_tdata(m_axis_ctrl_tdata),
-  .m_axis_ctrl_tlast(m_axis_ctrl_tlast),
-  .m_axis_ctrl_tvalid(m_axis_ctrl_tvalid),
-  .m_axis_ctrl_tready(m_axis_ctrl_tready),
-  .s_axis_ctrl_tdata(s_axis_ctrl_tdata),
-  .s_axis_ctrl_tlast(s_axis_ctrl_tlast),
-  .s_axis_ctrl_tvalid(s_axis_ctrl_tvalid),
-  .s_axis_ctrl_tready(s_axis_ctrl_tready),
+    // AXIS-Ctrl Clock and Reset
+    .axis_ctrl_clk      (axis_ctrl_clk),
+    .axis_ctrl_rst      (axis_ctrl_rst),
+    // AXIS-Ctrl to User Logic
+    .m_axis_ctrl_tdata  (m_axis_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_axis_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_axis_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_axis_ctrl_tready),
+    // AXIS-Ctrl from User Logic
+    .s_axis_ctrl_tdata  (s_axis_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_axis_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_axis_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_axis_ctrl_tready),
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
index 4c349b11b..a491e3973 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
@@ -1,28 +1,28 @@
 <%!
-import math
-%>
+  import math
+%>\
   axis_ctrl_endpoint #(
-    .SYNC_CLKS(${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
-    .SLAVE_FIFO_SIZE(${math.ceil(math.log2(config['control']['fifo_depth']))})         
+    .SYNC_CLKS       (${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
+    .SLAVE_FIFO_SIZE ($clog2(${config['control']['fifo_depth']}))
   ) axis_ctrl_endpoint_i (
-    .rfnoc_ctrl_clk(rfnoc_ctrl_clk),
-    .rfnoc_ctrl_rst(rfnoc_ctrl_rst),
-    .axis_ctrl_clk(axis_ctrl_clk),
-    .axis_ctrl_rst(axis_ctrl_rst),
-    .s_rfnoc_ctrl_tdata(s_rfnoc_ctrl_tdata),
-    .s_rfnoc_ctrl_tlast(s_rfnoc_ctrl_tlast),
-    .s_rfnoc_ctrl_tvalid(s_rfnoc_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_rfnoc_ctrl_tready),
-    .m_rfnoc_ctrl_tdata(m_rfnoc_ctrl_tdata),
-    .m_rfnoc_ctrl_tlast(m_rfnoc_ctrl_tlast),
-    .m_rfnoc_ctrl_tvalid(m_rfnoc_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_rfnoc_ctrl_tready),
-    .s_axis_ctrl_tdata(s_axis_ctrl_tdata),
-    .s_axis_ctrl_tlast(s_axis_ctrl_tlast),
-    .s_axis_ctrl_tvalid(s_axis_ctrl_tvalid),
-    .s_axis_ctrl_tready(s_axis_ctrl_tready),
-    .m_axis_ctrl_tdata(m_axis_ctrl_tdata),
-    .m_axis_ctrl_tlast(m_axis_ctrl_tlast),
-    .m_axis_ctrl_tvalid(m_axis_ctrl_tvalid),
-    .m_axis_ctrl_tready(m_axis_ctrl_tready)
-    );
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst      (rfnoc_ctrl_rst),
+    .axis_ctrl_clk       (axis_ctrl_clk),
+    .axis_ctrl_rst       (axis_ctrl_rst),
+    .s_rfnoc_ctrl_tdata  (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata  (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
+    .s_axis_ctrl_tdata   (s_axis_ctrl_tdata),
+    .s_axis_ctrl_tlast   (s_axis_ctrl_tlast),
+    .s_axis_ctrl_tvalid  (s_axis_ctrl_tvalid),
+    .s_axis_ctrl_tready  (s_axis_ctrl_tready),
+    .m_axis_ctrl_tdata   (m_axis_ctrl_tdata),
+    .m_axis_ctrl_tlast   (m_axis_ctrl_tlast),
+    .m_axis_ctrl_tvalid  (m_axis_ctrl_tvalid),
+    .m_axis_ctrl_tready  (m_axis_ctrl_tready)
+  );
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
index dd15bd100..794d71bd8 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
@@ -13,10 +13,12 @@
     out_wire = ""
     term = ";"
 %>\
+  // AXIS-Ctrl to User Logic
   ${out_wire}wire [31:0]        ${ma_pre}axis_ctrl_tdata${term}
   ${out_wire}wire               ${ma_pre}axis_ctrl_tlast${term}
   ${out_wire}wire               ${ma_pre}axis_ctrl_tvalid${term}
   ${in_wire}wire               ${ma_pre}axis_ctrl_tready${term}
+  // AXIS-Ctrl Control from User Logic
   ${in_wire}wire [31:0]        ${sl_pre}axis_ctrl_tdata${term}
   ${in_wire}wire               ${sl_pre}axis_ctrl_tlast${term}
   ${in_wire}wire               ${sl_pre}axis_ctrl_tvalid${term}
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
new file mode 100644
index 000000000..2da895702
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
@@ -0,0 +1,33 @@
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXI-Stream Payload Context Clock and Reset
+    .axis_data_clk (axis_data_clk),
+    .axis_data_rst (axis_data_rst),
+%for idx, port_name in enumerate(config['data']['inputs']):
+    // Data Stream to User Logic: ${port_name}
+    .m_${port_name}_axis_tdata      (m_${port_name}_axis_tdata),
+    .m_${port_name}_axis_tkeep      (m_${port_name}_axis_tkeep),
+    .m_${port_name}_axis_tlast      (m_${port_name}_axis_tlast),
+    .m_${port_name}_axis_tvalid     (m_${port_name}_axis_tvalid),
+    .m_${port_name}_axis_tready     (m_${port_name}_axis_tready),
+    .m_${port_name}_axis_ttimestamp (m_${port_name}_axis_ttimestamp),
+    .m_${port_name}_axis_thas_time  (m_${port_name}_axis_thas_time),
+    .m_${port_name}_axis_tlength    (m_${port_name}_axis_tlength),
+    .m_${port_name}_axis_teov       (m_${port_name}_axis_teov),
+    .m_${port_name}_axis_teob       (m_${port_name}_axis_teob)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+    // Data Stream from User Logic: ${port_name}
+    .s_${port_name}_axis_tdata      (s_${port_name}_axis_tdata),
+    .s_${port_name}_axis_tkeep      (s_${port_name}_axis_tkeep),
+    .s_${port_name}_axis_tlast      (s_${port_name}_axis_tlast),
+    .s_${port_name}_axis_tvalid     (s_${port_name}_axis_tvalid),
+    .s_${port_name}_axis_tready     (s_${port_name}_axis_tready),
+    .s_${port_name}_axis_ttimestamp (s_${port_name}_axis_ttimestamp),
+    .s_${port_name}_axis_thas_time  (s_${port_name}_axis_thas_time),
+    .s_${port_name}_axis_teov       (s_${port_name}_axis_teov),
+    .s_${port_name}_axis_teob       (s_${port_name}_axis_teob)${"," if (idx < num_outputs -1) else ""}
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
new file mode 100644
index 000000000..f2fa6e9da
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
@@ -0,0 +1,170 @@
+<%!
+import math
+%>\
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_axis_data #(
+      .CHDR_W         (CHDR_W),
+      .ITEM_W         (${port_info['item_width']}),
+      .NIPC           (${port_info['nipc']}),
+      .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+      .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']}))
+    ) chdr_to_axis_data_in_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .axis_data_clk      (axis_data_clk),
+      .axis_data_rst      (axis_data_rst),
+      .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[((${port_index}+i)*CHDR_W)+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_tdata       (m_${port_name}_axis_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .m_axis_tkeep       (m_${port_name}_axis_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .m_axis_tlast       (m_${port_name}_axis_tlast[i]),
+      .m_axis_tvalid      (m_${port_name}_axis_tvalid[i]),
+      .m_axis_tready      (m_${port_name}_axis_tready[i]),
+      .m_axis_ttimestamp  (m_${port_name}_axis_ttimestamp[64*i+:64]),
+      .m_axis_thas_time   (m_${port_name}_axis_thas_time[i]),
+      .m_axis_tlength     (m_${port_name}_axis_tlength[i*16+:16]),
+      .m_axis_teov        (m_${port_name}_axis_teov[i]),
+      .m_axis_teob        (m_${port_name}_axis_teob[i]),
+      .flush_en           (data_i_flush_en),
+      .flush_timeout      (data_i_flush_timeout),
+      .flush_active       (data_i_flush_active[${port_index}+i]),
+      .flush_done         (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  chdr_to_axis_data #(
+    .CHDR_W         (CHDR_W),
+    .ITEM_W         (${port_info['item_width']}),
+    .NIPC           (${port_info['nipc']}),
+    .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+    .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']}))
+  ) chdr_to_axis_data_in_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .axis_data_clk      (axis_data_clk),
+    .axis_data_rst      (axis_data_rst),
+    .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_tdata       (m_${port_name}_axis_tdata),
+    .m_axis_tkeep       (m_${port_name}_axis_tkeep),
+    .m_axis_tlast       (m_${port_name}_axis_tlast),
+    .m_axis_tvalid      (m_${port_name}_axis_tvalid),
+    .m_axis_tready      (m_${port_name}_axis_tready),
+    .m_axis_ttimestamp  (m_${port_name}_axis_ttimestamp),
+    .m_axis_thas_time   (m_${port_name}_axis_thas_time),
+    .m_axis_tlength     (m_${port_name}_axis_tlength),
+    .m_axis_teov        (m_${port_name}_axis_teov),
+    .m_axis_teob        (m_${port_name}_axis_teob),
+    .flush_en           (data_i_flush_en),
+    .flush_timeout      (data_i_flush_timeout),
+    .flush_active       (data_i_flush_active[${port_index}]),
+    .flush_done         (data_i_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    axis_data_to_chdr #(
+      .CHDR_W         (CHDR_W),
+      .ITEM_W         (${port_info['item_width']}),
+      .NIPC           (${port_info['nipc']}),
+      .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+      .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+      .MTU            (MTU)
+    ) axis_data_to_chdr_out_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .axis_data_clk      (axis_data_clk),
+      .axis_data_rst      (axis_data_rst),
+      .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_tdata       (s_${port_name}_axis_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .s_axis_tkeep       (s_${port_name}_axis_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .s_axis_tlast       (s_${port_name}_axis_tlast[i]),
+      .s_axis_tvalid      (s_${port_name}_axis_tvalid[i]),
+      .s_axis_tready      (s_${port_name}_axis_tready[i]),
+      .s_axis_ttimestamp  (s_${port_name}_axis_ttimestamp[64*i+:64]),
+      .s_axis_thas_time   (s_${port_name}_axis_thas_time[i]),
+      .s_axis_teov        (s_${port_name}_axis_teov[i]),
+      .s_axis_teob        (s_${port_name}_axis_teob[i]),
+      .flush_en           (data_o_flush_en),
+      .flush_timeout      (data_o_flush_timeout),
+      .flush_active       (data_o_flush_active[${port_index}+i]),
+      .flush_done         (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  axis_data_to_chdr #(
+    .CHDR_W         (CHDR_W),
+    .ITEM_W         (${port_info['item_width']}),
+    .NIPC           (${port_info['nipc']}),
+    .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+    .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+    .MTU            (MTU)
+  ) axis_data_to_chdr_out_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .axis_data_clk      (axis_data_clk),
+    .axis_data_rst      (axis_data_rst),
+    .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_tdata       (s_${port_name}_axis_tdata),
+    .s_axis_tkeep       (s_${port_name}_axis_tkeep),
+    .s_axis_tlast       (s_${port_name}_axis_tlast),
+    .s_axis_tvalid      (s_${port_name}_axis_tvalid),
+    .s_axis_tready      (s_${port_name}_axis_tready),
+    .s_axis_ttimestamp  (s_${port_name}_axis_ttimestamp),
+    .s_axis_thas_time   (s_${port_name}_axis_thas_time),
+    .s_axis_teov        (s_${port_name}_axis_teov),
+    .s_axis_teob        (s_${port_name}_axis_teob),
+    .flush_en           (data_o_flush_en),
+    .flush_timeout      (data_o_flush_timeout),
+    .flush_active       (data_o_flush_active[${port_index}]),
+    .flush_done         (data_o_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
new file mode 100644
index 000000000..4d3c719ae
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
@@ -0,0 +1,78 @@
+<%page args="mode"/>\
+<%
+  if mode == "shell":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = "input  "
+    out_wire = "output "
+    term = ","
+  elif mode == "block":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = ""
+    out_wire = ""
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+%for idx, port_name in enumerate(config['data']['inputs']):
+<%
+  port_info = config['data']['inputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Data Stream to User Logic: ${port_name}
+  ${out_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${ma_pre}${port_name}_axis_tdata${term}
+  ${out_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${ma_pre}${port_name}_axis_tkeep${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tready${term}
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0] ${ma_pre}${port_name}_axis_ttimestamp${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_thas_time${term}
+  ${out_wire}wire [${num_ports}*16-1:0]     ${ma_pre}${port_name}_axis_tlength${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_teov${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%else:
+  // Data Stream to User Logic: ${port_name}
+  ${out_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${ma_pre}${port_name}_axis_tdata${term}
+  ${out_wire}wire [${port_info['nipc']}-1:0]       ${ma_pre}${port_name}_axis_tkeep${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port_name}_axis_tready${term}
+  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port_name}_axis_ttimestamp${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_thas_time${term}
+  ${out_wire}wire [15:0]        ${ma_pre}${port_name}_axis_tlength${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_teov${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endif
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Data Stream to User Logic: ${port_name}
+  ${in_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${sl_pre}${port_name}_axis_tdata${term}
+  ${in_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${sl_pre}${port_name}_axis_tkeep${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tready${term}
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_thas_time${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_teov${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) else ""}
+%else:
+  // Data Stream from User Logic: ${port_name}
+  ${in_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${sl_pre}${port_name}_axis_tdata${term}
+  ${in_wire}wire [${port_info['nipc'] - 1}:0]         ${sl_pre}${port_name}_axis_tkeep${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port_name}_axis_tready${term}
+  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port_name}_axis_ttimestamp${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_thas_time${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_teov${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_outputs - 1) else ""}
+%endif
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako
new file mode 100644
index 000000000..e3a6c655b
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako
@@ -0,0 +1,36 @@
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXI-Stream Payload Context Clock and Reset
+    .axis_data_clk (axis_data_clk),
+    .axis_data_rst (axis_data_rst),
+%for idx, port_name in enumerate(config['data']['inputs']):
+    // Payload Stream to User Logic: ${port_name}
+    .m_${port_name}_payload_tdata  (m_${port_name}_payload_tdata),
+    .m_${port_name}_payload_tkeep  (m_${port_name}_payload_tkeep),
+    .m_${port_name}_payload_tlast  (m_${port_name}_payload_tlast),
+    .m_${port_name}_payload_tvalid (m_${port_name}_payload_tvalid),
+    .m_${port_name}_payload_tready (m_${port_name}_payload_tready),
+    // Context Stream to User Logic: ${port_name}
+    .m_${port_name}_context_tdata  (m_${port_name}_context_tdata),
+    .m_${port_name}_context_tuser  (m_${port_name}_context_tuser),
+    .m_${port_name}_context_tlast  (m_${port_name}_context_tlast),
+    .m_${port_name}_context_tvalid (m_${port_name}_context_tvalid),
+    .m_${port_name}_context_tready (m_${port_name}_context_tready)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+    // Payload Stream from User Logic: ${port_name}
+    .s_${port_name}_payload_tdata  (s_${port_name}_payload_tdata),
+    .s_${port_name}_payload_tkeep  (s_${port_name}_payload_tkeep),
+    .s_${port_name}_payload_tlast  (s_${port_name}_payload_tlast),
+    .s_${port_name}_payload_tvalid (s_${port_name}_payload_tvalid),
+    .s_${port_name}_payload_tready (s_${port_name}_payload_tready),
+    // Context Stream from User Logic: ${port_name}
+    .s_${port_name}_context_tdata  (s_${port_name}_context_tdata),
+    .s_${port_name}_context_tuser  (s_${port_name}_context_tuser),
+    .s_${port_name}_context_tlast  (s_${port_name}_context_tlast),
+    .s_${port_name}_context_tvalid (s_${port_name}_context_tvalid),
+    .s_${port_name}_context_tready (s_${port_name}_context_tready)${"," if (idx < num_outputs -1) else ""}
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako
new file mode 100644
index 000000000..61c8cffd6
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako
@@ -0,0 +1,178 @@
+<%!
+import math
+%>\
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_axis_pyld_ctxt #(
+      .CHDR_W              (CHDR_W),
+      .ITEM_W              (${port_info['item_width']}),
+      .NIPC                (${port_info['nipc']}),
+      .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+      .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+      .CONTEXT_PREFETCH_EN (1)
+    ) chdr_to_axis_pyld_ctxt_in_${port_name} (
+      .axis_chdr_clk         (rfnoc_chdr_clk),
+      .axis_chdr_rst         (rfnoc_chdr_rst),
+      .axis_data_clk         (axis_data_clk),
+      .axis_data_rst         (axis_data_rst),
+      .s_axis_chdr_tdata     (s_rfnoc_chdr_tdata[((${port_index}+i)*CHDR_W)+:CHDR_W]),
+      .s_axis_chdr_tlast     (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid    (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready    (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_payload_tdata  (m_${port_name}_payload_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .m_axis_payload_tkeep  (m_${port_name}_payload_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .m_axis_payload_tlast  (m_${port_name}_payload_tlast[i]),
+      .m_axis_payload_tvalid (m_${port_name}_payload_tvalid[i]),
+      .m_axis_payload_tready (m_${port_name}_payload_tready[i]),
+      .m_axis_context_tdata  (m_${port_name}_context_tdata[CHDR_W*i+:CHDR_W]),
+      .m_axis_context_tuser  (m_${port_name}_context_tuser[4*i+:4]),
+      .m_axis_context_tlast  (m_${port_name}_context_tlast[i]),
+      .m_axis_context_tvalid (m_${port_name}_context_tvalid[i]),
+      .m_axis_context_tready (m_${port_name}_context_tready[i]),
+      .flush_en              (data_i_flush_en),
+      .flush_timeout         (data_i_flush_timeout),
+      .flush_active          (data_i_flush_active[${port_index}+i]),
+      .flush_done            (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  chdr_to_axis_pyld_ctxt #(
+    .CHDR_W              (CHDR_W),
+    .ITEM_W              (${port_info['item_width']}),
+    .NIPC                (${port_info['nipc']}),
+    .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+    .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+    .CONTEXT_PREFETCH_EN (1)
+  ) chdr_to_axis_pyld_ctxt_in_${port_name} (
+    .axis_chdr_clk         (rfnoc_chdr_clk),
+    .axis_chdr_rst         (rfnoc_chdr_rst),
+    .axis_data_clk         (axis_data_clk),
+    .axis_data_rst         (axis_data_rst),
+    .s_axis_chdr_tdata     (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast     (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid    (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready    (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_payload_tdata  (m_${port_name}_payload_tdata),
+    .m_axis_payload_tkeep  (m_${port_name}_payload_tkeep),
+    .m_axis_payload_tlast  (m_${port_name}_payload_tlast),
+    .m_axis_payload_tvalid (m_${port_name}_payload_tvalid),
+    .m_axis_payload_tready (m_${port_name}_payload_tready),
+    .m_axis_context_tdata  (m_${port_name}_context_tdata),
+    .m_axis_context_tuser  (m_${port_name}_context_tuser),
+    .m_axis_context_tlast  (m_${port_name}_context_tlast),
+    .m_axis_context_tvalid (m_${port_name}_context_tvalid),
+    .m_axis_context_tready (m_${port_name}_context_tready),
+    .flush_en              (data_i_flush_en),
+    .flush_timeout         (data_i_flush_timeout),
+    .flush_active          (data_i_flush_active[${port_index}]),
+    .flush_done            (data_i_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    axis_pyld_ctxt_to_chdr #(
+      .CHDR_W              (CHDR_W),
+      .ITEM_W              (${port_info['item_width']}),
+      .NIPC                (${port_info['nipc']}),
+      .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+      .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+      .MTU                 (MTU),
+      .CONTEXT_PREFETCH_EN (1)
+    ) axis_pyld_ctxt_to_chdr_out_${port_name} (
+      .axis_chdr_clk         (rfnoc_chdr_clk),
+      .axis_chdr_rst         (rfnoc_chdr_rst),
+      .axis_data_clk         (axis_data_clk),
+      .axis_data_rst         (axis_data_rst),
+      .m_axis_chdr_tdata     (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast     (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid    (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready    (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_payload_tdata  (s_${port_name}_payload_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .s_axis_payload_tkeep  (s_${port_name}_payload_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .s_axis_payload_tlast  (s_${port_name}_payload_tlast[i]),
+      .s_axis_payload_tvalid (s_${port_name}_payload_tvalid[i]),
+      .s_axis_payload_tready (s_${port_name}_payload_tready[i]),
+      .s_axis_context_tdata  (s_${port_name}_context_tdata[CHDR_W*i+:CHDR_W]),
+      .s_axis_context_tuser  (s_${port_name}_context_tuser[4*i+:4]),
+      .s_axis_context_tlast  (s_${port_name}_context_tlast[i]),
+      .s_axis_context_tvalid (s_${port_name}_context_tvalid[i]),
+      .s_axis_context_tready (s_${port_name}_context_tready[i]),
+      .framer_errors         (),
+      .flush_en              (data_o_flush_en),
+      .flush_timeout         (data_o_flush_timeout),
+      .flush_active          (data_o_flush_active[${port_index}+i]),
+      .flush_done            (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  axis_pyld_ctxt_to_chdr #(
+    .CHDR_W              (CHDR_W),
+    .ITEM_W              (${port_info['item_width']}),
+    .NIPC                (${port_info['nipc']}),
+    .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+    .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+    .MTU                 (MTU),
+    .CONTEXT_PREFETCH_EN (1)
+  ) axis_pyld_ctxt_to_chdr_out_${port_name} (
+    .axis_chdr_clk         (rfnoc_chdr_clk),
+    .axis_chdr_rst         (rfnoc_chdr_rst),
+    .axis_data_clk         (axis_data_clk),
+    .axis_data_rst         (axis_data_rst),
+    .m_axis_chdr_tdata     (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast     (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid    (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready    (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_payload_tdata  (s_${port_name}_payload_tdata),
+    .s_axis_payload_tkeep  (s_${port_name}_payload_tkeep),
+    .s_axis_payload_tlast  (s_${port_name}_payload_tlast),
+    .s_axis_payload_tvalid (s_${port_name}_payload_tvalid),
+    .s_axis_payload_tready (s_${port_name}_payload_tready),
+    .s_axis_context_tdata  (s_${port_name}_context_tdata),
+    .s_axis_context_tuser  (s_${port_name}_context_tuser),
+    .s_axis_context_tlast  (s_${port_name}_context_tlast),
+    .s_axis_context_tvalid (s_${port_name}_context_tvalid),
+    .s_axis_context_tready (s_${port_name}_context_tready),
+    .framer_errors         (),
+    .flush_en              (data_o_flush_en),
+    .flush_timeout         (data_o_flush_timeout),
+    .flush_active          (data_o_flush_active[${port_index}]),
+    .flush_done            (data_o_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako
new file mode 100644
index 000000000..8251749df
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako
@@ -0,0 +1,84 @@
+<%page args="mode"/>\
+<%
+  if mode == "shell":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = "input  "
+    out_wire = "output "
+    term = ","
+  elif mode == "block":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = ""
+    out_wire = ""
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+%for idx, port in enumerate(config['data']['inputs']):
+<%
+  port_info = config['data']['inputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Payload Stream to User Logic: ${port}
+  ${out_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${ma_pre}${port}_payload_tdata${term}
+  ${out_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${ma_pre}${port}_payload_tkeep${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0] ${ma_pre}${port}_context_tdata${term}
+  ${out_wire}wire [${num_ports}*4-1:0]      ${ma_pre}${port}_context_tuser${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%else:
+  // Payload Stream to User Logic: ${port}
+  ${out_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${ma_pre}${port}_payload_tdata${term}
+  ${out_wire}wire [${port_info['nipc']}-1:0]       ${ma_pre}${port}_payload_tkeep${term}
+  ${out_wire}wire               ${ma_pre}${port}_payload_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port}_payload_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_context_tdata${term}
+  ${out_wire}wire [3:0]         ${ma_pre}${port}_context_tuser${term}
+  ${out_wire}wire               ${ma_pre}${port}_context_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port}_context_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endif
+%endfor
+%for idx, port in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Payload Stream to User Logic: ${port}
+  ${in_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${sl_pre}${port}_payload_tdata${term}
+  ${in_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${sl_pre}${port}_payload_tkeep${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0] ${sl_pre}${port}_context_tdata${term}
+  ${in_wire}wire [${num_ports}*4-1:0]      ${sl_pre}${port}_context_tuser${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) else ""}
+%else:
+  // Payload Stream from User Logic: ${port}
+  ${in_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${sl_pre}${port}_payload_tdata${term}
+  ${in_wire}wire [${port_info['nipc'] - 1}:0]         ${sl_pre}${port}_payload_tkeep${term}
+  ${in_wire}wire               ${sl_pre}${port}_payload_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port}_payload_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port}_payload_tready${term}
+  // Context Stream from User Logic: ${port}
+  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_context_tdata${term}
+  ${in_wire}wire [3:0]         ${sl_pre}${port}_context_tuser${term}
+  ${in_wire}wire               ${sl_pre}${port}_context_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port}_context_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_outputs - 1) else ""}
+%endif
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako
deleted file mode 100644
index c78946289..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako
+++ /dev/null
@@ -1,31 +0,0 @@
-<%page args="num_inputs, num_outputs"/>\
-\
-%for idx, input in enumerate(config['data']['inputs']):
-  // Payload Stream to User Logic: ${input}
-  .m_${input}_payload_tdata(${input}_payload_tdata),
-  .m_${input}_payload_tkeep(${input}_payload_tkeep),
-  .m_${input}_payload_tlast(${input}_payload_tlast),
-  .m_${input}_payload_tvalid(${input}_payload_tvalid),
-  .m_${input}_payload_tready(${input}_payload_tready),
-  // Context Stream to User Logic: ${input}
-  .m_${input}_context_tdata(${input}_context_tdata),
-  .m_${input}_context_tuser(${input}_context_tuser),
-  .m_${input}_context_tlast(${input}_context_tlast),
-  .m_${input}_context_tvalid(${input}_context_tvalid),
-  .m_${input}_context_tready(${input}_context_tready)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
-%endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  // Payload Stream from User Logic: ${output}
-  .s_${output}_payload_tdata(${output}_payload_tdata),
-  .s_${output}_payload_tkeep(${output}_payload_tkeep),
-  .s_${output}_payload_tlast(${output}_payload_tlast),
-  .s_${output}_payload_tvalid(${output}_payload_tvalid),
-  .s_${output}_payload_tready(${output}_payload_tready),
-  // Context Stream from User Logic: ${output}
-  .s_${output}_context_tdata(${output}_context_tdata),
-  .s_${output}_context_tuser(${output}_context_tuser),
-  .s_${output}_context_tlast(${output}_context_tlast),
-  .s_${output}_context_tvalid(${output}_context_tvalid),
-  .s_${output}_context_tready(${output}_context_tready)${"," if (idx < num_outputs -1) else ""}
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako
deleted file mode 100644
index c181eeedd..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako
+++ /dev/null
@@ -1,78 +0,0 @@
-
-%for idx, input in enumerate(config['data']['inputs']):
-  <%
-    port_tmp = config['data']['inputs'][input]
-  %>
-  chdr_to_axis_raw_data #(
-    .CHDR_W(CHDR_W),
-    .ITEM_W(${port_tmp['item_width']}),
-    .NIPC(${port_tmp['nipc']}),
-    .SYNC_CLKS(${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),              
-    .CONTEXT_FIFO_SIZE(${port_tmp['context_fifo_depth']}),      
-    .PAYLOAD_FIFO_SIZE(${port_tmp['payload_fifo_depth']}),      
-    .CONTEXT_PREFETCH_EN(1)     
-  ) chdr_to_axis_raw_data_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .axis_data_clk(axis_data_clk),
-    .axis_data_rst(axis_data_rst),
-    .s_axis_chdr_tdata(s_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .s_axis_chdr_tlast(s_rfnoc_chdr_tlast[${idx}]),  
-    .s_axis_chdr_tvalid(s_rfnoc_chdr_tvalid[${idx}]),
-    .s_axis_chdr_tready(s_rfnoc_chdr_tready[${idx}]),
-    .m_axis_payload_tdata(m_${input}_payload_tdata),
-    .m_axis_payload_tkeep(m_${input}_payload_tkeep),
-    .m_axis_payload_tlast(m_${input}_payload_tlast),
-    .m_axis_payload_tvalid(m_${input}_payload_tvalid),
-    .m_axis_payload_tready(m_${input}_payload_tready),
-    .m_axis_context_tdata(m_${input}_context_tdata),
-    .m_axis_context_tuser(m_${input}_context_tuser),
-    .m_axis_context_tlast(m_${input}_context_tlast),
-    .m_axis_context_tvalid(m_${input}_context_tvalid),
-    .m_axis_context_tready(m_${input}_context_tready),
-    .flush_en(data_i_flush_en),
-    .flush_timeout(data_i_flush_timeout),
-    .flush_active(data_i_flush_active[${idx}]), 
-    .flush_done(data_i_flush_done[${idx}])
-  );
-%endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  <%
-    port_tmp = config['data']['outputs'][output]
-  %>
-  axis_raw_data_to_chdr #(
-    .CHDR_W(CHDR_W),
-    .ITEM_W(${port_tmp['item_width']}),
-    .NIPC(${port_tmp['nipc']}),
-    .SYNC_CLKS(${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),              
-    .CONTEXT_FIFO_SIZE(${port_tmp['context_fifo_depth']}),      
-    .PAYLOAD_FIFO_SIZE(${port_tmp['payload_fifo_depth']}),      
-    .CONTEXT_PREFETCH_EN(1),    
-    .MTU(MTU)
-  ) axis_raw_data_to_chdr_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .axis_data_clk(axis_data_clk),
-    .axis_data_rst(axis_data_rst),
-    .m_axis_chdr_tdata(m_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .m_axis_chdr_tlast(m_rfnoc_chdr_tlast[${idx}]),    
-    .m_axis_chdr_tvalid(m_rfnoc_chdr_tvalid[${idx}]),
-    .m_axis_chdr_tready(m_rfnoc_chdr_tready[${idx}]),
-    .s_axis_payload_tdata(s_${output}_payload_tdata),
-    .s_axis_payload_tkeep(s_${output}_payload_tkeep),
-    .s_axis_payload_tlast(s_${output}_payload_tlast),
-    .s_axis_payload_tvalid(s_${output}_payload_tvalid),
-    .s_axis_payload_tready(s_${output}_payload_tready),
-    .s_axis_context_tdata(s_${output}_context_tdata),
-    .s_axis_context_tuser(s_${output}_context_tuser),
-    .s_axis_context_tlast(s_${output}_context_tlast),
-    .s_axis_context_tvalid(s_${output}_context_tvalid),
-    .s_axis_context_tready(s_${output}_context_tready),
-    .framer_errors(),   
-    .flush_en(data_o_flush_en),
-    .flush_timeout(data_o_flush_timeout),
-    .flush_active(data_o_flush_active[${idx}]),
-    .flush_done(data_o_flush_done[${idx}])
-  );
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako
deleted file mode 100644
index abb8ef5e0..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako
+++ /dev/null
@@ -1,50 +0,0 @@
-<%page args="mode, num_inputs, num_outputs"/>\
-<%
-  if mode == "shell":
-    sl_pre = "s_"
-    ma_pre = "m_"
-    in_wire = "input  "
-    out_wire = "output "
-    term = ","
-  elif mode == "block":
-    sl_pre = ""
-    ma_pre = ""
-    in_wire = ""
-    out_wire = ""
-    term = ";"
-%>\
-%for idx, port in enumerate(config['data']['inputs']):
-  <%
-    port_tmp = config['data']['inputs'][port]
-  %>\
-  // Payload Stream to User Logic: ${port}
-  ${out_wire}wire [${port_tmp['item_width']*port_tmp['nipc']-1}:0]        ${ma_pre}${port}_payload_tdata${term}
-  ${out_wire}wire [${port_tmp['nipc']-1}:0]         ${ma_pre}${port}_payload_tkeep${term}
-  ${out_wire}wire               ${ma_pre}${port}_payload_tlast${term}
-  ${out_wire}wire               ${ma_pre}${port}_payload_tvalid${term}
-  ${in_wire}wire               ${ma_pre}${port}_payload_tready${term}
-  // Context Stream to User Logic: ${port}
-  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_context_tdata${term}
-  ${out_wire}wire [3:0]         ${ma_pre}${port}_context_tuser${term}
-  ${out_wire}wire               ${ma_pre}${port}_context_tlast${term}
-  ${out_wire}wire               ${ma_pre}${port}_context_tvalid${term}
-  ${in_wire}wire               ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
-%endfor
-
-%for idx, port in enumerate(config['data']['outputs']):
-  <%
-    port_tmp = config['data']['outputs'][port]
-  %>\
-  // Payload Stream from User Logic: ${port}
-  ${in_wire}wire [${port_tmp['item_width'] * port_tmp['nipc'] - 1}:0]        ${sl_pre}${port}_payload_tdata${term}
-  ${in_wire}wire [${port_tmp['nipc'] - 1}:0]         ${sl_pre}${port}_payload_tkeep${term}
-  ${in_wire}wire               ${sl_pre}${port}_payload_tlast${term}
-  ${in_wire}wire               ${sl_pre}${port}_payload_tvalid${term}
-  ${out_wire}wire               ${sl_pre}${port}_payload_tready${term}
-  // Context Stream from User Logic: ${port}
-  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_context_tdata${term}
-  ${in_wire}wire [3:0]         ${sl_pre}${port}_context_tuser${term}
-  ${in_wire}wire               ${sl_pre}${port}_context_tlast${term}
-  ${in_wire}wire               ${sl_pre}${port}_context_tvalid${term}
-  ${out_wire}wire               ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
index 944f4af16..310f3b53b 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
@@ -1,41 +1,44 @@
-  // Control Port Master
-  .m_ctrlport_req_wr(m_ctrlport_req_wr),
-  .m_ctrlport_req_rd(m_ctrlport_req_rd),
-  .m_ctrlport_req_addr(m_ctrlport_req_addr),
-  .m_ctrlport_req_data(m_ctrlport_req_data),
+    // CtrlPort Clock and Reset
+    .ctrlport_clk              (ctrlport_clk),
+    .ctrlport_rst              (ctrlport_rst),
+    // CtrlPort Master
+    .m_ctrlport_req_wr         (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd         (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr       (m_ctrlport_req_addr),
+    .m_ctrlport_req_data       (m_ctrlport_req_data),
 %if config['control']['ctrlport']['byte_mode']:
-  .m_ctrlport_req_byte_en(m_ctrlport_req_byte_en),
+    .m_ctrlport_req_byte_en    (m_ctrlport_req_byte_en),
 %endif
 %if config['control']['ctrlport']['timed']:
-  .m_ctrlport_req_has_time(m_ctrlport_req_has_time),
-  .m_ctrlport_req_time(m_ctrlport_req_time),
+    .m_ctrlport_req_has_time   (m_ctrlport_req_has_time),
+    .m_ctrlport_req_time       (m_ctrlport_req_time),
 %endif
-  .m_ctrlport_resp_ack(m_ctrlport_resp_ack),
+    .m_ctrlport_resp_ack       (m_ctrlport_resp_ack),
 %if config['control']['ctrlport']['has_status']:
-  .m_ctrlport_resp_status(m_ctrlport_resp_status),
+    .m_ctrlport_resp_status    (m_ctrlport_resp_status),
 %endif
-  .m_ctrlport_resp_data(m_ctrlport_resp_data),
+    .m_ctrlport_resp_data      (m_ctrlport_resp_data),
 %if config['control']['interface_direction'] != "slave":
-  // Control Port Slave
-  .s_ctrlport_req_wr(s_ctrlport_req_wr),
-  .s_ctrlport_req_rd(s_ctrlport_req_rd),
-  .s_ctrlport_req_addr(s_ctrlport_req_addr),
-  .s_ctrlport_req_portid(s_ctrlport_req_portid),
+    // CtrlPort Slave
+    .s_ctrlport_req_wr         (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd         (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr       (s_ctrlport_req_addr),
+    .s_ctrlport_req_portid     (s_ctrlport_req_portid),
   %if config['control']['interface_direction'] == "remote_master_slave":
-  .s_ctrlport_req_rem_epid(s_ctrlport_req_rem_epid),
-  .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_rem_epid   (s_ctrlport_req_rem_epid),
+    .s_ctrlport_req_rem_portid (s_ctrlport_req_rem_portid),
   %endif
-  .s_ctrlport_req_data(s_ctrlport_req_data),
+    .s_ctrlport_req_data       (s_ctrlport_req_data),
   %if config['control']['ctrlport']['byte_mode']:
-  .s_ctrlport_req_byte_en(s_ctrlport_req_byte_en),
+    .s_ctrlport_req_byte_en    (s_ctrlport_req_byte_en),
   %endif
   %if config['control']['ctrlport']['timed']:
-  .s_ctrlport_req_has_time(s_ctrlport_req_has_time),
-  .s_ctrlport_req_time(s_ctrlport_req_time),
+    .s_ctrlport_req_has_time   (s_ctrlport_req_has_time),
+    .s_ctrlport_req_time       (s_ctrlport_req_time),
   %endif
-  .s_ctrlport_resp_ack(s_ctrlport_resp_ack),
+    .s_ctrlport_resp_ack       (s_ctrlport_resp_ack),
   %if config['control']['ctrlport']['has_status']:
-  .s_ctrlport_resp_status(s_ctrlport_resp_status),
+    .s_ctrlport_resp_status    (s_ctrlport_resp_status),
   %endif
-  .s_ctrlport_resp_data(s_ctrlport_resp_data),
+    .s_ctrlport_resp_data      (s_ctrlport_resp_data),
 %endif
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
index 9aecc2b80..6dfe7f4be 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
@@ -1,47 +1,46 @@
 <%!
 import math
-%>
+%>\
   ctrlport_endpoint #(
-    .THIS_PORTID(THIS_PORTID),
-    .SYNC_CLKS(${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
-    .AXIS_CTRL_MST_EN(${int(config['control']['interface_direction'] != "slave")}),
-    .AXIS_CTRL_SLV_EN(1),       
-    .SLAVE_FIFO_SIZE(${math.ceil(math.log2(config['control']['fifo_depth']))})         
+    .THIS_PORTID      (THIS_PORTID),
+    .SYNC_CLKS        (${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
+    .AXIS_CTRL_MST_EN (${int(config['control']['interface_direction'] != "slave")}),
+    .AXIS_CTRL_SLV_EN (1),
+    .SLAVE_FIFO_SIZE  ($clog2(${config['control']['fifo_depth']}))
   ) ctrlport_endpoint_i (
-    .rfnoc_ctrl_clk(rfnoc_ctrl_clk),
-    .rfnoc_ctrl_rst(rfnoc_ctrl_rst),
-    .ctrlport_clk(ctrlport_clk),
-    .ctrlport_rst(ctrlport_rst),
-    .s_rfnoc_ctrl_tdata(s_rfnoc_ctrl_tdata),
-    .s_rfnoc_ctrl_tlast(s_rfnoc_ctrl_tlast),
-    .s_rfnoc_ctrl_tvalid(s_rfnoc_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_rfnoc_ctrl_tready),
-    .m_rfnoc_ctrl_tdata(m_rfnoc_ctrl_tdata),
-    .m_rfnoc_ctrl_tlast(m_rfnoc_ctrl_tlast),
-    .m_rfnoc_ctrl_tvalid(m_rfnoc_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_rfnoc_ctrl_tready),
-    .m_ctrlport_req_wr(m_ctrlport_req_wr),
-    .m_ctrlport_req_rd(m_ctrlport_req_rd),
-    .m_ctrlport_req_addr(m_ctrlport_req_addr),
-    .m_ctrlport_req_data(m_ctrlport_req_data),
-    .m_ctrlport_req_byte_en(${"m_ctrlport_req_byte_en" if config['control']['ctrlport']['byte_mode'] else ""}),        
-    .m_ctrlport_req_has_time(${"m_ctrlport_req_has_time" if config['control']['ctrlport']['timed'] else ""}),      
-    .m_ctrlport_req_time(${"m_ctrlport_req_time" if config['control']['ctrlport']['timed'] else ""}),              
-    .m_ctrlport_resp_ack(m_ctrlport_resp_ack),
-    .m_ctrlport_resp_status(${"m_ctrlport_resp_status" if config['control']['ctrlport']['has_status'] else "'h0"}),        
-    .m_ctrlport_resp_data(m_ctrlport_resp_data),
-    .s_ctrlport_req_wr(${"s_ctrlport_req_wr" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_rd(${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_addr(${"s_ctrlport_req_addr" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_portid(${"s_ctrlport_req_portid" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_rem_epid(${"s_ctrlport_req_rem_epid" if config['control']['interface_direction'] == "remote_master_slave" else "'h0"}),
-    .s_ctrlport_req_rem_portid(${"s_ctrlport_req_rem_portid" if config['control']['interface_direction'] == "remote_master_slave" else "'h0"}),
-    .s_ctrlport_req_data(${"s_ctrlport_req_data" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_byte_en(${"s_ctrlport_req_byte_en" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_has_time(${"s_ctrlport_req_has_time" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_time(${"s_ctrlport_req_time" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_resp_ack(${"s_ctrlport_resp_ack" if config['control']['interface_direction'] != "slave" else ""}),
-    .s_ctrlport_resp_status(${"s_ctrlport_resp_status" if config['control']['interface_direction'] != "slave" else ""}),
-    .s_ctrlport_resp_data(${"s_ctrlport_resp_data" if config['control']['interface_direction'] != "slave" else ""})
-    );
-  
\ No newline at end of file
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (rfnoc_ctrl_rst),
+    .ctrlport_clk              (ctrlport_clk),
+    .ctrlport_rst              (ctrlport_rst),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .m_ctrlport_req_wr         (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd         (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr       (m_ctrlport_req_addr),
+    .m_ctrlport_req_data       (m_ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (${"m_ctrlport_req_byte_en" if config['control']['ctrlport']['byte_mode'] else ""}),
+    .m_ctrlport_req_has_time   (${"m_ctrlport_req_has_time" if config['control']['ctrlport']['timed'] else ""}),
+    .m_ctrlport_req_time       (${"m_ctrlport_req_time" if config['control']['ctrlport']['timed'] else ""}),
+    .m_ctrlport_resp_ack       (m_ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (${"m_ctrlport_resp_status" if config['control']['ctrlport']['has_status'] else "2'b0"}),
+    .m_ctrlport_resp_data      (m_ctrlport_resp_data),
+    .s_ctrlport_req_wr         (${"s_ctrlport_req_wr" if config['control']['interface_direction'] != "slave" else "1'b0"}),
+    .s_ctrlport_req_rd         (${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "slave" else "1'b0"}),
+    .s_ctrlport_req_addr       (${"s_ctrlport_req_addr" if config['control']['interface_direction'] != "slave" else "20'b0"}),
+    .s_ctrlport_req_portid     (${"s_ctrlport_req_portid" if config['control']['interface_direction'] != "slave" else "10'b0"}),
+    .s_ctrlport_req_rem_epid   (${"s_ctrlport_req_rem_epid" if config['control']['interface_direction'] == "remote_master_slave" else "16'b0"}),
+    .s_ctrlport_req_rem_portid (${"s_ctrlport_req_rem_portid" if config['control']['interface_direction'] == "remote_master_slave" else "10'b0"}),
+    .s_ctrlport_req_data       (${"s_ctrlport_req_data" if config['control']['interface_direction'] != "slave" else "32'b0"}),
+    .s_ctrlport_req_byte_en    (${"s_ctrlport_req_byte_en" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['byte_mode'] else "4'hF"}),
+    .s_ctrlport_req_has_time   (${"s_ctrlport_req_has_time" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['timed'] else "1'b0"}),
+    .s_ctrlport_req_time       (${"s_ctrlport_req_time" if config['control']['interface_direction'] != "slave"  and config['control']['ctrlport']['timed'] else "64'b0"}),
+    .s_ctrlport_resp_ack       (${"s_ctrlport_resp_ack" if config['control']['interface_direction'] != "slave" else ""}),
+    .s_ctrlport_resp_status    (${"s_ctrlport_resp_status" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['has_status'] else ""}),
+    .s_ctrlport_resp_data      (${"s_ctrlport_resp_data" if config['control']['interface_direction'] != "slave" else ""})
+  );
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
index 6d149ae6b..8d989677a 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
@@ -14,7 +14,7 @@
     ma_wire = ""
     term = ";"
 %>\
-  // Control Port Master
+  // CtrlPort Master
   ${ma_wire}wire               ${ma_pre}ctrlport_req_wr${term}
   ${ma_wire}wire               ${ma_pre}ctrlport_req_rd${term}
   ${ma_wire}wire [19:0]        ${ma_pre}ctrlport_req_addr${term}
@@ -23,7 +23,7 @@
   ${ma_wire}wire [3:0]         ${ma_pre}ctrlport_req_byte_en${term}
 %endif
 %if config['control']['ctrlport']['timed']:
-  ${ma_wire}wire               ${ma_pre}ctrlport_req_ha${sl_pre}time${term}
+  ${ma_wire}wire               ${ma_pre}ctrlport_req_has_time${term}
   ${ma_wire}wire [63:0]        ${ma_pre}ctrlport_req_time${term}
 %endif
   ${sl_wire}wire               ${ma_pre}ctrlport_resp_ack${term}
@@ -31,9 +31,8 @@
   ${sl_wire}wire [1:0]         ${ma_pre}ctrlport_resp_status${term}
 %endif
   ${sl_wire}wire [31:0]        ${ma_pre}ctrlport_resp_data${term}
-
 %if config['control']['interface_direction'] != "slave":
-  // Control Port Slave
+  // CtrlPort Slave
   ${sl_wire}wire               ${sl_pre}ctrlport_req_wr${term}
   ${sl_wire}wire               ${sl_pre}ctrlport_req_rd${term}
   ${sl_wire}wire [19:0]        ${sl_pre}ctrlport_req_addr${term}