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| author | Wade Fife <wade.fife@ettus.com> | 2020-01-31 07:41:21 -0600 |
|---|---|---|
| committer | Wade Fife <32272501+wordimont@users.noreply.github.com> | 2020-02-06 14:50:33 -0600 |
| commit | 26085ecf1a87efadba60bbc29bb5811f82f3c741 (patch) | |
| tree | 69a78bcd96c321be02bb8ba8ef46bd20f45d2a00 /host/utils/rfnoc_blocktool/templates/modules | |
| parent | 6f96639d25e3c6103048aa9809420e897970def0 (diff) | |
| download | uhd-26085ecf1a87efadba60bbc29bb5811f82f3c741.tar.gz uhd-26085ecf1a87efadba60bbc29bb5811f82f3c741.tar.bz2 uhd-26085ecf1a87efadba60bbc29bb5811f82f3c741.zip | |
fixup! utils: blocktool: Fix blocktool
Diffstat (limited to 'host/utils/rfnoc_blocktool/templates/modules')
| -rw-r--r-- | host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako index 4d3c719ae..9b33b84d1 100644 --- a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako +++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako @@ -28,7 +28,7 @@ ${out_wire}wire [${num_ports}-1:0] ${ma_pre}${port_name}_axis_tlast${term} ${out_wire}wire [${num_ports}-1:0] ${ma_pre}${port_name}_axis_tvalid${term} ${in_wire}wire [${num_ports}-1:0] ${ma_pre}${port_name}_axis_tready${term} - ${out_wire}wire [${num_ports}*CHDR_W-1:0] ${ma_pre}${port_name}_axis_ttimestamp${term} + ${out_wire}wire [${num_ports}*64-1:0] ${ma_pre}${port_name}_axis_ttimestamp${term} ${out_wire}wire [${num_ports}-1:0] ${ma_pre}${port_name}_axis_thas_time${term} ${out_wire}wire [${num_ports}*16-1:0] ${ma_pre}${port_name}_axis_tlength${term} ${out_wire}wire [${num_ports}-1:0] ${ma_pre}${port_name}_axis_teov${term} @@ -40,7 +40,7 @@ ${out_wire}wire ${ma_pre}${port_name}_axis_tlast${term} ${out_wire}wire ${ma_pre}${port_name}_axis_tvalid${term} ${in_wire}wire ${ma_pre}${port_name}_axis_tready${term} - ${out_wire}wire [CHDR_W-1:0] ${ma_pre}${port_name}_axis_ttimestamp${term} + ${out_wire}wire [63:0] ${ma_pre}${port_name}_axis_ttimestamp${term} ${out_wire}wire ${ma_pre}${port_name}_axis_thas_time${term} ${out_wire}wire [15:0] ${ma_pre}${port_name}_axis_tlength${term} ${out_wire}wire ${ma_pre}${port_name}_axis_teov${term} @@ -59,7 +59,7 @@ ${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_tlast${term} ${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_tvalid${term} ${out_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_tready${term} - ${in_wire}wire [${num_ports}*CHDR_W-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term} + ${in_wire}wire [${num_ports}*64-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term} ${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_thas_time${term} ${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_teov${term} ${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) else ""} @@ -70,7 +70,7 @@ ${in_wire}wire ${sl_pre}${port_name}_axis_tlast${term} ${in_wire}wire ${sl_pre}${port_name}_axis_tvalid${term} ${out_wire}wire ${sl_pre}${port_name}_axis_tready${term} - ${in_wire}wire [CHDR_W-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term} + ${in_wire}wire [63:0] ${sl_pre}${port_name}_axis_ttimestamp${term} ${in_wire}wire ${sl_pre}${port_name}_axis_thas_time${term} ${in_wire}wire ${sl_pre}${port_name}_axis_teov${term} ${in_wire}wire ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_outputs - 1) else ""} |