| Commit message (Collapse) | Author | Age | Files | Lines |
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- Delays changed after ADC config change and FPGA fixes
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- radio_rst was being asserted to reset the capture iface IDELAYs but
that was excessive and had adverse effects on the rest of the radio
- Replaced radio_rst with a localized IDELAYCTRL reset
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This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
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- The following function implementations were moved from x300_impl.cpp
to x300_adc_dac_utils.cpp
- synchronize_dacs
- self_test_adcs
- extended_adc_test
- self_cal_adc_capture_delay
- self_cal_adc_xfer_delay
- This reduces the size of the x300_impl object file
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- We added additional microcode to configure DCI matching,config rate,etc
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- The value was originally empirically determined based on self-cal
results. After the fix for uncalibrated IDELAY, the self-cal offset
data was no longer correct.
- The new delay through the ADC ensures that the self-cal nominally
pick the halfway tap of 16
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- Everytime the LMK is configured, we do the following:
- Reset all LMK regs
- Wait for LMK lock
- Reset radio_clk PLL in FPGA
- Wait for FPGA PLL to lock
- Assert radio_rst which resets downstream radio logic
- This address the intermittent self-cal failures due to uncalibrated IDELAY taps
- Bumped FPGA compat to 12
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- This changed with the ADS62P44 -> ADS62P48 design change
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- New device arg "ext_adc_self_test" triggers the test
- ext_adc_self_test=<time> runs the test for "time" seconds
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- product code, revision and revision compat errors are now exceptions
- Added recover_mb_eeprom arg to recover from a corrupt/uninitialized EEPROM
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- Added new field "revision_compat" to mb_eeprom
- Enforce a revision_compat of 7
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- Added new PCIe and MB PIDs for new boards
- Added an error if MB PID is invalid
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* Single class for loading firmware/FPGA images onto devices instead of multiple utilities
* Loading functions are registered for each device, corresponding to their --args="type=foo" name
* Deprecation warnings added to all product-specific image loading utilities
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- B2x0: FW compat number (goes with previous firmware update)
- X3x0: Max HW rev number
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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- If the self-cal fails, UHD waits for 2 sec for the ADC temp
to stabilize and retries the self-cal
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- Characterized over process and temperature
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- Self-calibration routine steps through various values of IDELAY
taps on the SS data bits to detect metastability in the capture interface
and computes an ideal delay tap value
- Self calibration is triggered at device creation
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- Self-calibration routine steps through various values of LMK
delay to detect metastability in the SSCLK -> radio_clk crossing
and computes an ideal delay for the ADC clock.
- Self calibration is triggered at startup if the self_cal_adc_delay
device arg is specified
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- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
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Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
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- The firmware is a subset of the FPGA so this order makes sense
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Conflicts:
host/lib/usrp/x300/x300_clock_ctrl.cpp
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This creates a wb_iface child class called timed_wb_iface, which
adds support for timed commands.
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Conflicts:
host/docs/usrp_e3x0.dox
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- Increased filter loop bandwith on clock control chip
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* CMake now not applying C++ flags to C files
* GCC 4.4: anti-aliasing rules
* MSVC: narrowing, differences in subclass function parameters
* Clang: uninitialized variables
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- GPIO on UART connector all board Revs
- Consolidated fpgpio_bitbang into fpgpio example and renamed it gpio
- Changed FP_GPIO readback address to match X300
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