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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-23 22:42:08 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-23 22:42:08 -0700 |
| commit | f530b02cbf2ed6ea126a2774803b2c687c24efbc (patch) | |
| tree | 0479650ef1e7968f2d232808ba5537a0616c32be /host/lib/usrp/x300 | |
| parent | 86924e9cca30b3f4d61fa2d2697d742afa6f73b0 (diff) | |
| download | uhd-f530b02cbf2ed6ea126a2774803b2c687c24efbc.tar.gz uhd-f530b02cbf2ed6ea126a2774803b2c687c24efbc.tar.bz2 uhd-f530b02cbf2ed6ea126a2774803b2c687c24efbc.zip | |
x300: Removed radio_rst assertion code
- radio_rst was being asserted to reset the capture iface IDELAYs but
that was excessive and had adverse effects on the rest of the radio
- Replaced radio_rst with a localized IDELAYCTRL reset
Diffstat (limited to 'host/lib/usrp/x300')
| -rw-r--r-- | host/lib/usrp/x300/x300_fw_common.h | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_regs.hpp | 1 |
3 files changed, 4 insertions, 3 deletions
diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h index e137b916b..6493e938d 100644 --- a/host/lib/usrp/x300/x300_fw_common.h +++ b/host/lib/usrp/x300/x300_fw_common.h @@ -33,7 +33,7 @@ extern "C" { #define X300_REVISION_MIN 2 #define X300_FW_COMPAT_MAJOR 4 #define X300_FW_COMPAT_MINOR 0 -#define X300_FPGA_COMPAT_MAJOR 12 +#define X300_FPGA_COMPAT_MAJOR 13 //shared memory sections - in between the stack and the program space #define X300_FW_SHMEM_BASE 0x6000 diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 82ed5bfe2..903b63198 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1455,8 +1455,8 @@ void x300_impl::update_clock_source(mboard_members_t &mb, const std::string &sou throw uhd::runtime_error((boost::format("Reference Clock PLL in FPGA failed to lock to %s source.") % source).str()); } - //Reset the logic in the radio clock domain - mb.zpu_ctrl->poke32(SR_ADDR(SET0_BASE, ZPU_SR_SW_RST), ZPU_SR_SW_RST_RADIO_RST); + //Reset the IDELAYCTRL used to calibrate the data interface delays + mb.zpu_ctrl->poke32(SR_ADDR(SET0_BASE, ZPU_SR_SW_RST), ZPU_SR_SW_RST_ADC_IDELAYCTRL); mb.zpu_ctrl->poke32(SR_ADDR(SET0_BASE, ZPU_SR_SW_RST), 0); //Wait for the ADC IDELAYCTRL to be ready diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp index fb3a42172..6e92a6dbc 100644 --- a/host/lib/usrp/x300/x300_regs.hpp +++ b/host/lib/usrp/x300/x300_regs.hpp @@ -74,6 +74,7 @@ localparam ZPU_SR_ETHINT1 = 56; #define ZPU_SR_SW_RST_ETH_PHY (1<<0) #define ZPU_SR_SW_RST_RADIO_RST (1<<1) #define ZPU_SR_SW_RST_RADIO_CLK_PLL (1<<2) +#define ZPU_SR_SW_RST_ADC_IDELAYCTRL (1<<3) //clock controls #define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL 0x00 |