Merge branch 'master' into ashish/vivado

4 files changed, 135 insertions, 148 deletions

diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index e35f73eab..d9b27b6b4 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2013-2014 Ettus Research LLC
+// Copyright 2013-2015 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -41,7 +41,7 @@
 
 #define NIUSRPRIO_DEFAULT_RPC_PORT "5444"
 
-#define X300_REV(x) (x - "A" + 1)
+#define X300_REV(x) ((x) - "A" + 1)
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -695,15 +695,14 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
     // front panel gpio
     ////////////////////////////////////////////////////////////////////
     mb.fp_gpio = gpio_core_200::make(mb.radio_perifs[0].ctrl, TOREG(SR_FP_GPIO), RB32_FP_GPIO);
-    const std::vector<std::string> GPIO_ATTRS = boost::assign::list_of("CTRL")("DDR")("OUT")("ATR_0X")("ATR_RX")("ATR_TX")("ATR_XX");
-    BOOST_FOREACH(const std::string &attr, GPIO_ATTRS)
+    BOOST_FOREACH(const gpio_attr_map_t::value_type attr, gpio_attr_map)
     {
-        _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / attr)
+        _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / attr.second)
             .set(0)
-            .subscribe(boost::bind(&x300_impl::set_fp_gpio, this, mb.fp_gpio, attr, _1));
+            .subscribe(boost::bind(&x300_impl::set_fp_gpio, this, mb.fp_gpio, attr.first, _1));
     }
     _tree->create<boost::uint32_t>(mb_path / "gpio" / "FP0" / "READBACK")
-        .publish(boost::bind(&x300_impl::get_fp_gpio, this, mb.fp_gpio, "READBACK"));
+        .publish(boost::bind(&x300_impl::get_fp_gpio, this, mb.fp_gpio));
 
     ////////////////////////////////////////////////////////////////////
     // register the time keepers - only one can be the highlander
@@ -1353,7 +1352,7 @@ void x300_impl::set_time_source_out(mboard_members_t &mb, const bool enb)
 void x300_impl::update_clock_source(mboard_members_t &mb, const std::string &source)
 {
     //Optimize for the case when the current source is internal and we are trying
-    //to set it to internal. This is the only case where we are guaranteed that 
+    //to set it to internal. This is the only case where we are guaranteed that
     //the clock has not gone away so we can skip setting the MUX and reseting the LMK.
     if (not (mb.current_refclk_src == "internal" and source == "internal")) {
         //Update the clock MUX on the motherboard to select the requested source
@@ -1432,8 +1431,8 @@ bool x300_impl::wait_for_ref_locked(wb_iface::sptr ctrl, double timeout)
         boost::this_thread::sleep(boost::posix_time::milliseconds(1));
     } while (boost::get_system_time() < timeout_time);
 
-    //failed to lock on reference
-    return false;
+    //Check one last time
+    return get_ref_locked(ctrl).to_bool();
 }
 
 sensor_value_t x300_impl::get_ref_locked(wb_iface::sptr ctrl)
@@ -1534,20 +1533,24 @@ void x300_impl::set_mb_eeprom(i2c_iface::sptr i2c, const mboard_eeprom_t &mb_eep
  * front-panel GPIO
  **********************************************************************/
 
-boost::uint32_t x300_impl::get_fp_gpio(gpio_core_200::sptr gpio, const std::string &)
+boost::uint32_t x300_impl::get_fp_gpio(gpio_core_200::sptr gpio)
 {
     return boost::uint32_t(gpio->read_gpio(dboard_iface::UNIT_RX));
 }
 
-void x300_impl::set_fp_gpio(gpio_core_200::sptr gpio, const std::string &attr, const boost::uint32_t value)
+void x300_impl::set_fp_gpio(gpio_core_200::sptr gpio, const gpio_attr_t attr, const boost::uint32_t value)
 {
-    if (attr == "CTRL") return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value);
-    if (attr == "DDR") return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value);
-    if (attr == "OUT") return gpio->set_gpio_out(dboard_iface::UNIT_RX, value);
-    if (attr == "ATR_0X") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value);
-    if (attr == "ATR_RX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value);
-    if (attr == "ATR_TX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value);
-    if (attr == "ATR_XX") return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value);
+    switch (attr)
+    {
+    case GPIO_CTRL:   return gpio->set_pin_ctrl(dboard_iface::UNIT_RX, value);
+    case GPIO_DDR:    return gpio->set_gpio_ddr(dboard_iface::UNIT_RX, value);
+    case GPIO_OUT:    return gpio->set_gpio_out(dboard_iface::UNIT_RX, value);
+    case GPIO_ATR_0X: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, value);
+    case GPIO_ATR_RX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, value);
+    case GPIO_ATR_TX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, value);
+    case GPIO_ATR_XX: return gpio->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, value);
+    default:        UHD_THROW_INVALID_CODE_PATH();
+    }
 }
 
 /***********************************************************************
@@ -1720,14 +1723,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
                 case X300_USRP_PCIE_SSID:
                     mb_type = USRP_X300_MB; break;
                 case X310_USRP_PCIE_SSID:
-                case X310_2940R_PCIE_SSID:
-                case X310_2942R_PCIE_SSID:
-                case X310_2943R_PCIE_SSID:
-                case X310_2944R_PCIE_SSID:
-                case X310_2950R_PCIE_SSID:
-                case X310_2952R_PCIE_SSID:
-                case X310_2953R_PCIE_SSID:
-                case X310_2954R_PCIE_SSID:
+                case X310_2940R_40MHz_PCIE_SSID:
+                case X310_2940R_120MHz_PCIE_SSID:
+                case X310_2942R_40MHz_PCIE_SSID:
+                case X310_2942R_120MHz_PCIE_SSID:
+                case X310_2943R_40MHz_PCIE_SSID:
+                case X310_2943R_120MHz_PCIE_SSID:
+                case X310_2944R_40MHz_PCIE_SSID:
+                case X310_2950R_40MHz_PCIE_SSID:
+                case X310_2950R_120MHz_PCIE_SSID:
+                case X310_2952R_40MHz_PCIE_SSID:
+                case X310_2952R_120MHz_PCIE_SSID:
+                case X310_2953R_40MHz_PCIE_SSID:
+                case X310_2953R_120MHz_PCIE_SSID:
+                case X310_2954R_40MHz_PCIE_SSID:
                     mb_type = USRP_X310_MB; break;
                 default:
                     mb_type = UNKNOWN;      break;
@@ -1755,14 +1764,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
             case X300_USRP_PCIE_SSID:
                 mb_type = USRP_X300_MB; break;
             case X310_USRP_PCIE_SSID:
-            case X310_2940R_PCIE_SSID:
-            case X310_2942R_PCIE_SSID:
-            case X310_2943R_PCIE_SSID:
-            case X310_2944R_PCIE_SSID:
-            case X310_2950R_PCIE_SSID:
-            case X310_2952R_PCIE_SSID:
-            case X310_2953R_PCIE_SSID:
-            case X310_2954R_PCIE_SSID:
+            case X310_2940R_40MHz_PCIE_SSID:
+            case X310_2940R_120MHz_PCIE_SSID:
+            case X310_2942R_40MHz_PCIE_SSID:
+            case X310_2942R_120MHz_PCIE_SSID:
+            case X310_2943R_40MHz_PCIE_SSID:
+            case X310_2943R_120MHz_PCIE_SSID:
+            case X310_2944R_40MHz_PCIE_SSID:
+            case X310_2950R_40MHz_PCIE_SSID:
+            case X310_2950R_120MHz_PCIE_SSID:
+            case X310_2952R_40MHz_PCIE_SSID:
+            case X310_2952R_120MHz_PCIE_SSID:
+            case X310_2953R_40MHz_PCIE_SSID:
+            case X310_2953R_120MHz_PCIE_SSID:
+            case X310_2954R_40MHz_PCIE_SSID:
                 mb_type = USRP_X310_MB; break;
             default:
                 UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl;
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp
index 70c5dccb4..9ad060c85 100644
--- a/host/lib/usrp/x300/x300_impl.hpp
+++ b/host/lib/usrp/x300/x300_impl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2013-2014 Ettus Research LLC
+// Copyright 2013-2015 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -360,8 +360,8 @@ private:
     void check_fpga_compat(const uhd::fs_path &mb_path, uhd::wb_iface::sptr iface);
 
     void update_atr_leds(gpio_core_200_32wo::sptr, const std::string &ant);
-    boost::uint32_t get_fp_gpio(gpio_core_200::sptr, const std::string &);
-    void set_fp_gpio(gpio_core_200::sptr, const std::string &, const boost::uint32_t);
+    boost::uint32_t get_fp_gpio(gpio_core_200::sptr);
+    void set_fp_gpio(gpio_core_200::sptr, const gpio_attr_t, const boost::uint32_t);
 
     //**PRECONDITION**
     //This function assumes that all the VITA times in "radios" are synchronized
diff --git a/host/lib/usrp/x300/x300_io_impl.cpp b/host/lib/usrp/x300/x300_io_impl.cpp
index 334ae8168..e3515af0c 100644
--- a/host/lib/usrp/x300/x300_io_impl.cpp
+++ b/host/lib/usrp/x300/x300_io_impl.cpp
@@ -23,6 +23,7 @@
 #include <uhd/transport/nirio_zero_copy.hpp>
 #include "async_packet_handler.hpp"
 #include <uhd/transport/bounded_buffer.hpp>
+#include <uhd/transport/chdr.hpp>
 #include <boost/bind.hpp>
 #include <uhd/utils/tasks.hpp>
 #include <uhd/utils/log.hpp>
@@ -124,41 +125,6 @@ void x300_impl::update_subdev_spec(const std::string &tx_rx, const size_t mb_i,
 
 
 /***********************************************************************
- * VITA stuff
- **********************************************************************/
-static void x300_if_hdr_unpack_be(
-    const boost::uint32_t *packet_buff,
-    vrt::if_packet_info_t &if_packet_info
-){
-    if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR;
-    return vrt::if_hdr_unpack_be(packet_buff, if_packet_info);
-}
-
-static void x300_if_hdr_pack_be(
-    boost::uint32_t *packet_buff,
-    vrt::if_packet_info_t &if_packet_info
-){
-    if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR;
-    return vrt::if_hdr_pack_be(packet_buff, if_packet_info);
-}
-
-static void x300_if_hdr_unpack_le(
-    const boost::uint32_t *packet_buff,
-    vrt::if_packet_info_t &if_packet_info
-){
-    if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR;
-    return vrt::if_hdr_unpack_le(packet_buff, if_packet_info);
-}
-
-static void x300_if_hdr_pack_le(
-    boost::uint32_t *packet_buff,
-    vrt::if_packet_info_t &if_packet_info
-){
-    if_packet_info.link_type = vrt::if_packet_info_t::LINK_TYPE_CHDR;
-    return vrt::if_hdr_pack_le(packet_buff, if_packet_info);
-}
-
-/***********************************************************************
  * RX flow control handler
  **********************************************************************/
 static size_t get_rx_flow_control_window(size_t frame_size, size_t sw_buff_size, const device_addr_t& rx_args)
@@ -209,9 +175,9 @@ static void handle_rx_flowctrl(const boost::uint32_t sid, zero_copy_if::sptr xpo
 
     //load header
     if (big_endian)
-        x300_if_hdr_pack_be(pkt, packet_info);
+        vrt::chdr::if_hdr_pack_be(pkt, packet_info);
     else
-        x300_if_hdr_pack_le(pkt, packet_info);
+        vrt::chdr::if_hdr_pack_le(pkt, packet_info);
 
     //load payload
     pkt[packet_info.num_header_words32+0] = uhd::htonx<boost::uint32_t>(0);
@@ -276,12 +242,12 @@ static void handle_tx_async_msgs(boost::shared_ptr<x300_tx_fc_guts_t> guts, zero
     {
         if (big_endian)
         {
-            x300_if_hdr_unpack_be(packet_buff, if_packet_info);
+            vrt::chdr::if_hdr_unpack_be(packet_buff, if_packet_info);
             endian_conv = uhd::ntohx;
         }
         else
         {
-            x300_if_hdr_unpack_le(packet_buff, if_packet_info);
+            vrt::chdr::if_hdr_unpack_le(packet_buff, if_packet_info);
             endian_conv = uhd::wtohx;
         }
     }
@@ -430,10 +396,10 @@ rx_streamer::sptr x300_impl::get_rx_stream(const uhd::stream_args_t &args_)
         //init some streamer stuff
         std::string conv_endianness;
         if (mb.if_pkt_is_big_endian) {
-            my_streamer->set_vrt_unpacker(&x300_if_hdr_unpack_be);
+            my_streamer->set_vrt_unpacker(&vrt::chdr::if_hdr_unpack_be);
             conv_endianness = "be";
         } else {
-            my_streamer->set_vrt_unpacker(&x300_if_hdr_unpack_le);
+            my_streamer->set_vrt_unpacker(&vrt::chdr::if_hdr_unpack_le);
             conv_endianness = "le";
         }
 
@@ -594,10 +560,10 @@ tx_streamer::sptr x300_impl::get_tx_stream(const uhd::stream_args_t &args_)
 
         std::string conv_endianness;
         if (mb.if_pkt_is_big_endian) {
-            my_streamer->set_vrt_packer(&x300_if_hdr_pack_be);
+            my_streamer->set_vrt_packer(&vrt::chdr::if_hdr_pack_be);
             conv_endianness = "be";
         } else {
-            my_streamer->set_vrt_packer(&x300_if_hdr_pack_le);
+            my_streamer->set_vrt_packer(&vrt::chdr::if_hdr_pack_le);
             conv_endianness = "le";
         }
 
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index f920b5ae2..4c5729efe 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -25,40 +25,40 @@
 
 #define localparam static const int
 
-localparam SR_DACSYNC   = 5;
-localparam SR_LOOPBACK  = 6;
-localparam SR_TEST      = 7;
-localparam SR_SPI       = 8;
-localparam SR_GPIO      = 16;
-localparam SR_MISC_OUTS = 24;
-localparam SR_READBACK  = 32;
-localparam SR_TX_CTRL   = 64;
-localparam SR_RX_CTRL   = 96;
-localparam SR_TIME      = 128;
-localparam SR_RX_DSP    = 144;
-localparam SR_TX_DSP    = 184;
-localparam SR_LEDS      = 195;
-localparam SR_FP_GPIO   = 200;
-localparam SR_RX_FRONT  = 208;
-localparam SR_TX_FRONT  = 216;
-
-localparam RB32_GPIO            = 0;
-localparam RB32_SPI             = 4;
-localparam RB64_TIME_NOW        = 8;
-localparam RB64_TIME_PPS        = 16;
-localparam RB32_TEST            = 24;
-localparam RB32_RX              = 28;
-localparam RB32_FP_GPIO         = 32;
-
-localparam BL_ADDRESS     = 0;
-localparam BL_DATA        = 1;
+localparam SR_DACSYNC    = 5;
+localparam SR_LOOPBACK   = 6;
+localparam SR_TEST       = 7;
+localparam SR_SPI        = 8;
+localparam SR_GPIO       = 16;
+localparam SR_MISC_OUTS  = 24;
+localparam SR_READBACK   = 32;
+localparam SR_TX_CTRL    = 64;
+localparam SR_RX_CTRL    = 96;
+localparam SR_TIME       = 128;
+localparam SR_RX_DSP     = 144;
+localparam SR_TX_DSP     = 184;
+localparam SR_LEDS       = 195;
+localparam SR_FP_GPIO    = 200;
+localparam SR_RX_FRONT   = 208;
+localparam SR_TX_FRONT   = 216;
+
+localparam RB32_GPIO     = 0;
+localparam RB32_SPI      = 4;
+localparam RB64_TIME_NOW = 8;
+localparam RB64_TIME_PPS = 16;
+localparam RB32_TEST     = 24;
+localparam RB32_RX       = 28;
+localparam RB32_FP_GPIO  = 32;
+
+localparam BL_ADDRESS    = 0;
+localparam BL_DATA       = 1;
 
 //wishbone settings map - relevant to host code
-#define SET0_BASE 0xa000
-#define SETXB_BASE 0xb000
-#define BOOT_LDR_BASE 0xFA00
-#define I2C0_BASE 0xfe00
-#define I2C1_BASE 0xff00
+#define SET0_BASE     0xa000
+#define SETXB_BASE    0xb000
+#define BOOT_LDR_BASE 0xfa00
+#define I2C0_BASE     0xfe00
+#define I2C1_BASE     0xff00
 #define SR_ADDR(base, offset) ((base) + (offset)*4)
 
 localparam ZPU_SR_LEDS       = 00;
@@ -70,56 +70,62 @@ localparam ZPU_SR_ETHINT0    = 40;
 localparam ZPU_SR_ETHINT1    = 56;
 
 //clock controls
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL  0x00
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL  0x02
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO     0x03
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL  0x00
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL  0x02
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO     0x03
-
-localparam ZPU_RB_SPI = 2;
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL 0x00
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL 0x02
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO    0x03
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL 0x00
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL 0x02
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO    0x03
+
+localparam ZPU_RB_SPI        = 2;
 localparam ZPU_RB_CLK_STATUS = 3;
 localparam ZPU_RB_COMPAT_NUM = 6;
 localparam ZPU_RB_ETH_TYPE0  = 4;
 localparam ZPU_RB_ETH_TYPE1  = 5;
 
 //clock status
-#define ZPU_RB_CLK_STATUS_LMK_STATUS    (0x3 << 0)
-#define ZPU_RB_CLK_STATUS_LMK_LOCK      (0x1 << 2)
-#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER  (0x1 << 3)
-#define ZPU_RB_CLK_STATUS_PPS_DETECT    (0x1 << 4)
+#define ZPU_RB_CLK_STATUS_LMK_STATUS   (0x3 << 0)
+#define ZPU_RB_CLK_STATUS_LMK_LOCK     (0x1 << 2)
+#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER (0x1 << 3)
+#define ZPU_RB_CLK_STATUS_PPS_DETECT   (0x1 << 4)
 
 //spi slaves on radio
-#define DB_DAC_SEN (1 << 7)
-#define DB_ADC_SEN (1 << 6)
+#define DB_DAC_SEN      (1 << 7)
+#define DB_ADC_SEN      (1 << 6)
 #define DB_RX_LSADC_SEN (1 << 5)
 #define DB_RX_LSDAC_SEN (1 << 4)
 #define DB_TX_LSADC_SEN (1 << 3)
 #define DB_TX_LSDAC_SEN (1 << 2)
-#define DB_RX_SEN (1 << 1)
-#define DB_TX_SEN (1 << 0)
+#define DB_RX_SEN       (1 << 1)
+#define DB_TX_SEN       (1 << 0)
 
 //-------------------------------------------------------------------
 // PCIe Registers
 //-------------------------------------------------------------------
 
-static const uint32_t X300_PCIE_VID         = 0x1093;
-static const uint32_t X300_PCIE_PID         = 0xC4C4;
-static const uint32_t X300_USRP_PCIE_SSID   = 0x7736;
-static const uint32_t X310_USRP_PCIE_SSID   = 0x76CA;
-static const uint32_t X310_2940R_PCIE_SSID  = 0x772B;
-static const uint32_t X310_2942R_PCIE_SSID  = 0x772C;
-static const uint32_t X310_2943R_PCIE_SSID  = 0x772D;
-static const uint32_t X310_2944R_PCIE_SSID  = 0x772E;
-static const uint32_t X310_2950R_PCIE_SSID  = 0x772F;
-static const uint32_t X310_2952R_PCIE_SSID  = 0x7730;
-static const uint32_t X310_2953R_PCIE_SSID  = 0x7731;
-static const uint32_t X310_2954R_PCIE_SSID  = 0x7732;
+static const uint32_t X300_PCIE_VID               = 0x1093;
+static const uint32_t X300_PCIE_PID               = 0xC4C4;
+static const uint32_t X300_USRP_PCIE_SSID         = 0x7736;
+static const uint32_t X310_USRP_PCIE_SSID         = 0x76CA;
+static const uint32_t X310_2940R_40MHz_PCIE_SSID  = 0x772B;
+static const uint32_t X310_2940R_120MHz_PCIE_SSID = 0x77FB;
+static const uint32_t X310_2942R_40MHz_PCIE_SSID  = 0x772C;
+static const uint32_t X310_2942R_120MHz_PCIE_SSID = 0x77FC;
+static const uint32_t X310_2943R_40MHz_PCIE_SSID  = 0x772D;
+static const uint32_t X310_2943R_120MHz_PCIE_SSID = 0x77FD;
+static const uint32_t X310_2944R_40MHz_PCIE_SSID  = 0x772E;
+static const uint32_t X310_2950R_40MHz_PCIE_SSID  = 0x772F;
+static const uint32_t X310_2950R_120MHz_PCIE_SSID = 0x77FE;
+static const uint32_t X310_2952R_40MHz_PCIE_SSID  = 0x7730;
+static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF;
+static const uint32_t X310_2953R_40MHz_PCIE_SSID  = 0x7731;
+static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800;
+static const uint32_t X310_2954R_40MHz_PCIE_SSID  = 0x7732;
 
 static const uint32_t FPGA_X3xx_SIG_VALUE   = 0x58333030;
 
 static const uint32_t PCIE_FPGA_ADDR_BASE   = 0xC0000;
-#define PCIE_FPGA_REG(X)                    (PCIE_FPGA_ADDR_BASE + X)
+#define PCIE_FPGA_REG(X)                    (PCIE_FPGA_ADDR_BASE + (X))
 
 static const uint32_t FPGA_PCIE_SIG_REG     = PCIE_FPGA_REG(0x0000);
 static const uint32_t FPGA_CNTR_LO_REG      = PCIE_FPGA_REG(0x0004);
@@ -140,8 +146,8 @@ static const uint32_t DMA_FRAME_SIZE_REG    = 0x4;
 static const uint32_t DMA_SAMPLE_COUNT_REG  = 0x8;
 static const uint32_t DMA_PKT_COUNT_REG     = 0xC;
 
-#define PCIE_TX_DMA_REG(REG, CHAN)          (PCIE_TX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG)
-#define PCIE_RX_DMA_REG(REG, CHAN)          (PCIE_RX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG)
+#define PCIE_TX_DMA_REG(REG, CHAN)          (PCIE_TX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG))
+#define PCIE_RX_DMA_REG(REG, CHAN)          (PCIE_RX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG))
 
 static const uint32_t DMA_CTRL_DISABLED     = 0x00000000;
 static const uint32_t DMA_CTRL_ENABLED      = 0x00000002;
@@ -154,15 +160,15 @@ static const uint32_t DMA_STATUS_ERROR      = 0x00000001;
 static const uint32_t DMA_STATUS_BUSY       = 0x00000002;
 
 static const uint32_t PCIE_ROUTER_REG_BASE  = PCIE_FPGA_REG(0x0500);
-#define PCIE_ROUTER_REG(X)                  (PCIE_ROUTER_REG_BASE + X)
+#define PCIE_ROUTER_REG(X)                  (PCIE_ROUTER_REG_BASE + (X))
 
 static const uint32_t PCIE_ZPU_DATA_BASE    = 0x30000;
 static const uint32_t PCIE_ZPU_READ_BASE    = 0x20000;  //Trig and Status share the same base
 static const uint32_t PCIE_ZPU_STATUS_BASE  = 0x20000;
 
-#define PCIE_ZPU_DATA_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + X)
-#define PCIE_ZPU_READ_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + X)
-#define PCIE_ZPU_STATUS_REG(X)              (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + X)
+#define PCIE_ZPU_DATA_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + (X))
+#define PCIE_ZPU_READ_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + (X))
+#define PCIE_ZPU_STATUS_REG(X)              (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + (X))
 
 static const uint32_t PCIE_ZPU_READ_START       = 0x0;
 static const uint32_t PCIE_ZPU_READ_CLOBBER     = 0x80000000;