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* b2xx,e3xx,x300: Bumped FPGA compat numbers after SW time-sync changesAshish Chaudhari2015-12-101-1/+1
| | | | | | | - b200: compat 13 - b200mini: compat 4 - e3xx: compat 14 - x3xx: compat 19
* Bumped FPGA compat numbers for B200, X300, and E300.michael-west2015-12-101-1/+1
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* E300/X300: Add VITA time synchronization on internal signalmichael-west2015-12-103-2/+13
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* b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-031-1/+1
| | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
* cores: Corrected scaling_adjustment calculationIan Buckley2015-09-032-0/+10
| | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* X300: Fix base address for FP GPIOmichael-west2015-09-011-1/+1
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* x300: Removed call to is_pps_presentAshish Chaudhari2015-08-171-4/+4
| | | | - It's status is thrown away anyway
* b200,e300,x300: Updated compat number for release 3.9.0Ashish Chaudhari2015-08-141-1/+1
| | | | | | - b200: compat 10 - e300: compat 10 - x300: compat 14
* uhd: Fixes to build with MSVCAshish Chaudhari2015-08-131-1/+1
| | | | | - Included list header in soft_reg header - Fixed typo in x300_impl
* B200/X300: Make default clock and time sources internalmichael-west2015-08-121-14/+0
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* UHD: Remove initialization of time to GPS time.michael-west2015-08-121-4/+1
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* Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-121-1/+1
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| * cmake: added variable to LIBUHD_REGISTER_COMPONENT macro to make required, ↵Nicholas Corgan2015-08-111-1/+1
| | | | | | | | | | | | set LibUHD to required * If required component's dependencies aren't met, CMake will throw an error unless user specifically disables it
* | Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-104-58/+80
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| * x300: added missing included necessary in Boost 1.46Nicholas Corgan2015-08-101-0/+1
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| * x300, e300: Moved common register names to radio namespaceMartin Braun2015-08-074-48/+55
| | | | | | | | This preps the code for merging common registers altogether.
| * image_loader: force user to specify deviceNicholas Corgan2015-08-051-9/+23
| | | | | | | | | | * On utility level, force user to use --args=type=foo * In each loader, throw an error if args are ambiguous
| * x300: nirio: Fix compiler warningsMoritz Fischer2015-07-311-1/+1
| | | | | | | | | | | | | | | | | | The old code used a non standard (though very common) way to determine the size of an array. In order to avoid warnings, pass another parameter to indicate the size. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* | x300: Used new soft register API for X300 registersAshish Chaudhari2015-08-044-176/+196
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* x300: Moved all tick set subscribers to same placeMartin Braun2015-07-291-10/+7
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* cores: Moved subtree populate code to DSP cores (X3x0, E310)Martin Braun2015-07-291-36/+26
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* cores: Moved subtree populate code to frontend coresMartin Braun2015-07-291-20/+8
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* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
| | | | - Delays changed after ADC config change and FPGA fixes
* x300: Removed radio_rst assertion codeAshish Chaudhari2015-07-233-3/+4
| | | | | | - radio_rst was being asserted to reset the capture iface IDELAYs but that was excessive and had adverse effects on the rest of the radio - Replaced radio_rst with a localized IDELAYCTRL reset
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
| | | | This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
* x300: Moved system-level ADC and DAC operationsAshish Chaudhari2015-07-233-386/+413
| | | | | | | | | | | - The following function implementations were moved from x300_impl.cpp to x300_adc_dac_utils.cpp - synchronize_dacs - self_test_adcs - extended_adc_test - self_cal_adc_capture_delay - self_cal_adc_xfer_delay - This reduces the size of the x300_impl object file
* x300: Increased the max image size for burnerAshish Chaudhari2015-07-231-1/+1
| | | | - We added additional microcode to configure DCI matching,config rate,etc
* x300: Updated CLK->DATA delay for ADCAshish Chaudhari2015-07-221-2/+2
| | | | | | | | - The value was originally empirically determined based on self-cal results. After the fix for uncalibrated IDELAY, the self-cal offset data was no longer correct. - The new delay through the ADC ensures that the self-cal nominally pick the halfway tap of 16
* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-224-32/+68
| | | | | | | | | | | - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12
* x300: Minor: Optimized ADC/DAC resetsAshish Chaudhari2015-07-221-11/+11
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* x300: Changed ADC clock swing to 1.6V from 0.7VAshish Chaudhari2015-07-221-2/+2
| | | | - This changed with the ADS62P44 -> ADS62P48 design change
* x300: Addressed code review feedback for Rev7+ supportAshish Chaudhari2015-07-203-118/+126
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* x300: Added extended ADC self-testAshish Chaudhari2015-07-192-9/+68
| | | | | - New device arg "ext_adc_self_test" triggers the test - ext_adc_self_test=<time> runs the test for "time" seconds
* x300: Made all X300 revision related errors fatalAshish Chaudhari2015-07-191-13/+20
| | | | | - product code, revision and revision compat errors are now exceptions - Added recover_mb_eeprom arg to recover from a corrupt/uninitialized EEPROM
* x300: Added HW rev compat number supportAshish Chaudhari2015-07-182-12/+27
| | | | | - Added new field "revision_compat" to mb_eeprom - Enforce a revision_compat of 7
* x300: Added new Rev7+ X3x0 MB product codesAshish Chaudhari2015-07-182-2/+54
| | | | | - Added new PCIe and MB PIDs for new boards - Added an error if MB PID is invalid
* x300: Bumped max HW rev to 8Martin Braun2015-07-161-1/+1
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* Added uhd::image_loader class and uhd_image_loader utilityNicholas Corgan2015-07-156-8/+538
| | | | | | * Single class for loading firmware/FPGA images onto devices instead of multiple utilities * Loading functions are registered for each device, corresponding to their --args="type=foo" name * Deprecation warnings added to all product-specific image loading utilities
* Merge branch 'maint'Martin Braun2015-07-141-1/+0
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| * x300: Removed stray debug printMartin Braun2015-07-141-1/+0
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* | Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-141-1/+1
| | | | | | | | | | - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
* | Merge branch 'maint'Martin Braun2015-07-142-0/+11
|\| | | | | | | | | | | | | | | | | | | Conflicts: fpga-src host/CMakeLists.txt host/cmake/Modules/UHDVersion.cmake host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * x300: Added max hw rev checkingMartin Braun2015-07-142-0/+11
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* | x300: Added retry mechanism to ADC capture delay self-calAshish Chaudhari2015-07-141-47/+65
| | | | | | | | | | - If the self-cal fails, UHD waits for 2 sec for the ADC temp to stabilize and retries the self-cal
* | x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
| | | | | | | | - Characterized over process and temperature
* | x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
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* | x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
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* | x300: Bumped FPGA compat number to 11Ashish Chaudhari2015-07-071-1/+1
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* | x300: Added self-cal to tune ADC source-sync data delaysAshish Chaudhari2015-07-073-50/+160
| | | | | | | | | | | | | | - Self-calibration routine steps through various values of IDELAY taps on the SS data bits to detect metastability in the capture interface and computes an ideal delay tap value - Self calibration is triggered at device creation
* | x300: Added self-cal to tune ADC clk delay at startupAshish Chaudhari2015-07-013-33/+239
| | | | | | | | | | | | | | | | - Self-calibration routine steps through various values of LMK delay to detect metastability in the SSCLK -> radio_clk crossing and computes an ideal delay for the ADC clock. - Self calibration is triggered at startup if the self_cal_adc_delay device arg is specified
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