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* b2xx,e3xx,x300: Bumped FPGA compat numbers after SW time-sync changesAshish Chaudhari2015-12-101-1/+1
* Bumped FPGA compat numbers for B200, X300, and E300.michael-west2015-12-101-1/+1
* E300/X300: Add VITA time synchronization on internal signalmichael-west2015-12-103-2/+13
* b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-031-1/+1
* cores: Corrected scaling_adjustment calculationIan Buckley2015-09-032-0/+10
* X300: Fix base address for FP GPIOmichael-west2015-09-011-1/+1
* x300: Removed call to is_pps_presentAshish Chaudhari2015-08-171-4/+4
* b200,e300,x300: Updated compat number for release 3.9.0Ashish Chaudhari2015-08-141-1/+1
* uhd: Fixes to build with MSVCAshish Chaudhari2015-08-131-1/+1
* B200/X300: Make default clock and time sources internalmichael-west2015-08-121-14/+0
* UHD: Remove initialization of time to GPS time.michael-west2015-08-121-4/+1
* Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-121-1/+1
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| * cmake: added variable to LIBUHD_REGISTER_COMPONENT macro to make required, se...Nicholas Corgan2015-08-111-1/+1
* | Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-104-58/+80
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| * x300: added missing included necessary in Boost 1.46Nicholas Corgan2015-08-101-0/+1
| * x300, e300: Moved common register names to radio namespaceMartin Braun2015-08-074-48/+55
| * image_loader: force user to specify deviceNicholas Corgan2015-08-051-9/+23
| * x300: nirio: Fix compiler warningsMoritz Fischer2015-07-311-1/+1
* | x300: Used new soft register API for X300 registersAshish Chaudhari2015-08-044-176/+196
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* x300: Moved all tick set subscribers to same placeMartin Braun2015-07-291-10/+7
* cores: Moved subtree populate code to DSP cores (X3x0, E310)Martin Braun2015-07-291-36/+26
* cores: Moved subtree populate code to frontend coresMartin Braun2015-07-291-20/+8
* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
* x300: Removed radio_rst assertion codeAshish Chaudhari2015-07-233-3/+4
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
* x300: Moved system-level ADC and DAC operationsAshish Chaudhari2015-07-233-386/+413
* x300: Increased the max image size for burnerAshish Chaudhari2015-07-231-1/+1
* x300: Updated CLK->DATA delay for ADCAshish Chaudhari2015-07-221-2/+2
* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-224-32/+68
* x300: Minor: Optimized ADC/DAC resetsAshish Chaudhari2015-07-221-11/+11
* x300: Changed ADC clock swing to 1.6V from 0.7VAshish Chaudhari2015-07-221-2/+2
* x300: Addressed code review feedback for Rev7+ supportAshish Chaudhari2015-07-203-118/+126
* x300: Added extended ADC self-testAshish Chaudhari2015-07-192-9/+68
* x300: Made all X300 revision related errors fatalAshish Chaudhari2015-07-191-13/+20
* x300: Added HW rev compat number supportAshish Chaudhari2015-07-182-12/+27
* x300: Added new Rev7+ X3x0 MB product codesAshish Chaudhari2015-07-182-2/+54
* x300: Bumped max HW rev to 8Martin Braun2015-07-161-1/+1
* Added uhd::image_loader class and uhd_image_loader utilityNicholas Corgan2015-07-156-8/+538
* Merge branch 'maint'Martin Braun2015-07-141-1/+0
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| * x300: Removed stray debug printMartin Braun2015-07-141-1/+0
* | Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-141-1/+1
* | Merge branch 'maint'Martin Braun2015-07-142-0/+11
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| * x300: Added max hw rev checkingMartin Braun2015-07-142-0/+11
* | x300: Added retry mechanism to ADC capture delay self-calAshish Chaudhari2015-07-141-47/+65
* | x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
* | x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
* | x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
* | x300: Bumped FPGA compat number to 11Ashish Chaudhari2015-07-071-1/+1
* | x300: Added self-cal to tune ADC source-sync data delaysAshish Chaudhari2015-07-073-50/+160
* | x300: Added self-cal to tune ADC clk delay at startupAshish Chaudhari2015-07-013-33/+239
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