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path: root/host/lib/usrp/x300/x300_clock_ctrl.cpp
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* uhd: Harmonize fuzzy frequency comparisonsMartin Braun2022-02-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Throughout UHD, we often do floating-point comparisons for frequency ranges that require resilience to floating point rounding errors. Most of the time the checks look like this: ```cpp if (fp_compare_epsilon<double>(freq) > boundary) { // ... } ``` The exception is the N320 daughterboard control, which uses a custom epsilon: ```cpp if (fp_compare_epsilon<double>(freq, RHODIUM_FREQ_COMPARE_EPSILON) > boundary) { // ... } ``` This was, for the most part, not by design, but because authors simply didn't think about which epsilon value was appropriate for the frequency comparison. This was complicated by the fact that fp_compare_epsilon previously had some issues. This patch introduces FREQ_COMPARE_EPSILON, which is a sensible default value for fp_compare_epsilon when doing frequency comparisons (note that fp_compare_delta already had such a value). Also, it introduces freq_compare_epsilon(x), which is a shorthand for fp_compare_epsilon<double>(x, FREQ_COMPARE_EPSILON). We then replace all occurrences of fp_compare_epsilon<double> which are specific to frequency checks with freq_compare_epsilon.
* x300: clang-formatMartin Braun2022-01-111-6/+6
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* X300: Fix error message for wrong reference frequencyMartin Anderseck2021-09-161-1/+2
| | | | | Error message was not adapted when support for 11.52 MHz and 23.04 MHz references was added. Fixing this.
* uhd: Remove all occurences of boost::math::*round()Martin Braun2021-06-241-5/+4
| | | | | | | Its behaviour is almost identical to std::lround, which we use instead. The only downside of std::lround is that it always returns a long, which we don't always need. We thus add some casts for those cases to make the compiler happy.
* X300: Reduce phase noise for 184.32 MHz MCRmichael-west2021-04-161-2/+5
| | | | | | | Reverts charge pump current changes for 10 MHz reference / 184.32 MHz master clock rate case that caused additional phase noise. Signed-off-by: michael-west <michael.west@ettus.com>
* host: Update code base using clang-tidyMartin Braun2021-03-171-13/+14
| | | | | | | | | | | | The checks from the new clang-tidy file are applied to the source tree using: $ find . -name "*.cpp" | sort -u | xargs \ --max-procs 8 --max-args 1 clang-tidy --format-style=file \ --fix -p /path/to/compile_commands.json Note: This is the same procedure as 107a49c0, but applied to all the new code since then.
* x300: Change PLL CP currents in x300_clock_ctrlmguyler-ni2019-02-281-8/+8
| | | | | - modify PLL charge pump values to improve phase coherence - affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
* uhd: mpm: apply clang-format to all filesBrent Stapleton2019-01-161-419/+521
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Applying formatting changes to all .cpp and .hpp files in the following directories: ``` find host/examples/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/tests/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find host/utils/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file find mpm/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file ``` Also formatted host/include/, except Cpp03 was used as a the language standard instead of Cpp11. ``` sed -i 's/ Cpp11/ Cpp03/g' .clang-format find host/include/ -iname *.hpp -o -iname *.cpp | \ xargs clang-format -i -style=file ``` Formatting style was designated by the .clang-format file.
* x300: Fix compiler warnings related to type conversionsMartin Braun2019-01-071-10/+10
| | | | | | | These compiler warnings mostly pop up on MSVC. Most of them are due to inconsistent usage of size_t, uint{8,16,32}_t, and even int. This commit changes types mostly such that variables have the correct type to begin with, although it also contains a few explicit type-casts.
* x300: New mode to configure master clock rateScott Torborg2018-11-161-2/+95
| | | | | | | | Add a new clocking mode to automatically configure arbitrary master clock rates. Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com>
* X300: Add support for 11.52 MHz and 23.04 MHz referencesMichael West2018-07-171-12/+82
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* uhd: Update license headersMartin Braun2018-02-191-1/+2
| | | | | | | All copyright is now attributed to "Ettus Research, a National Instruments company". SPDX headers were also updated to latest version 3.0.
* Move all license headers to SPDX format.Martin Braun2017-12-221-12/+1
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* utils: introduce new logging API and remove msg APIAndrej Rode2017-02-201-3/+2
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* Remove all boost:: namespace prefix for uint32_t, int32_t etc. (fixed-width ↵Martin Braun2016-11-081-21/+21
| | | | | | | | types) - Also removes all references to boost/cstdint.hpp and replaces it with stdint.h (The 'correct' replacement would be <cstdint>, but not all of our compilers support that).
* UBX: Phase synchronizationmichael-west2016-02-181-3/+6
| | | | | | | - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock
* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
| | | | - Delays changed after ADC config change and FPGA fixes
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
| | | | This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
* x300: Changed ADC clock swing to 1.6V from 0.7VAshish Chaudhari2015-07-221-2/+2
| | | | - This changed with the ADS62P44 -> ADS62P48 design change
* x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
| | | | - Characterized over process and temperature
* x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
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* x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
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* x300: Added set/get_clock_delay to x300_clock_ctrlAshish Chaudhari2015-07-011-16/+227
| | | | | | | - This function allows delaying divider pairs using the digital and analog delay blocks in the LMK divider - ctrl object caches delay for later retrieval - Minor fixes to LMK regmap
* Merge branch 'maint'Martin Braun2015-06-091-16/+28
|\ | | | | | | | | | | | | Conflicts: host/lib/usrp/common/ad9361_ctrl.hpp host/lib/usrp/common/ad9361_driver/ad9361_device.h host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
| * x300: Updated clock rate / ref freq warnings for clarityMartin Braun2015-05-221-16/+28
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* | Merge branch 'master' into vivadoAshish Chaudhari2015-04-211-330/+437
|\| | | | | | | | | Conflicts: host/lib/usrp/x300/x300_clock_ctrl.cpp
| * X300: Change dboard clock rate to 50 MHzmichael-west2015-04-101-325/+432
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* | Merge branch 'master' into vivadoAshish Chaudhari2015-04-091-1/+1
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| * x300: Fix for Bug #714: Phase wobble across four channels on two devicesNeel Pandeya2015-03-301-1/+1
| | | | | | | | - Increased filter loop bandwith on clock control chip
* | x300: Timing changes for the new DAC data interfaceAshish Chaudhari2015-03-121-1/+6
|/ | | | | | | | | - Switched DAC to DCI delay bypass mode because we shift the DCI in the FPGA now - Changed LMK control to add 900ps delay to DAC clocks to be consistent with the radio_clk delay. The timing analyzer is expecting the two clocks to have a 0 deg phase diff.
* x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-061-1/+0
| | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* Merge branch 'maint'Martin Braun2014-09-251-5/+0
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| * x300: Reverted back to no analog delay for DAC ref clocksmichael-west2014-09-251-5/+0
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* | Merge branch 'maint'Martin Braun2014-09-241-0/+1
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| * x300: Added output sync for DAC reference clocksMartin Braun2014-09-241-0/+1
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* | Added missing pure virtual destructors to base classesNicholas Corgan2014-09-011-0/+4
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* Changed analog delay on DAC reference and radio clocks from 1075ps to 900psmichael-west2014-08-181-4/+4
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* - Fixes for channel alignmentmichael-west2014-08-181-0/+11
| | | | | | | | | | - Added analog delay for radio clock - Added analog delay for DAC reference clocks - Removed resetting of clock control - Removed setting of reference clock and PPS to external sources during initialization - Fixes for set_time_unknown_pps - Removed wait for PPS edge after setting time from GPSDO - Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
* Addressed comments from review.michael-west2014-03-151-1/+1
| | | | | | - Fixed typos. - Renamed reset() to reset_clocks(). - Created wait_for_ref_locked() function.
* Fixed bug found during testing where internal clock reference was taking ↵Michael West2014-02-201-0/+4
| | | | | | several seconds to lock. Added reset to the clock control and called it whenever the clock reference is changed.
* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-141-2/+4
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* Merging USRP X300 and X310 support!!Ben Hilburn2014-02-041-0/+396
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