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authorAshish Chaudhari <ashish@ettus.com>2015-04-09 09:47:55 -0700
committerAshish Chaudhari <ashish@ettus.com>2015-04-09 09:47:55 -0700
commit625724d7f81c214e9955334860a364802be3fda9 (patch)
tree39d6d0087646ef4028bc6a57d33c89a28112fed8 /host/lib/usrp/x300/x300_clock_ctrl.cpp
parent700bf99bdc483fdcc9deb54abc29bd7f81e16089 (diff)
parent3f0b770ab14aa0acaf4846680e3ee7379a1f93d7 (diff)
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Merge branch 'master' into vivado
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
-rw-r--r--host/lib/usrp/x300/x300_clock_ctrl.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp
index 22eba3eb3..3aebfea68 100644
--- a/host/lib/usrp/x300/x300_clock_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp
@@ -190,7 +190,7 @@ void set_master_clock_rate(double clock_rate) {
// PLL1 - 2 MHz compare frequency
_lmk04816_regs.PLL1_N_28 = 100;
_lmk04816_regs.PLL1_R_27 = 5;
- _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA;
+ _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA;
// PLL2 - 96 MHz compare frequency
_lmk04816_regs.PLL2_N_30 = 5;