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| author | michael-west <michael.west@ettus.com> | 2014-08-08 17:40:54 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-08-18 22:52:53 +0200 |
| commit | 8055ac0d4f10c8c13709d49fedcc66615e472a79 (patch) | |
| tree | 0e47c9967061e45f22630c5e8e4e8ab7288be317 /host/lib/usrp/x300/x300_clock_ctrl.cpp | |
| parent | 7297ebffc344cce30f2570b1587beae94adeed1e (diff) | |
| download | uhd-8055ac0d4f10c8c13709d49fedcc66615e472a79.tar.gz uhd-8055ac0d4f10c8c13709d49fedcc66615e472a79.tar.bz2 uhd-8055ac0d4f10c8c13709d49fedcc66615e472a79.zip | |
- Fixes for channel alignment
- Added analog delay for radio clock
- Added analog delay for DAC reference clocks
- Removed resetting of clock control
- Removed setting of reference clock and PPS to external sources during initialization
- Fixes for set_time_unknown_pps
- Removed wait for PPS edge after setting time from GPSDO
- Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a8b30a0ab..daae5df9b 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -283,6 +283,7 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout0_1_PD = lmk04816_regs_t::CLKOUT0_1_PD_POWER_UP; this->write_regs(0); _lmk04816_regs.CLKout0_1_DIV = vco_div; + _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X; this->write_regs(0); // Register 1 @@ -294,6 +295,8 @@ void set_master_clock_rate(double clock_rate) { // Register 3 _lmk04816_regs.CLKout6_7_DIV = vco_div; _lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO; + _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X; + _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X; // Register 4 _lmk04816_regs.CLKout8_9_DIV = vco_div; // Register 5 @@ -305,12 +308,20 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX + // Analog delay of 1075ps (maximum) to synchronize the radio clock with the source synchronous ADC clocks. + // This delay may need to vary due to temperature. Tested and verified at room temperature only. + _lmk04816_regs.CLKout0_1_ADLY = 0x17; + // Register 7 _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX _lmk04816_regs.CLKout5_TYPE = lmk04816_regs_t::CLKOUT5_TYPE_LVPECL_700MVPP; //DB_0_TX _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC + // Analog delay of 1075ps (maximum) to synchronize the DAC reference clocks with the source synchronous DAC clocks. + // This delay may need to vary due to temperature. Tested and verified at room temperature only. + _lmk04816_regs.CLKout6_7_ADLY = 0x17; + // Register 8 _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC _lmk04816_regs.CLKout10_TYPE = lmk04816_regs_t::CLKOUT10_TYPE_LVDS; //REF_CLKOUT |