| Commit message (Collapse) | Author | Age | Files | Lines |
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types)
- Also removes all references to boost/cstdint.hpp and replaces it with
stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
compilers support that).
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- Also added a template specialization for enabling the VAS_DLY bit locations based on VAS_TEMP setting (aka retune)
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any kind of interface
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- Also added check for reading chip ID
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GCC6 doesn't like nested /* /* */ */ comments (rightly so),
and complains.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Added regmap
- Added controller class
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* Removed code referencing now-unsupported versions of Boost
* Added <stdint.h> includes where needed
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Conflicts:
host/lib/usrp/cores/gpio_core_200.cpp
host/lib/usrp/dboard/db_ubx.cpp
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- Disabled MAX2871 VCO auto selection for phase sync
- Added checks for new phase sync constraints recently published by Maxim
- Added dboard_clock_rate option for X300
- Adjusted timing of SYNC signal relative to dboard referenc clock
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- Removed adf435x_common and replaced with a real encapsulated interface
- Looks similar to the MAX287X code
- Updated all DB classes to use the new common code
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- Added desired and coerced values and accessors to property
- Added support to register desired subscribers
- set APIs don't reallocate storage for a property value
- Renamed callback method registration APIs
- Registering 2 coercers or publishers for a property will throw
- Registering a coercer and a publisher for the same property will throw
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- Improved FW/FPGA compat mismatch error messages
- Added power-cycle message to loader
- Disabled "SW too new for HW" version check
- Added retry mechanism in n230_find to allow for ARP updates
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Conflicts:
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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- Add delay after putting CODEC in loopback mode
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Lowest master clock rate is now 220 kHz. At low clock rates,
the convergence time for the DC offset and quadrature calibration
times is much larger, though.
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* Unreferenced exceptions in try-catch statements
* Incorrect function documentation
* Unlabelled unused variables
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Patch addresses issue:
#742 "tx_waveforms seems to produce unexpectedly large image"
Tx Quad Cal performance is temporally dependent with better results
when run after the AD9361 is configured for transmission than at
initialization. This gets is roughly 5-10 dB of additional quadrature
image suppression.
Even better performance can be reached when Tx Quad Cal is run
after streaming and the AD9361 is actively transmitting. Calibration
in this state, however, requires user intervention by retuning the
transmit chain by > 100 MHz. Total IQ suppression should be in the
range of 40-50+ dBFS dependent on operating frequency.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Patch addresses issue:
#872 "B200: Tx and Rx calibration share same frequency state"
ADI specifies recalibration for certain paths when the LO shifts by
more than 100 MHz. Tx and Rx maintain independent LO frequencies so
use separate values for determining whether to perform re-calibration
at tuning intervals.
Also, maintain last calibration frequencies from initialization and
clock rate changes. Doing so prevents a re-calibration if the first
requested Tx or Rx frequency is close to the default values of
850 and 800 MHz respectively.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Addressed and related issues:
#186 "B200: Catalina RX signal distortion"
#821 "Incorrect behavior with auto DC Offset correction turnned off"
#820 "Rx DC Offset Correction Convergence on B2xx Dependent on Master Clock Rate"
#755 "Demodulate IQ signal amplitude oscillation on B210 at 200 MHz carrier"
Due to recent change "ad9361: Invert phase on Rx LNA bypass path", we
now have uniform phase alignment across the entire gain range. This
drastically improves performance of RF DC tracking - not to be confused
with the - active and input dependent - baseband (BB) DC tracking loop.
RF DC tracking is not affected by input signals and updates during gain
changes. The updated configuration provides improved DC suppression for
operation whether BB tracking loop is enabled or disabled.
New behavior differs from the previous case where disabling BB tracking
would clear all - static and active - calibration tables. Now, static
correction tables are not wiped when BB tracking is turned off.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Patch provides an alternative resolution to issue #807
"B210: severe distortion on In-phase data for some gain settings"
Rx quadrature tracking, an active input-sensitive loop, causes problems
on a handful of receive signals. Problematic signals include pulsed GMSK
and near-DC tones among others.
As an alternative, improve operation when active tracking is disabled.
Run single shot quadrature calibration at the following events to provide
calibrated image suppression. The corrections without active tracking are
not input dependent.
Rx quadrature single shot calibration points:
1. AD9361 initialization
2. Clock rate change
3. Tuning differences greater then 100 MHz when tracking is disabled
Note that if tracking is enabled (default case), this patch has no effect
during streaming. Only the non-default (user set) case is affected.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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- Created AD936x manager class
- Moved functionality from B2x0 and E310 into manager
- Separated property tree + perifs initialization in both device classes
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Fixes issue #828 "B200: Tx quadrature calibration regression in master"
Following commit added new gain table settings to reflect updated values
from ADI. Gain indices used by Tx Quad Cal were not matched to
accommodate the new tables.
2b06c38 "b2xx: dc offset and iq imbalance correction control"
Requirement for Tx Quad Cal is for TIA gain and analog LPF gain to be
set at 0 dB, or 0x20 in the gain table. Final effect is a dramatic
decrease in Tx DC offset and quadrature image.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Patch fixes a portion of #807
"B210: severe distortion on In-phase data for some gain settings"
ADI recommends that the "Prevent Pos Loop Gain" setting be enabled to
prevent the Rx quadrature tracking loop from becoming unstable at low
power levels. ADI Linux kernel driver also reflects this setting.
We do not follow the ADI recommendation. Adjust accordingly.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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This patch resolves issue #823
"B200: Receive RF DC calibration makes calibration worse below 34 dB"
According to ADI reference documents, enabling any of the 3 LNA's in the
receive path causes a 180 degree phase shift. Correspondingly, we invert
the LNA bypass path (gain indices below 34 dB) to match. Testing,
however, reveals that one of these statements or the polarity inversion
setting itself is false. Disabling the switch results in expected
behavior and proper phase alignment.
Overall effect is up to 60 dB of DC offset suppression ahead of the Rx
analog LPF. This reduces the problematic dependency on active baseband
tracking and may resolves multiple tracking stability issues.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
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When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
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Conflicts:
host/CMakeLists.txt
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Conflicts:
host/lib/usrp/b200/b200_io_impl.cpp
host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
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