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authorIan Buckley <ian.buckley@gmail.com>2015-05-26 15:35:04 -0700
committerIan Buckley <ianb@ionconcepts.com>2015-07-08 11:51:25 -0700
commit69bcfba936e49c2825a6d9be677c3150a5c6b70c (patch)
treeeba7afc1762bf1f3e6a23d3d81092560625cfb4b /host/lib/usrp/common
parent22fedfc3a656eca181f8bba6ffcec680e6c300e4 (diff)
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B200: New AD9361 I/O timing programming to work with new b200_io.v logic design.
Diffstat (limited to 'host/lib/usrp/common')
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index e63460730..db5de52d0 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -1455,13 +1455,13 @@ void ad9361_device_t::initialize()
* Force TX on one port, RX on the other. */
switch (_client_params->get_digital_interface_mode()) {
case AD9361_DDR_FDD_LVCMOS: {
- _io_iface->poke8(0x010, 0xc8);
+ _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode
_io_iface->poke8(0x011, 0x00);
_io_iface->poke8(0x012, 0x02);
} break;
case AD9361_DDR_FDD_LVDS: {
- _io_iface->poke8(0x010, 0xcc);
+ _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 2R2T timing.
_io_iface->poke8(0x011, 0x00);
_io_iface->poke8(0x012, 0x10);