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Implementation uses SSSE3 intructions to perform 12-bit
sample pack/unpack operations to/from standard 16 and 32
bit host values. Input/output shuffle orderings for a
single 128-bit SSE register with 16-bit integers shown
below.
16-bit interleaved I/Q
---------------------------------------
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 | Input
---------------------------------------
| 127 0 |
12-bit packed I/Q byteswapped
-----------------------
| I0 | Q0 | I1 | 0
|-----------------------|
| I1 | Q1 | I2 | Q2 | Output
|-----------------------|
| Q2 | I3 | Q3 |
|-----------------------|
| Unused | 3
-----------------------
31 0
Fixes: #1740, #966
Related: #1739
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