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* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-088-16/+8
* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-306-5/+24
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-085-0/+546
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-171-2/+5
* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10205-0/+299634
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
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