fpga: tools: Add UHD_FPGA_DIR definition to synthesis

This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:

`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"

Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:

`define RFNOC_CHDR_UTILS_PATH \
  `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH

3 files changed, 11 insertions, 6 deletions

diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak
index 74f1ef034..3ca44b01b 100644
--- a/fpga/usrp3/tools/make/viv_design_builder.mak
+++ b/fpga/usrp3/tools/make/viv_design_builder.mak
@@ -25,7 +25,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
-	export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \
+	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
 
@@ -50,7 +50,7 @@ CHECK_VIVADO_DESIGN = \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
-	export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \
+	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
 
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak
index 64af051a1..c49c05cba 100644
--- a/fpga/usrp3/tools/make/viv_simulator.mak
+++ b/fpga/usrp3/tools/make/viv_simulator.mak
@@ -52,6 +52,7 @@ SETUP_AND_LAUNCH_SIMULATION = \
 	export VIV_SIM_USER_DO=$(MODELSIM_USER_DO); \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_SIM_64BIT=$(MODELSIM_64BIT); \
+	export VIV_VERILOG_DEFS="UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	$(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal
 
 # -------------------------------------------------------------------
@@ -65,8 +66,8 @@ SETUP_AND_LAUNCH_VLINT = \
 	export VLINT_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \
 	export VLINT_SIM_SRCS=$(EXP_SIM_SRCS); \
 	export VLINT_INC_SRCS=$(EXP_INC_SRCS); \
-	export VLINT_SVLOG_ARGS="$(SVLOG_ARGS)"; \
-	export VLINT_VLOG_ARGS="$(VLOG_ARGS)"; \
+	export VLINT_SVLOG_ARGS="$(SVLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
+	export VLINT_VLOG_ARGS="$(VLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	export VLINT_VHDL_ARGS="$(VHDL_ARGS)"; \
 	export VLINT_MODELSIM_INI="$(MODELSIM_INI)"; \
 	$(TOOLS_DIR)/scripts/launch_vlint.sh
diff --git a/fpga/usrp3/tools/scripts/viv_sim_project.tcl b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
index 922c1edcc..3e7cb429b 100644
--- a/fpga/usrp3/tools/scripts/viv_sim_project.tcl
+++ b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
@@ -14,6 +14,7 @@ set part_name       $::env(VIV_PART_NAME)
 set sim_runtime     $::env(VIV_SIM_RUNTIME)
 set sim_fast        $::env(VIV_SIM_FAST)
 set vivado_mode     $::env(VIV_MODE)
+set verilog_defs    $::env(VIV_VERILOG_DEFS)
 set working_dir     [pwd]
 
 set sim_fileset "sim_1"
@@ -104,11 +105,14 @@ set_property target_simulator $simulator [current_project]
 
 # Vivado quirk when passing options to external simulators
 if [expr [string equal $simulator "XSim"] == 1] {
-    set_property verilog_define "WORKING_DIR=\"$working_dir\"" [get_filesets $sim_fileset]
+    append verilog_defs " WORKING_DIR=\"$working_dir\""
 } else {
-    set_property verilog_define "WORKING_DIR=$working_dir" [get_filesets $sim_fileset]
+    append verilog_defs " WORKING_DIR=$working_dir"
 }
 
+# Pass Verilog definitions to simulation for all files
+set_property verilog_define $verilog_defs [get_filesets $sim_fileset]
+
 # XSim specific settings
 set_property xsim.simulate.runtime "${sim_runtime}us" -objects [get_filesets $sim_fileset]
 set_property xsim.elaborate.debug_level "all" -objects [get_filesets $sim_fileset]