aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/tools/make
Commit message (Collapse)AuthorAgeFilesLines
* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-082-4/+5
| | | | | | | | | | | | | | | | | This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-5/+4
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-081-0/+2
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
|
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-171-0/+2
| | | | | | | | | | | This adds the MSIM_VIV_COMPLIBDIR environment variable to specify a non-default location for the compilation libraries. This also allows a modelsim.ini other than the one in the ModelSim installation folder to be used. By default, the one in the simulation libraries compilation directory will be used. This can be changed by setting MSIM_MODELSIM_INI to the one you want to use, or set it to an empty string to use the one in the ModelSim installation folder.
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-171-2/+5
| | | | | Allow building of just the IP by running "make ip" in simulation directories.
* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-031-0/+33
| | | | | | This adds the ability to call BUILD_VIVADO_IP, as before, followed by REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and then rebuild the IP with the patched file.
* fpga: Remove Python2 support from build systemMartin Braun2021-01-043-7/+7
| | | | | | | - 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview()
* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
|
* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
| | | | | | | During recreation of block diagrams any RTL modules will be kept in hidden directories within the build directory. Updates of the RTL sources might not be taken into account. Solution is to remove Xilinx's hidden project directories before calling vivado.
* fpga: tools: Allow multiple top modules with ModelSimWade Fife2020-06-111-1/+1
|
* fpga: tools: Improve native ModelSim supportWade Fife2020-05-261-72/+38
| | | | | This adds support for colored output and support for directories added to the list of source files (for HLS support).
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-261-1/+1
| | | | | | | | For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process.
* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-121-3/+4
|
* fpga: tools: Add -voptargs=+acc to ModelSim GUIWade Fife2020-04-141-1/+1
| | | | | | Add -voptargs=+acc to the default options when running vsim. This option enables debug command access to objects in the design, which is generally needed for debugging in the GUI.
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
|
* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-202-19/+106
| | | | | | | | | | | | | | | This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-286-0/+418
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 04:50:12 +0000