| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | fpga: lib: Fix comments and indentation in axi_fifo_short.v | Wade Fife | 2020-08-04 | 1 | -98/+87 |
| * | fpga: lib: Add xge features for new xport_sv | Andrew Moch | 2020-07-31 | 1 | -100/+191 |
| * | fpga: lib: Update AxiLiteIf | Andrew Moch | 2020-07-31 | 1 | -1/+74 |
| * | fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64 | Andrew Moch | 2020-07-30 | 1 | -1/+1 |
| * | fpga: rfnoc: Add Signal Generator RFNoC block | Wade Fife | 2020-07-30 | 12 | -18/+1925 |
| * | fpga: lib: Add axis_packetize module | Wade Fife | 2020-07-30 | 2 | -0/+162 |
| * | fpga: Add Switchboard RFNoC block | Jesse Zhang | 2020-07-30 | 7 | -0/+1121 |
| * | TwinRX: Fix increased noise floor | michael-west | 2020-07-21 | 1 | -1/+1 |
| * | fpga: remove liberio | RobertWalstab | 2020-07-20 | 3 | -126/+2 |
| * | fpga: rfnoc: Fix testbenches to run under ModelSim | Wade Fife | 2020-07-20 | 8 | -86/+64 |
| * | fpga: rfnoc: Add RFNoC Moving Average block | Wade Fife | 2020-07-16 | 8 | -0/+1587 |
| * | fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax | Max Köhler | 2020-07-10 | 1 | -39/+41 |
| * | fpga: lib: Add width agnostic version of Ethernet Interface | Andrew Moch | 2020-06-30 | 13 | -0/+3339 |
| * | fpga: rfnoc: Add Log-Power block | Wade Fife | 2020-06-29 | 6 | -0/+1006 |
| * | fpga: rfnoc: Fix chdr_update_length function | Wade Fife | 2020-06-29 | 1 | -1/+1 |
| * | fpga: rfnoc: Add RFNoC Window block | Wade Fife | 2020-06-29 | 8 | -0/+1454 |
| * | fpga: lib: Fix axi_packet_gate RAM dib width | Wade Fife | 2020-06-29 | 1 | -1/+1 |
| * | fpga: lib: Add features to axi_lite.vh | Andrew Moch | 2020-06-26 | 1 | -23/+62 |
| * | fpga: lib: Add synthesizable AXI4-Stream SV components | Andrew Moch | 2020-06-25 | 15 | -0/+3201 |
| * | fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb | Wade Fife | 2020-06-25 | 1 | -8/+16 |
| * | fpga: lib: Add interface and model for AXI4-Lite | Andrew Moch | 2020-06-24 | 4 | -0/+349 |
| * | fpga: lib: Pipeline and add clken to ip_hdr_checksum | Andrew Moch | 2020-06-24 | 4 | -66/+51 |
| * | fpga: rfnoc: Add support for 512-bit CHDR widths | Andrew Moch | 2020-06-18 | 16 | -220/+358 |
| * | fpga: lib: add extended spi core for 64bit | Max Köhler | 2020-06-17 | 2 | -0/+287 |
| * | fpga: lib: extend wb_spi ability to limit transmission length | Max Köhler | 2020-06-04 | 1 | -3/+9 |
| * | fpga: lib: Fix writes in axil_regport_master | Andrew Moch | 2020-06-04 | 1 | -23/+43 |
| * | fpga: rfnoc: Add defaults for rate changing | Wade Fife | 2020-05-28 | 2 | -10/+14 |
| * | fpga: rfnoc: Add RFNoC Add/Sub block | Wade Fife | 2020-05-28 | 7 | -10/+1190 |
| * | rfnoc: Add Split Stream RFNoC block | Wade Fife | 2020-05-28 | 6 | -0/+932 |
| * | fpga: rfnoc: Add Vector IIR RFNoC block | Wade Fife | 2020-05-19 | 8 | -20/+1394 |
| * | fpga: rfnoc: Clean up ctrlport_splitter usage | Wade Fife | 2020-05-12 | 2 | -2/+2 |
| * | fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1 | Wade Fife | 2020-05-12 | 1 | -45/+61 |
| * | TwinRX: Remove decimation from frontend | Michael West | 2020-05-12 | 1 | -36/+52 |
| * | DUC/DDC: Add variable time increment | Michael West | 2020-05-12 | 5 | -19/+39 |
| * | fpga: Change default MTU to 10 | Wade Fife | 2020-05-11 | 5 | -5/+5 |
| * | rfnoc: Add RFNoC fosphor block | Wade Fife | 2020-04-14 | 7 | -1/+1585 |
| * | fpga: rfnoc: Add option to sample sideband info at start of packet | Wade Fife | 2020-04-14 | 1 | -58/+117 |
| * | fpga: core: Add chdr_update_length function | Wade Fife | 2020-04-14 | 1 | -0/+21 |
| * | fpga: lib: Add AXI-Stream splitter (axis_split) | Wade Fife | 2020-04-14 | 2 | -0/+129 |
| * | fpga: rfnoc: Add gate to dynamically enable control-port interfaces | Max Köhler | 2020-04-01 | 1 | -0/+91 |
| * | fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 | Max Köhler | 2020-04-01 | 1 | -13/+51 |
| * | fpga: Fix errors found by linting with vsim | Andrew Moch | 2020-03-23 | 6 | -19/+22 |
| * | sim: Add item support to RFNoC simulation | Wade Fife | 2020-03-09 | 6 | -6/+6 |
| * | sim: Parameterize chdr_word_t data type | Wade Fife | 2020-03-09 | 8 | -8/+30 |
| * | fpga: lib: Modify for loop to Verilog 2001 syntax | Max Köhler | 2020-03-09 | 1 | -34/+35 |
| * | rfnoc: Fix FIR and AXI RAM block register documentation | Wade Fife | 2020-03-05 | 2 | -9/+11 |
| * | rfnoc: Add management filter to generic xport | Wade Fife | 2020-02-19 | 3 | -71/+138 |
| * | radio: Update TB to use new block ctrl connect | Wade Fife | 2020-02-19 | 1 | -41/+17 |
| * | rfnoc: Update blocks to use autogenerated noc_shell | Wade Fife | 2020-02-06 | 23 | -1825/+2407 |
| * | fixup! lib: add option for output register in pps generator | Humberto Jimenez | 2020-02-05 | 1 | -1/+1 |
