sim: Parameterize chdr_word_t data type

This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:

  // Define the CHDR word and item/sample data types
  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;

ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:

  // Convert CHDR data buffer to a buffer of samples
  samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);

8 files changed, 30 insertions, 8 deletions

diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
index 8ae72027e..e4753e92f 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
@@ -83,6 +83,8 @@ module rfnoc_block_axi_ram_fifo_tb #(
   // Bus Functional Models
   //---------------------------------------------------------------------------
 
+  typedef ChdrData #(CHDR_W)::chdr_word_t chdr_word_t;
+
   RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
   AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
   AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv
index 86f64ab4c..e6f2c4d6b 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv
@@ -35,6 +35,7 @@ module rfnoc_block_ddc_tb();
 
   // Block configuration
   localparam int CHDR_W        = 64;
+  localparam int SAMP_W        = 32;
   localparam int THIS_PORTID   = 'h123;
   localparam int MTU           = 8;
   localparam int NUM_PORTS     = 1;
@@ -60,6 +61,8 @@ module rfnoc_block_ddc_tb();
   // Bus Functional Models
   //---------------------------------------------------------------------------
 
+  typedef ChdrData #(CHDR_W, SAMP_W)::chdr_word_t chdr_word_t;
+
   RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
   AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
   AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv
index de54d5ee0..8151ed761 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv
@@ -35,6 +35,7 @@ module rfnoc_block_duc_tb();
 
   // Block configuration
   localparam int CHDR_W         = 64;
+  localparam int SAMP_W         = 32;
   localparam int THIS_PORTID    = 'h123;
   localparam int MTU            = 8;
   localparam int NUM_PORTS      = 1;
@@ -49,6 +50,7 @@ module rfnoc_block_duc_tb();
 
   bit rfnoc_chdr_clk;
   bit rfnoc_ctrl_clk;
+  bit ce_clk;
 
   sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
   sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
@@ -59,6 +61,8 @@ module rfnoc_block_duc_tb();
   // Bus Functional Models
   //---------------------------------------------------------------------------
 
+  typedef ChdrData #(CHDR_W, SAMP_W)::chdr_word_t chdr_word_t;
+
   RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
   AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
   AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv
index 05b38ddeb..412963dc7 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv
@@ -30,6 +30,7 @@ module rfnoc_block_fft_tb();
   // Block configuration
   localparam int NOC_ID        = 32'hFF70_0000;
   localparam int CHDR_W        = 64;
+  localparam int SAMP_W        = 32;
   localparam int THIS_PORTID   = 'h123;
   localparam int MTU           = 10;
   localparam int NUM_PORTS     = 1;
@@ -60,6 +61,8 @@ module rfnoc_block_fft_tb();
   // Bus Functional Models
   //---------------------------------------------------------------------------
 
+  typedef ChdrData #(CHDR_W, SAMP_W)::chdr_word_t chdr_word_t;
+
   RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
   AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
   AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv
index 2a961b89f..fedb4f46b 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv
@@ -36,6 +36,7 @@ module rfnoc_block_fir_filter_tb #(
 
   // DUT parameters to test
   localparam int CHDR_W      = 64;
+  localparam int SAMP_W      = 32;
   localparam int THIS_PORTID = 'h123;
   localparam int MTU         = 8;
   //
@@ -86,6 +87,8 @@ module rfnoc_block_fir_filter_tb #(
   // Bus Functional Models
   //---------------------------------------------------------------------------
 
+  typedef ChdrData #(CHDR_W, SAMP_W)::chdr_word_t chdr_word_t;
+
   RfnocBackendIf        backend            (rfnoc_chdr_clk, rfnoc_ctrl_clk);
   AxiStreamIf #(32)     m_ctrl             (rfnoc_ctrl_clk, 1'b0);
   AxiStreamIf #(32)     s_ctrl             (rfnoc_ctrl_clk, 1'b0);
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
index 699d53b11..192a8143b 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
@@ -24,6 +24,7 @@ module rfnoc_block_null_src_sink_tb;
   localparam [9:0]  THIS_PORTID = 10'h17;
   localparam [15:0] THIS_EPID   = 16'hDEAD;
   localparam int    CHDR_W      = 64;
+  localparam int    ITEM_W      = 32;
   localparam int    SPP         = 201;
   localparam int    LPP         = ((SPP+1)/2);
   localparam int    NUM_PKTS    = 50;
@@ -48,6 +49,8 @@ module rfnoc_block_null_src_sink_tb;
   AxiStreamIf #(CHDR_W) s0_chdr (rfnoc_chdr_clk);                 // Optional data iface
   AxiStreamIf #(CHDR_W) s1_chdr (rfnoc_chdr_clk);                 // Optional data iface
 
+  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
+
   // Bus functional model for a software block controller
   RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
 
@@ -128,7 +131,7 @@ module rfnoc_block_null_src_sink_tb;
       // Read status register and validate it
       blk_ctrl.reg_read(dut.REG_CTRL_STATUS, rvalue);
       `ASSERT_ERROR(rvalue[31:24] == 2, "Incorrect NIPC Value");
-      `ASSERT_ERROR(rvalue[23:16] == 32, "Incorrect ITEM_W Value");
+      `ASSERT_ERROR(rvalue[23:16] == ITEM_W, "Incorrect ITEM_W Value");
       test.end_timeout(timeout);
     end
     test.end_test();
@@ -139,7 +142,7 @@ module rfnoc_block_null_src_sink_tb;
       repeat (NUM_PKTS) begin
         chdr_word_t rx_data[$];
         int rx_bytes;
-        automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new, rx_dbuff = new;
+        automatic ItemDataBuff #(logic[ITEM_W-1:0]) tx_dbuff = new, rx_dbuff = new;
         for (int i = 0; i < SPP; i++)
           tx_dbuff.put($urandom());
         test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
@@ -176,7 +179,7 @@ module rfnoc_block_null_src_sink_tb;
       repeat (NUM_PKTS) begin
         chdr_word_t rx_data[$];
         int rx_bytes;
-        automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new;
+        automatic ItemDataBuff #(logic[ITEM_W-1:0]) tx_dbuff = new;
         for (int i = 0; i < SPP; i++)
           tx_dbuff.put($urandom());
         test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv
index 4438cae9e..553b0e33e 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv
@@ -27,7 +27,6 @@ module rfnoc_block_radio_tb #(
   import PkgRfnocBlockCtrlBfm::*;
   import PkgAxisCtrlBfm::*;
   import PkgChdrBfm::*;
-  import PkgRfnocItemUtils::*;
 
   // Pull in radio register offsets and constants
   `include "rfnoc_block_radio_regs.vh"
@@ -87,6 +86,9 @@ module rfnoc_block_radio_tb #(
   AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
   AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0);
 
+  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
+  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      sample_t;
+
   // Bus functional model for a software block controller
   RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = new(backend, m_ctrl, s_ctrl);
 
@@ -370,13 +372,13 @@ module rfnoc_block_radio_tb #(
       for (int i = 0; i < valid_words; i++) begin
         // Check each sample of the next chdr_word_t value
         for (int sub_sample = 0; sub_sample < $bits(chdr_word_t)/ITEM_W; sub_sample++) begin
-          chdr_word_t word;
-          word = data[i][ITEM_W*sub_sample +: ITEM_W];  // Work around Vivado 2018.3 issue
+          sample_t actual;
+          actual = data[i][ITEM_W*sub_sample +: ITEM_W];  // Work around Vivado 2018.3 issue
           `ASSERT_ERROR(
-            word == sample_val,
+            actual == sample_val,
             $sformatf(
               "Sample %0d (0x%X) didn't match expected value (0x%X)",
-              sample_count, data[i][ITEM_W*sub_sample +: ITEM_W],  sample_val
+              sample_count, actual, sample_val
             )
           );
           sample_val++;
diff --git a/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
index 0626ee447..34bf10707 100644
--- a/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
+++ b/fpga/usrp3/lib/rfnoc/sim/chdr_stream_endpoint_tb/chdr_stream_endpoint_tb.sv
@@ -45,6 +45,8 @@ module chdr_stream_endpoint_tb;
   localparam [9:0]  PORT_A   = 10'd1;
   localparam [9:0]  PORT_B   = 10'd2;
 
+  typedef ChdrData #(CHDR_W)::chdr_word_t chdr_word_t;
+
   // ----------------------------------------
   // DUT (and Crossbar) Instantiations
   // ----------------------------------------