fpga: lib: Add interface and model for AXI4-Lite

(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
    and an AxiLiteBfm class.

Important Methods
  a. wr - performs non-blocking write and checks for expected response
  b. wr_block - performs a blocking write and provides response
  c. rd - performs a non-blocking read and checks for expected response
  d. rd_block - persforms a blocking read  and provides response

The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods.  When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.

4 files changed, 349 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi4lite_sv/AxiLiteIf.sv b/fpga/usrp3/lib/axi4lite_sv/AxiLiteIf.sv
new file mode 100644
index 000000000..beb095bc3
--- /dev/null
+++ b/fpga/usrp3/lib/axi4lite_sv/AxiLiteIf.sv
@@ -0,0 +1,209 @@
+//
+// Copyright 2020 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Interface: AxiLiteIf
+// Description:
+//  AXI4-LITE is an ARM standard for lighter weight registers
+//  axis based on the AXI4 protocol. For more information
+//  on the spec see - https://developer.arm.com/docs/ihi0022/d
+//
+//  The interface contains methods for
+//  (1) Writing an address
+//  (2) Reading an address
+//
+// Parameters:
+//  - DATA_WIDTH - Width of the data on AXI4-Lite bus
+//  - ADDR_WIDTH - Width of the address on AXI4-Lite bus
+//
+
+//-----------------------------------------------------------------------------
+// AXI4-Lite interface
+//-----------------------------------------------------------------------------
+
+interface AxiLiteIf #(
+  int DATA_WIDTH = 64,
+  int ADDR_WIDTH = 1
+) (
+  input logic clk,
+  input logic rst = 1'b0
+);
+
+  import PkgAxiLite::*;
+
+  localparam BYTES_PER_WORD = DATA_WIDTH/8;
+
+  // local type defs
+  typedef logic [DATA_WIDTH-1:0]     data_t;
+  typedef logic [ADDR_WIDTH-1:0]     addr_t;
+  typedef logic [BYTES_PER_WORD-1:0] strb_t;
+
+  // Signals that make up an AxiLite interface
+  // Write Address Channel
+  addr_t awaddr;
+  logic  awvalid;
+  logic  awready;
+
+  // Write Data Channel
+  data_t wdata;
+  strb_t wstrb = '1;
+  logic  wvalid;
+  logic  wready;
+
+  // Write Response Channel
+  resp_t bresp;
+  logic  bvalid;
+  logic  bready;
+
+  // Read Address Channel
+  addr_t araddr;
+  logic  arvalid;
+  logic  arready;
+
+  // Read Data Channel
+  data_t rdata;
+  resp_t rresp;
+  logic  rvalid;
+  logic  rready;
+
+  // Master Functions
+  task automatic drive_aw(input addr_t addr);
+    awaddr  = addr;
+    awvalid = 1;
+  endtask
+
+  task automatic drive_w(input data_t data,
+                         input strb_t strb = '1);
+    wdata   = data;
+    wstrb   = wstrb;
+    wvalid  = 1;
+  endtask
+
+  task automatic drive_aw_idle();
+    awaddr  = 'X;
+    awvalid = 0;
+  endtask
+
+  task automatic drive_w_idle();
+    wdata   = 'X;
+    wstrb   = 'X;
+    wvalid  = 0;
+  endtask
+  task automatic drive_read(input addr_t addr);
+    araddr  = addr;
+    arvalid = 1;
+  endtask
+
+  task automatic drive_read_idle();
+    araddr  = 'X;
+    arvalid = 0;
+  endtask
+
+  // Slave Functions
+  task automatic drive_write_resp(input resp_t resp=OKAY);
+    bresp  = resp;
+    bvalid = 1;
+  endtask
+
+  task automatic drive_write_resp_idle();
+    bresp  = OKAY;
+    bvalid = 0;
+  endtask
+
+  task automatic drive_read_resp(input data_t data,
+                                 input resp_t resp=OKAY);
+    rdata  = data;
+    rresp  = resp;
+    rvalid = 1;
+  endtask
+
+  task automatic drive_read_resp_idle();
+    rdata  = 'X;
+    rresp  = OKAY;
+    rvalid = 0;
+  endtask
+
+  // Drive Functions  (These are not particularly useful
+  // but they guarantee the modules using the package don't
+  // drive the interface with a continuous assignment)
+  task automatic drive_awaddr(input  addr_t  addr);
+    awaddr = addr;
+  endtask
+  task automatic drive_awvalid(input  logic valid);
+    awvalid = valid;
+  endtask
+  task automatic drive_awready(input  logic  ready);
+    awready = ready;
+  endtask
+  task automatic drive_wdata(input  data_t data);
+    wdata = data;
+  endtask
+  task automatic drive_wstrb(input  strb_t strb);
+    wstrb = strb;
+  endtask
+  task automatic drive_wvalid(input  logic valid);
+    wvalid = valid;
+  endtask
+  task automatic drive_wready(input  logic  ready);
+    wready = ready;
+  endtask
+
+  task automatic drive_bresp(input  resp_t resp);
+    bresp = resp;
+  endtask
+  task automatic drive_bvalid(input  logic valid);
+    bvalid = valid;
+  endtask
+  task automatic drive_bready(input  logic  ready);
+    bready = ready;
+  endtask
+
+  task automatic drive_araddr(input  addr_t  addr);
+    araddr = addr;
+  endtask
+  task automatic drive_arvalid(input  logic valid);
+    arvalid = valid;
+  endtask
+  task automatic drive_arready(input  logic  ready);
+    arready = ready;
+  endtask
+
+  task automatic drive_rdata(input  data_t data);
+    rdata = data;
+  endtask
+  task automatic drive_rresp(input  resp_t resp);
+    rresp = resp;
+  endtask
+  task automatic drive_rvalid(input  logic valid);
+    rvalid = valid;
+  endtask
+  task automatic drive_rready(input  logic  ready);
+    rready = ready;
+  endtask
+
+  // View from the master side
+  modport master (
+    input  clk, rst,
+    output awaddr,awvalid,wdata,wstrb,wvalid,bready,araddr,arvalid,rready,
+    input  awready,wready,bresp,bvalid,arready,rdata,rresp,rvalid,
+    import drive_aw,
+    import drive_w,
+    import drive_w_idle,
+    import drive_aw_idle,
+    import drive_read,
+    import drive_read_idle
+  );
+
+  // View from the slave side
+  modport slave (
+    input  clk, rst,
+    input  awaddr,awvalid,wdata,wstrb,wvalid,bready,araddr,arvalid,rready,
+    output awready,wready,bresp,bvalid,arready,rdata,rresp,rvalid,
+    import drive_write_resp,
+    import drive_write_resp_idle,
+    import drive_read_resp,
+    import drive_read_resp_idle
+  );
+
+endinterface : AxiLiteIf
diff --git a/fpga/usrp3/lib/axi4lite_sv/Makefile.srcs b/fpga/usrp3/lib/axi4lite_sv/Makefile.srcs
new file mode 100644
index 000000000..eb9239a2b
--- /dev/null
+++ b/fpga/usrp3/lib/axi4lite_sv/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2020 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+AXI4LITE_SV_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi4lite_sv/, \
+PkgAxiLite.sv \
+AxiLiteIf.sv \
+))
diff --git a/fpga/usrp3/lib/axi4lite_sv/PkgAxiLite.sv b/fpga/usrp3/lib/axi4lite_sv/PkgAxiLite.sv
new file mode 100644
index 000000000..09b15e986
--- /dev/null
+++ b/fpga/usrp3/lib/axi4lite_sv/PkgAxiLite.sv
@@ -0,0 +1,21 @@
+//
+// Copyright 2020 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Package: PkgAxiLite
+// Description:
+//   AXI4-Lite is an ARM standard for lighter weight registers
+//   axis based on the AXI4 protocol. For more information
+//   on the spec see - https://developer.arm.com/docs/ihi0022/d
+//
+//   This package contains types used for AxiLiteIf.
+//
+
+//-----------------------------------------------------------------------------
+// AXI4-Lite Package
+//-----------------------------------------------------------------------------
+
+package PkgAxiLite;
+  typedef enum logic [1:0] {OKAY=0,SLVERR=2,DECERR=3} resp_t;
+endpackage : PkgAxiLite
diff --git a/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh b/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh
new file mode 100644
index 000000000..b260a1b24
--- /dev/null
+++ b/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh
@@ -0,0 +1,106 @@
+//
+// Copyright 2020 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Header File:  axi_lite.vh
+// Description:  Macros for use with AXI4S
+//
+
+//-----------------------------------------------------------------------------
+// Unidirectional AXI4-Stream interface
+//-----------------------------------------------------------------------------
+
+// Macro that drives o from i for all fields. Of course, ready runs in the
+// counter direction.
+
+`define AXI4LITE_ASSIGN(O,I) \
+  /* write address channel */
+  ``O.awaddr  = ``I.awaddr;\
+  ``O.awvalid = ``I.awvalid;\
+  ``I.awready = ``O.awready;\
+  /* write data channel */
+  ``O.wdata   = ``I.wdata;\
+  ``O.wstrb   = ``I.wstrb;\
+  ``O.wvalid  = ``I.wvalid;\
+  ``I.wready  = ``O.wready;\
+  /* write resp channel */
+  ``I.bresp   = ``O.bresp;\
+  ``I.bvalid  = ``O.bvalid;\
+  ``O.bready  = ``I.bready;\
+  /* read address channel */
+  ``O.araddr  = ``I.araddr;\
+  ``O.arvalid = ``I.arvalid;\
+  ``I.arready = ``O.arready;\
+  /* read resp channel */
+  ``I.rdata   = ``O.rdata;\
+  ``I.rresp   = ``O.rresp;\
+  ``I.rvalid  = ``O.rvalid;\
+  ``O.rready  = ``I.rready;
+
+`define AXI4LITE_DEBUG_ASSIGN(O,I) \
+  (* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0]     ``I``_debug_awaddr;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_awvalid;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_awready;\
+  (* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0]     ``I``_debug_wdata;\
+  (* mark_debug = "true" *) logic [``I.BYTES_PER_WORD-1:0] ``I``_debug_wstrb;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_wvalid;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_wready;\
+  (* mark_debug = "true" *) logic [1:0]                    ``I``_debug_bresp;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_bvalid;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_bready;\
+  (* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0]     ``I``_debug_araddr;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_arvalid;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_arready;\
+  (* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0]     ``I``_debug_rdata;\
+  (* mark_debug = "true" *) logic [1:0]                    ``I``_debug_rresp;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_rvalid;\
+  (* mark_debug = "true" *) logic                          ``I``_debug_rready;\
+  always_comb begin\
+  /* write address channel */
+  ``I``_debug_awaddr  = ``I.awaddr;\
+  ``I``_debug_awvalid = ``I.awvalid;\
+  ``I.awready = ``I``_debug_awready;\
+  /* write data channel */
+  ``I``_debug_wdata   = ``I.wdata;\
+  ``I``_debug_wstrb   = ``I.wstrb;\
+  ``I``_debug_wvalid  = ``I.wvalid;\
+  ``I.wready  = ``I``_debug_wready;\
+  /* write resp channel */
+  ``I.bresp   = ``I``_debug_bresp;\
+  ``I.bvalid  = ``I``_debug_bvalid;\
+  ``I``_debug_bready  = ``I.bready;\
+  /* read address channel */
+  ``I``_debug_araddr  = ``I.araddr;\
+  ``I``_debug_arvalid = ``I.arvalid;\
+  ``I.arready = ``I``_debug_arready;\
+  /* read resp channel */
+  ``I.rdata   = ``I``_debug_rdata;\
+  ``I.rresp   = ``I``_debug_rresp;\
+  ``I.rvalid  = ``I``_debug_rvalid;\
+  ``I``_debug_rready  = ``I.rready;
+  end\
+  always_comb begin\
+  /* write address channel */
+  ``O.awaddr  = ``I``_debug_awaddr;\
+  ``O.awvalid = ``I``_debug_awvalid;\
+  ``I``_debug_awready = ``O.awready;\
+  /* write data channel */
+  ``O.wdata   = ``I``_debug_wdata;\
+  ``O.wstrb   = ``I``_debug_wstrb;\
+  ``O.wvalid  = ``I``_debug_wvalid;\
+  ``I``_debug_wready  = ``O.wready;\
+  /* write resp channel */
+  ``I``_debug_bresp   = ``O.bresp;\
+  ``I``_debug_bvalid  = ``O.bvalid;\
+  ``O.bready  = ``I``_debug_bready;\
+  /* read address channel */
+  ``O.araddr  = ``I``_debug_araddr;\
+  ``O.arvalid = ``I``_debug_arvalid;\
+  ``I``_debug_arready = ``O.arready;\
+  /* read resp channel */
+  ``I``_debug_rdata   = ``O.rdata;\
+  ``I``_debug_rresp   = ``O.rresp;\
+  ``I``_debug_rvalid  = ``O.rvalid;\
+  ``O.rready  = ``I``_debug_rready;
+  end
\ No newline at end of file