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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
| | | | | | - Fixed bus width from 25 to 24 bits Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: remove liberioRobertWalstab2020-07-203-126/+2
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* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-208-86/+64
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
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* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
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* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
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* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
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* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
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* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
| | | | | | Contains a fix for the AXI4LITE_ASSIGN macro, and adds AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and AXI4LITE_DEBUG_ASSIGN macros.
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2515-0/+3201
| | | | | | | | | | | | | | | | | | | Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
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* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-244-0/+349
| | | | | | | | | | | | | | | | | (1) Synthesizable AxiLiteIf (2) Simulation model for AxiLite contains an AxiLiteTransaction class and an AxiLiteBfm class. Important Methods a. wr - performs non-blocking write and checks for expected response b. wr_block - performs a blocking write and provides response c. rd - performs a non-blocking read and checks for expected response d. rd_block - persforms a blocking read and provides response The model allows parallel execution of reads and writes, but enforces rd and write ordering when using the above methods. When transactions are posted directly, ordering is not guaranteed, and reads and writes are put on the interface immediately.
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
| | | | | | | Adds LATENCY parameter to control the ammount of pieplineing. Adds a clock enable to control the advance of the pipeline. Used in xport when calculating new UDP headers for CHDR traffic.
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1816-220/+358
| | | | | | | | This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths.
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
| | | | | | | | | The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This commit adds a second spi core with capability to transfer up to 64 bits while keeping the same amount of resources when using generic setting MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the edges of sclk. The register stages were not aligned in the existing version.
* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
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* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
| | | | | | | Previously, if a write occurred before the FIFO was ready then a write could hang as the data channel would complete but leave the address channel in a state where it would never complete. The fix is to hold off acknowledging on the data channel until the FIFO is ready.
* fpga: rfnoc: Add defaults for rate changingWade Fife2020-05-282-10/+14
| | | | | | Add DEFAULT_M and DEFAULT_N parameters for rate changing cores. This allows the host to not need to configure fixed rate change cores.
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-287-10/+1190
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* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
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* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
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* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
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* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
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* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
| | | | | | | | | | | | | | The decimation in the rx_frontend_gen3 was added to reduce the bandwidth between the Radio and the DDC due to the limitation in bandwidth over the crossbar for dynamically connected blocks. The default FPGA image for the X300 now has a static connection between the Radio and DDC, so this is no longer necessary. This change allows the TwinRX receive channels to be time aligned with channels from other daughterboards so they can be used in the same streamer. Signed-off-by: Michael West <michael.west@ettus.com>
* DUC/DDC: Add variable time incrementMichael West2020-05-125-19/+39
| | | | | | | | | Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West <michael.west@ettus.com>
* fpga: Change default MTU to 10Wade Fife2020-05-115-5/+5
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* rfnoc: Add RFNoC fosphor blockWade Fife2020-04-147-1/+1585
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* fpga: rfnoc: Add option to sample sideband info at start of packetWade Fife2020-04-141-58/+117
| | | | | | | | The axis_data_to_chdr block previously only sampled the sideband information at the end of the packet. This adds a parameter that controls if the sideband information should be sampled at the beginning of the packet or the end of the packet. In the former case, large internal packet buffers are not required.
* fpga: core: Add chdr_update_length functionWade Fife2020-04-141-0/+21
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* fpga: lib: Add AXI-Stream splitter (axis_split)Wade Fife2020-04-142-0/+129
| | | | | | | The axis_split module takes a single AXI-Stream input and duplicates it onto multiple AXI-Stream outputs. This block correctly handles the somewhat tricky flow-control logic so that the AXI-Stream handshake protocol is honored at all top-level ports.
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
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* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
| | | | | The latency through the combiner is static if only one master interface is used and PRIORITY=1 is set.
* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
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* sim: Add item support to RFNoC simulationWade Fife2020-03-096-6/+6
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-098-8/+30
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
| | | | | | This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus).
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
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* rfnoc: Add management filter to generic xportWade Fife2020-02-193-71/+138
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* radio: Update TB to use new block ctrl connectWade Fife2020-02-191-41/+17
| | | | | This eliminates the complicated semaphore from the testbench and brings the radio testbench in line with the other testbenches.
* rfnoc: Update blocks to use autogenerated noc_shellWade Fife2020-02-0623-1825/+2407
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* fixup! lib: add option for output register in pps generatorHumberto Jimenez2020-02-051-1/+1
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* lib: add option for output register in pps generatorMax Köhler2020-01-281-2/+23
| | | | | | The pps_generator module receives a new parameter (PIPELINE) which can optionally add a register on the output. The default behaviour is unchanged.
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-28998-0/+583091
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
* Removed copy of FPGA source files.Martin Braun2014-10-07313-168710/+0
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* fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-246-221/+322
| | | | | | | - Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300
* fpga: Updating FPGA code for UHD-3.7.2-rc1Ben Hilburn2014-07-224-21/+52
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* fpga: updating b200 and x300 FPGA source code for latest imagesBen Hilburn2014-05-146-499/+531
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* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-14228-1027/+21529
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