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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
* fpga: remove liberioRobertWalstab2020-07-203-126/+2
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-208-86/+64
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2515-0/+3201
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-244-0/+349
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1816-220/+358
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
* fpga: rfnoc: Add defaults for rate changingWade Fife2020-05-282-10/+14
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-287-10/+1190
* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
* DUC/DDC: Add variable time incrementMichael West2020-05-125-19/+39
* fpga: Change default MTU to 10Wade Fife2020-05-115-5/+5
* rfnoc: Add RFNoC fosphor blockWade Fife2020-04-147-1/+1585
* fpga: rfnoc: Add option to sample sideband info at start of packetWade Fife2020-04-141-58/+117
* fpga: core: Add chdr_update_length functionWade Fife2020-04-141-0/+21
* fpga: lib: Add AXI-Stream splitter (axis_split)Wade Fife2020-04-142-0/+129
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
* sim: Add item support to RFNoC simulationWade Fife2020-03-096-6/+6
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-098-8/+30
* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
* rfnoc: Add management filter to generic xportWade Fife2020-02-193-71/+138
* radio: Update TB to use new block ctrl connectWade Fife2020-02-191-41/+17
* rfnoc: Update blocks to use autogenerated noc_shellWade Fife2020-02-0623-1825/+2407
* fixup! lib: add option for output register in pps generatorHumberto Jimenez2020-02-051-1/+1
* lib: add option for output register in pps generatorMax Köhler2020-01-281-2/+23
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-28998-0/+583091
* Removed copy of FPGA source files.Martin Braun2014-10-07313-168710/+0
* fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-246-221/+322
* fpga: Updating FPGA code for UHD-3.7.2-rc1Ben Hilburn2014-07-224-21/+52
* fpga: updating b200 and x300 FPGA source code for latest imagesBen Hilburn2014-05-146-499/+531
* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-14228-1027/+21529
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