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| | | * Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22641-491/+0
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| | * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
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| | * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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| | * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
| | | | | | | | | | | | | | | | workaround
| | * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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| | * | ignore emacs backup filesMatt Ettus2010-03-231-0/+1
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| | * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
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| | * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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| | * | copy in wrong placeMatt Ettus2010-03-101-60/+0
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| | * | copied over from quad radioMatt Ettus2010-02-081-0/+60
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| | * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-255-34/+103
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| | | * | speed up timing by ignoring the too_early error. We'll need to FIXME this laterMatt Ettus2010-01-191-2/+5
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| | | * | Added set time and set time at next pps. Removed the old sync pps commands, ↵Josh Blum2010-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | they dont make sense to use anymore. Replaced the mimo config with clock config. The clock config handles the pps and the reference. Modified the memory map and internal calls to reflect the fpga changes.
| | | * | moved around regs, added a bit to allow for alternate PPS sourceMatt Ettus2010-01-181-4/+10
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| | | * | remove time_sync and master_timer.Matt Ettus2010-01-183-22/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Master timer replaced with simple_timer which needs new memory map and control functions. it allows onetime and periodic interrupts. Copied from quad_radio time_sync functionality will go in time_64bit. Right now it only does external SMA connector, not mimo connector
| | | * | allow setting time immediately in cases where there is no external pps inputMatt Ettus2010-01-181-4/+5
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| | | * | allow processor to read back vrt time over readback muxMatt Ettus2010-01-181-2/+2
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| | | * | proper time sync to ppsMatt Ettus2010-01-182-5/+30
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| | * | | just debug pin changesMatt Ettus2010-01-252-1/+12
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| | * | | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
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| | * | | moved into subdirJosh Blum2010-01-22661-491/+0
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| | * | | should fix the endless packet bugMatt Ettus2010-01-181-1/+3
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| | * | | yet another typoMatt Ettus2010-01-151-1/+1
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| | * | | yet more debug linesMatt Ettus2010-01-152-4/+9
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| | * | | typoMatt Ettus2010-01-151-1/+1
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| | * | | add debug pins to find the problem with lost eof in the udp coreMatt Ettus2010-01-151-2/+2
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| | * | | try a width that works...Matt Ettus2010-01-141-1/+2
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| | * | | try proper resetMatt Ettus2010-01-141-1/+1
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| | * | | forgot to declare wireMatt Ettus2010-01-141-1/+3
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| | * | | debug stateMatt Ettus2010-01-143-5/+12
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| | * | | empty file, it is actually located in the control directoryMatt Ettus2010-01-141-0/+0
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| | * | | make it match the 36 bit wide versionMatt Ettus2010-01-142-6/+8
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| | * | | better debug pinsMatt Ettus2010-01-052-9/+9
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| | * | | more typo fixes.Matt Ettus2010-01-051-3/+3
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| | * | | typo fixMatt Ettus2010-01-051-1/+1
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| | * | | actually connect the ports -- why this isn't flagged as an error I'll never knowMatt Ettus2010-01-051-3/+8
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| | * | | place udp core in the memory spaceMatt Ettus2010-01-052-9/+12
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| | * | | Merge branch 'wip/usrp2' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-052-5/+30
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| | | * | | proper time sync to ppsMatt Ettus2009-12-222-5/+30
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| | * | | Merge branch 'udp' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-0513-49/+1073
| | |\ \ \ | | | |/ / | | |/| | | | | | | | | | | | Conflicts: usrp2/fpga/top/u2_rev3/Makefile
| | | * | never should have checked in this generated binary fileMatt Ettus2009-12-211-21251/+0
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| | | * | barebones udp support. Compiles, but untested.Matt Ettus2009-12-219-18/+538
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| | | * | 19-bit fifo handling for receive side of eth/udp systemMatt Ettus2009-12-212-45/+83
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| | | * | 19 bit wide interface in prep for connection to UDP/IP state machines.Matt Ettus2009-12-215-0/+21717
| | | |/ | | | | | | | | | | | | TX side done, not rx yet. Not tested, but it does compile.
| | * | cleaned up the main ibs state machineMatt Ettus2009-12-141-9/+22
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| | * | dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ↵Matt Ettus2009-12-143-10/+9
| | | | | | | | | | | | | | | | vrt fixed
| | * | changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
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| | * | reorder the memory mapMatt Ettus2009-12-112-2/+2
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| | * | put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
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| | * | only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
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