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| * | allow for varying the bitwidthmatt2007-03-201-1/+2
| | | | | | | | | | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4781 221aa14e-8319-0410-a670-987f0aec2ac5
| * | added commentmatt2007-03-201-1/+3
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| * | added comments, removed dead codematt2007-03-201-10/+6
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| * | Refactored FPGA *.vh files. Moved common pieces to toplevel/include.eb2007-03-0519-351/+145
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| * | Add new standard configuration for 1 RX w/ half-band, 1 TXeb2007-03-033-1/+75
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| * | updated qsf file to Quartus 6.1. No semantic changeseb2007-03-031-11/+11
| | | | | | | | | | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4694 221aa14e-8319-0410-a670-987f0aec2ac5
| * | fixed commenteb2007-02-261-1/+1
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| * | fixed commenteb2007-02-261-1/+1
| | | | | | | | | | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4655 221aa14e-8319-0410-a670-987f0aec2ac5
| * | Applied patch from Brett Trotter that stuffs zeros into the head of the tx ↵eb2007-01-176-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signal processing pipeline when the Tx FIFO is empty. This results in the DACs outputing zeros when there's no data, unless the tx pipeline is disabled on the host. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5
| * | removed unused/out-of-date bus_interface.veb2007-01-142-214/+0
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| * | latest version of quartusmatt2006-11-201-1/+1
| | | | | | | | | | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4004 221aa14e-8319-0410-a670-987f0aec2ac5
| * | optimized halfband coefficients, courtesy of Larry Doolittlematt2006-11-011-8/+8
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| * | Partial fix for ticket:81jcorgan2006-10-041-0/+1
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| * | New rbfs. These were compiled using Quartus 6.0 sp1 and include the ↵eb2006-09-274-0/+0
| | | | | | | | | | | | | | | | | | post-ADC / pre-DDC digital rssi measurement code. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3667 221aa14e-8319-0410-a670-987f0aec2ac5
| * | Updated FSF address in all files. Fixes ticket:51eb2006-09-1352-57/+57
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| * | Houston, we have a trunk.jcorgan2006-08-03171-0/+23027
| / | | | | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
* / Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22641-491/+0
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* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-044-15/+259
| | | | | | The counter is for performance monitoring in firmware, priority encoder and new interrupt controller are from quad radio and speed up interrupts. This is tested and it works for me.
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
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* Properly reset the fifos. We didn't connect before.Matt Ettus2009-10-051-5/+5
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* Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan2009-10-01613-90023/+2518
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
| * Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
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| * fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus2009-10-015-17/+159
| | | | | | | | simple_gemac
| * remove unused opencoresMatt Ettus2009-10-01463-71885/+0
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| * Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
| |\ | | | | | | | | | | | | | | | | | | Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
| | * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| | | | | | | | | | | | more sane config options, should be exactly the same memory map
| * | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
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| * | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
| |\| | | | | | | | | | | | | Conflicts: .gitignore
| * | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| | * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
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| * | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
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| * | | remove unused portMatt Ettus2009-09-101-1/+1
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| * | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
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| * | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
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| * | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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| * | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| | | | | | | | | | | | | | | | | | Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
| * | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
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| * | remove unused old style fifoMatt Ettus2009-09-041-31/+0
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| * | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
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| * | debug the rx sideMatt Ettus2009-09-041-1/+6
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| * | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
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| * | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
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| * | MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus2009-09-034-67/+70
| | | | | | | | | | | | accidentally using the rx_clk in one stage of the fifos on the tx side.
| * | set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
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| * | misc ignoresMatt Ettus2009-09-032-0/+3
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| * | made a new block ram based fifo, 64 (65) elements long, all fifos now have ↵Matt Ettus2009-09-0328-155/+652
| | | | | | | | | | | | "enhanced level logic" for accurate fullness. Maybe this will help...
| * | bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
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| * | major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
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| * | cleaning up the new fifosMatt Ettus2009-09-023-155/+0
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| * | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v ↵Matt Ettus2009-09-024-56/+2
| | | | | | | | | | | | and fifo_2clock.v are empty