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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4781 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4780 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4779 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4713 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4695 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4694 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4656 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4655 221aa14e-8319-0410-a670-987f0aec2ac5
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signal processing pipeline when the Tx FIFO is empty.
This results in the DACs outputing zeros when there's no data, unless
the tx pipeline is disabled on the host.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4287 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4277 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4004 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3917 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3709 221aa14e-8319-0410-a670-987f0aec2ac5
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post-ADC / pre-DDC digital rssi measurement code.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3667 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3534 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
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The counter is for performance monitoring in firmware, priority encoder
and new interrupt controller are from quad radio and speed up interrupts.
This is tested and it works for me.
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* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
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simple_gemac
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Functionality should not change at all
Conflicts:
usrp2/fpga/top/u2_core/u2_core.v
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more sane config options, should be exactly the same memory map
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Conflicts:
.gitignore
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Not fully tested, but it seems to work without frame errors, sequence
number errors or ethernet overruns. Still of course will get tx underruns
on a slow machine, and the transmitted signal has some issues though.
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accidentally using the rx_clk in one stage of the fifos on the tx side.
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"enhanced level logic" for accurate fullness. Maybe this will help...
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and fifo_2clock.v are empty
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