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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2006-08-03 04:51:51 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2006-08-03 04:51:51 +0000
commit4f523681b7e786694969bcb7bfddb68b976c8ab7 (patch)
tree8abf3004259c399ba18b7eea297c149bf2d980ce
downloaduhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.tar.gz
uhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.tar.bz2
uhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.zip
Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
-rw-r--r--Makefile.am24
-rw-r--r--Makefile.extra150
-rw-r--r--TODO23
-rwxr-xr-xgen_makefile_extra.py67
-rwxr-xr-xmegacells/accum32.bsf86
-rwxr-xr-xmegacells/accum32.cmp31
-rwxr-xr-xmegacells/accum32.inc32
-rwxr-xr-xmegacells/accum32.v765
-rwxr-xr-xmegacells/accum32_bb.v35
-rwxr-xr-xmegacells/accum32_inst.v7
-rwxr-xr-xmegacells/add32.bsf62
-rwxr-xr-xmegacells/add32.cmp29
-rwxr-xr-xmegacells/add32.inc30
-rwxr-xr-xmegacells/add32.v221
-rwxr-xr-xmegacells/add32_bb.v31
-rwxr-xr-xmegacells/add32_inst.v5
-rwxr-xr-xmegacells/addsub16.bsf96
-rwxr-xr-xmegacells/addsub16.cmp33
-rwxr-xr-xmegacells/addsub16.inc34
-rwxr-xr-xmegacells/addsub16.v438
-rwxr-xr-xmegacells/addsub16_bb.v39
-rwxr-xr-xmegacells/addsub16_inst.v9
-rwxr-xr-xmegacells/bustri.bsf62
-rwxr-xr-xmegacells/bustri.cmp29
-rwxr-xr-xmegacells/bustri.inc30
-rwxr-xr-xmegacells/bustri.v71
-rwxr-xr-xmegacells/bustri_bb.v31
-rwxr-xr-xmegacells/bustri_inst.v5
-rw-r--r--megacells/clk_doubler.v198
-rw-r--r--megacells/clk_doubler_bb.v143
-rw-r--r--megacells/dspclkpll.v237
-rw-r--r--megacells/dspclkpll_bb.v31
-rw-r--r--megacells/fifo_2k.v3343
-rw-r--r--megacells/fifo_2k_bb.v131
-rw-r--r--megacells/fifo_4k.v3495
-rw-r--r--megacells/fifo_4k_bb.v131
-rwxr-xr-xmegacells/mylpm_addsub.bsf80
-rwxr-xr-xmegacells/mylpm_addsub.cmp31
-rwxr-xr-xmegacells/mylpm_addsub.inc32
-rwxr-xr-xmegacells/mylpm_addsub.v102
-rwxr-xr-xmegacells/mylpm_addsub_bb.v35
-rwxr-xr-xmegacells/mylpm_addsub_inst.v7
-rw-r--r--megacells/pll.v207
-rw-r--r--megacells/pll_bb.v29
-rw-r--r--megacells/pll_inst.v4
-rwxr-xr-xmegacells/sub32.bsf87
-rwxr-xr-xmegacells/sub32.cmp32
-rwxr-xr-xmegacells/sub32.inc33
-rwxr-xr-xmegacells/sub32.v675
-rwxr-xr-xmegacells/sub32_bb.v37
-rwxr-xr-xmegacells/sub32_inst.v8
-rw-r--r--models/bustri.v17
-rw-r--r--models/fifo.v81
-rw-r--r--models/fifo_1c_1k.v81
-rw-r--r--models/fifo_1c_2k.v81
-rw-r--r--models/fifo_1c_4k.v76
-rw-r--r--models/fifo_1k.v24
-rw-r--r--models/fifo_2k.v24
-rw-r--r--models/fifo_4k.v24
-rw-r--r--models/pll.v33
-rw-r--r--models/ssram.v38
-rw-r--r--rbf/Makefile.am49
-rwxr-xr-xrbf/rev2/multi_2rxhb_2tx.rbfbin0 -> 180809 bytes
-rwxr-xr-xrbf/rev2/multi_4rx_0tx.rbfbin0 -> 180537 bytes
-rwxr-xr-xrbf/rev2/std_2rxhb_2tx.rbfbin0 -> 175896 bytes
-rwxr-xr-xrbf/rev2/std_4rx_0tx.rbfbin0 -> 171213 bytes
-rwxr-xr-xrbf/rev4/multi_2rxhb_2tx.rbfbin0 -> 180809 bytes
-rwxr-xr-xrbf/rev4/multi_4rx_0tx.rbfbin0 -> 180537 bytes
-rwxr-xr-xrbf/rev4/std_2rxhb_2tx.rbfbin0 -> 175896 bytes
-rwxr-xr-xrbf/rev4/std_4rx_0tx.rbfbin0 -> 171213 bytes
-rw-r--r--sdr_lib/adc_interface.v71
-rw-r--r--sdr_lib/bidir_reg.v29
-rwxr-xr-xsdr_lib/bus_interface.v213
-rwxr-xr-xsdr_lib/cic_decim.v106
-rw-r--r--sdr_lib/cic_int_shifter.v98
-rwxr-xr-xsdr_lib/cic_interp.v88
-rwxr-xr-xsdr_lib/clk_divider.v43
-rwxr-xr-xsdr_lib/cordic.v109
-rwxr-xr-xsdr_lib/cordic_stage.v60
-rwxr-xr-xsdr_lib/ddc.v97
-rw-r--r--sdr_lib/dpram.v47
-rwxr-xr-xsdr_lib/duc.v95
-rw-r--r--sdr_lib/ext_fifo.v126
-rwxr-xr-xsdr_lib/gen_cordic_consts.py10
-rw-r--r--sdr_lib/gen_sync.v43
-rw-r--r--sdr_lib/hb/acc.v22
-rw-r--r--sdr_lib/hb/coeff_ram.v26
-rw-r--r--sdr_lib/hb/coeff_rom.v19
-rw-r--r--sdr_lib/hb/halfband_decim.v163
-rw-r--r--sdr_lib/hb/halfband_interp.v121
-rw-r--r--sdr_lib/hb/hbd_tb/HBD80
-rw-r--r--sdr_lib/hb/hbd_tb/really_golden142
-rw-r--r--sdr_lib/hb/hbd_tb/regression95
-rwxr-xr-xsdr_lib/hb/hbd_tb/run_hbd4
-rw-r--r--sdr_lib/hb/hbd_tb/test_hbd.v75
-rw-r--r--sdr_lib/hb/mac.v58
-rw-r--r--sdr_lib/hb/mult.v16
-rw-r--r--sdr_lib/hb/ram16_2port.v22
-rw-r--r--sdr_lib/hb/ram16_2sum.v27
-rw-r--r--sdr_lib/hb/ram32_2sum.v22
-rw-r--r--sdr_lib/io_pins.v52
-rw-r--r--sdr_lib/master_control.v155
-rw-r--r--sdr_lib/master_control_multi.v73
-rwxr-xr-xsdr_lib/phase_acc.v52
-rw-r--r--sdr_lib/ram.v16
-rw-r--r--sdr_lib/ram16.v17
-rw-r--r--sdr_lib/ram32.v17
-rw-r--r--sdr_lib/ram64.v16
-rw-r--r--sdr_lib/rssi.v30
-rw-r--r--sdr_lib/rx_buffer.v182
-rw-r--r--sdr_lib/rx_chain.v105
-rw-r--r--sdr_lib/rx_chain_dual.v103
-rw-r--r--sdr_lib/rx_dcoffset.v22
-rw-r--r--sdr_lib/serial_io.v118
-rw-r--r--sdr_lib/setting_reg.v23
-rw-r--r--sdr_lib/setting_reg_masked.v26
-rw-r--r--sdr_lib/sign_extend.v35
-rw-r--r--sdr_lib/strobe_gen.v44
-rw-r--r--sdr_lib/tx_buffer.v138
-rw-r--r--sdr_lib/tx_chain.v65
-rw-r--r--sdr_lib/tx_chain_hb.v76
-rw-r--r--tb/cbus_tb.v71
-rw-r--r--tb/cordic_tb.v61
-rw-r--r--tb/decim_tb.v108
-rwxr-xr-xtb/fullchip_tb.v174
-rwxr-xr-xtb/interp_tb.v108
-rw-r--r--tb/justinterp_tb.v73
-rwxr-xr-xtb/makesine.pl14
-rwxr-xr-xtb/run_cordic4
-rwxr-xr-xtb/run_fullchip4
-rwxr-xr-xtb/usrp_tasks.v145
-rw-r--r--toplevel/mrfm/biquad_2stage.v131
-rw-r--r--toplevel/mrfm/biquad_6stage.v137
-rw-r--r--toplevel/mrfm/mrfm.csf444
-rw-r--r--toplevel/mrfm/mrfm.esf14
-rw-r--r--toplevel/mrfm/mrfm.psf312
-rw-r--r--toplevel/mrfm/mrfm.py129
-rw-r--r--toplevel/mrfm/mrfm.qpf29
-rw-r--r--toplevel/mrfm/mrfm.qsf411
-rw-r--r--toplevel/mrfm/mrfm.v199
-rw-r--r--toplevel/mrfm/mrfm.vh21
-rw-r--r--toplevel/mrfm/mrfm_compensator.v80
-rwxr-xr-xtoplevel/mrfm/mrfm_fft.py319
-rw-r--r--toplevel/mrfm/mrfm_proc.v96
-rw-r--r--toplevel/mrfm/shifter.v106
-rw-r--r--toplevel/sizetest/sizetest.csf160
-rw-r--r--toplevel/sizetest/sizetest.psf228
-rw-r--r--toplevel/sizetest/sizetest.quartus19
-rw-r--r--toplevel/sizetest/sizetest.ssf14
-rw-r--r--toplevel/sizetest/sizetest.v39
-rw-r--r--toplevel/usrp_multi/usrp_multi.csf444
-rw-r--r--toplevel/usrp_multi/usrp_multi.esf14
-rw-r--r--toplevel/usrp_multi/usrp_multi.psf312
-rw-r--r--toplevel/usrp_multi/usrp_multi.qpf29
-rw-r--r--toplevel/usrp_multi/usrp_multi.qsf408
-rw-r--r--toplevel/usrp_multi/usrp_multi.v379
-rw-r--r--toplevel/usrp_multi/usrp_multi.vh141
-rw-r--r--toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh62
-rw-r--r--toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh62
-rw-r--r--toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh62
-rw-r--r--toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh62
-rw-r--r--toplevel/usrp_multi/usrp_std.vh29
-rw-r--r--toplevel/usrp_std/usrp_std.csf444
-rw-r--r--toplevel/usrp_std/usrp_std.esf14
-rw-r--r--toplevel/usrp_std/usrp_std.psf312
-rw-r--r--toplevel/usrp_std/usrp_std.qpf29
-rw-r--r--toplevel/usrp_std/usrp_std.qsf406
-rw-r--r--toplevel/usrp_std/usrp_std.v324
-rw-r--r--toplevel/usrp_std/usrp_std.vh119
-rw-r--r--toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh61
-rw-r--r--toplevel/usrp_std/usrp_std_config_4rx_0tx.vh61
171 files changed, 23027 insertions, 0 deletions
diff --git a/Makefile.am b/Makefile.am
new file mode 100644
index 000000000..61227f056
--- /dev/null
+++ b/Makefile.am
@@ -0,0 +1,24 @@
+#
+# Copyright 2004,2005,2006 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+#
+
+SUBDIRS = rbf
+
+include Makefile.extra
diff --git a/Makefile.extra b/Makefile.extra
new file mode 100644
index 000000000..c3ccaa043
--- /dev/null
+++ b/Makefile.extra
@@ -0,0 +1,150 @@
+EXTRA_DIST = \
+ gen_makefile_extra.py \
+ megacells/accum32.bsf \
+ megacells/accum32.cmp \
+ megacells/accum32.inc \
+ megacells/accum32.v \
+ megacells/accum32_bb.v \
+ megacells/accum32_inst.v \
+ megacells/add32.bsf \
+ megacells/add32.cmp \
+ megacells/add32.inc \
+ megacells/add32.v \
+ megacells/add32_bb.v \
+ megacells/add32_inst.v \
+ megacells/addsub16.bsf \
+ megacells/addsub16.cmp \
+ megacells/addsub16.inc \
+ megacells/addsub16.v \
+ megacells/addsub16_bb.v \
+ megacells/addsub16_inst.v \
+ megacells/bustri.bsf \
+ megacells/bustri.cmp \
+ megacells/bustri.inc \
+ megacells/bustri.v \
+ megacells/bustri_bb.v \
+ megacells/bustri_inst.v \
+ megacells/clk_doubler.v \
+ megacells/clk_doubler_bb.v \
+ megacells/dspclkpll.v \
+ megacells/dspclkpll_bb.v \
+ megacells/fifo_2k.v \
+ megacells/fifo_2k_bb.v \
+ megacells/fifo_4k.v \
+ megacells/fifo_4k_bb.v \
+ megacells/mylpm_addsub.bsf \
+ megacells/mylpm_addsub.cmp \
+ megacells/mylpm_addsub.inc \
+ megacells/mylpm_addsub.v \
+ megacells/mylpm_addsub_bb.v \
+ megacells/mylpm_addsub_inst.v \
+ megacells/pll.v \
+ megacells/pll_bb.v \
+ megacells/pll_inst.v \
+ megacells/sub32.bsf \
+ megacells/sub32.cmp \
+ megacells/sub32.inc \
+ megacells/sub32.v \
+ megacells/sub32_bb.v \
+ megacells/sub32_inst.v \
+ models/bustri.v \
+ models/fifo.v \
+ models/fifo_1c_1k.v \
+ models/fifo_1c_2k.v \
+ models/fifo_1c_4k.v \
+ models/fifo_1k.v \
+ models/fifo_2k.v \
+ models/fifo_4k.v \
+ models/pll.v \
+ models/ssram.v \
+ sdr_lib/adc_interface.v \
+ sdr_lib/bidir_reg.v \
+ sdr_lib/bus_interface.v \
+ sdr_lib/cic_decim.v \
+ sdr_lib/cic_int_shifter.v \
+ sdr_lib/cic_interp.v \
+ sdr_lib/clk_divider.v \
+ sdr_lib/cordic.v \
+ sdr_lib/cordic_stage.v \
+ sdr_lib/ddc.v \
+ sdr_lib/dpram.v \
+ sdr_lib/duc.v \
+ sdr_lib/ext_fifo.v \
+ sdr_lib/gen_cordic_consts.py \
+ sdr_lib/gen_sync.v \
+ sdr_lib/hb/acc.v \
+ sdr_lib/hb/coeff_ram.v \
+ sdr_lib/hb/coeff_rom.v \
+ sdr_lib/hb/halfband_decim.v \
+ sdr_lib/hb/halfband_interp.v \
+ sdr_lib/hb/hbd_tb/test_hbd.v \
+ sdr_lib/hb/mac.v \
+ sdr_lib/hb/mult.v \
+ sdr_lib/hb/ram16_2port.v \
+ sdr_lib/hb/ram16_2sum.v \
+ sdr_lib/hb/ram32_2sum.v \
+ sdr_lib/io_pins.v \
+ sdr_lib/master_control.v \
+ sdr_lib/master_control_multi.v \
+ sdr_lib/phase_acc.v \
+ sdr_lib/ram.v \
+ sdr_lib/ram16.v \
+ sdr_lib/ram32.v \
+ sdr_lib/ram64.v \
+ sdr_lib/rx_buffer.v \
+ sdr_lib/rx_chain.v \
+ sdr_lib/rx_chain_dual.v \
+ sdr_lib/rx_dcoffset.v \
+ sdr_lib/serial_io.v \
+ sdr_lib/setting_reg.v \
+ sdr_lib/setting_reg_masked.v \
+ sdr_lib/sign_extend.v \
+ sdr_lib/strobe_gen.v \
+ sdr_lib/tx_buffer.v \
+ sdr_lib/tx_chain.v \
+ sdr_lib/tx_chain_hb.v \
+ tb/cbus_tb.v \
+ tb/cordic_tb.v \
+ tb/decim_tb.v \
+ tb/fullchip_tb.v \
+ tb/interp_tb.v \
+ tb/justinterp_tb.v \
+ tb/usrp_tasks.v \
+ toplevel/mrfm/biquad_2stage.v \
+ toplevel/mrfm/biquad_6stage.v \
+ toplevel/mrfm/mrfm.csf \
+ toplevel/mrfm/mrfm.esf \
+ toplevel/mrfm/mrfm.psf \
+ toplevel/mrfm/mrfm.py \
+ toplevel/mrfm/mrfm.qpf \
+ toplevel/mrfm/mrfm.qsf \
+ toplevel/mrfm/mrfm.v \
+ toplevel/mrfm/mrfm.vh \
+ toplevel/mrfm/mrfm_compensator.v \
+ toplevel/mrfm/mrfm_fft.py \
+ toplevel/mrfm/mrfm_proc.v \
+ toplevel/mrfm/shifter.v \
+ toplevel/sizetest/sizetest.csf \
+ toplevel/sizetest/sizetest.psf \
+ toplevel/sizetest/sizetest.v \
+ toplevel/usrp_multi/usrp_multi.csf \
+ toplevel/usrp_multi/usrp_multi.esf \
+ toplevel/usrp_multi/usrp_multi.psf \
+ toplevel/usrp_multi/usrp_multi.qpf \
+ toplevel/usrp_multi/usrp_multi.qsf \
+ toplevel/usrp_multi/usrp_multi.v \
+ toplevel/usrp_multi/usrp_multi.vh \
+ toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh \
+ toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh \
+ toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh \
+ toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh \
+ toplevel/usrp_multi/usrp_std.vh \
+ toplevel/usrp_std/usrp_std.csf \
+ toplevel/usrp_std/usrp_std.esf \
+ toplevel/usrp_std/usrp_std.psf \
+ toplevel/usrp_std/usrp_std.qpf \
+ toplevel/usrp_std/usrp_std.qsf \
+ toplevel/usrp_std/usrp_std.v \
+ toplevel/usrp_std/usrp_std.vh \
+ toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh \
+ toplevel/usrp_std/usrp_std_config_4rx_0tx.vh
diff --git a/TODO b/TODO
new file mode 100644
index 000000000..76287c3d4
--- /dev/null
+++ b/TODO
@@ -0,0 +1,23 @@
+
+
+Area Reduction
+==============
+Reduce one or both stages of dec/interp to max rate of 8 instead of 16
+Optimize CICs to minimize registers
+Reduce width of RX CORDIC
+Fix CORDIC wasted logic cells from bad synthesis
+Progressively narrow x,y,z on CORDIC
+16-bit wide FIFOs, split IQ/channels on other side (?)
+
+Enhancements
+============
+Halfband filter in Spartan 3
+Muxing of inputs
+Switch over to newfc
+RAM interface?
+
+Other
+=====
+Capture/Transmit straight samples (no DUC/DDC)
+
+
diff --git a/gen_makefile_extra.py b/gen_makefile_extra.py
new file mode 100755
index 000000000..165a84940
--- /dev/null
+++ b/gen_makefile_extra.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python
+#
+# Copyright 2006 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+#
+
+"""
+Generate Makefile.extra
+"""
+
+import sys
+import os.path
+
+extensions_we_like = (
+ '.v', '.vh',
+ '.csf', '.esf', '.psf', '.qpf', '.qsf',
+ '.inc', '.cmp', '.bsf',
+ '.py')
+
+def visit(keepers, dirname, names):
+ if 'rbf' in names:
+ names.remove('rbf')
+ if 'CVS' in names:
+ names.remove('CVS')
+
+ if dirname == '.':
+ dirname = ''
+ if dirname.startswith('./'):
+ dirname = dirname[2:]
+
+ for n in names:
+ base, ext = os.path.splitext(n)
+ if ext in extensions_we_like:
+ keepers.append(os.path.join(dirname, n))
+
+def generate(f):
+ keepers = []
+ os.path.walk('.', visit, keepers)
+ keepers.sort()
+ write_keepers(keepers, f)
+
+def write_keepers(files, outf):
+ m = reduce(max, map(len, files), 0)
+ e = 'EXTRA_DIST ='
+ outf.write('%s%s \\\n' % (e, (m-len(e)+8) * ' '))
+ for f in files[:-1]:
+ outf.write('\t%s%s \\\n' % (f, (m-len(f)) * ' '))
+ outf.write('\t%s\n' % (files[-1],))
+
+if __name__ == '__main__':
+ generate(open('Makefile.extra','w'))
diff --git a/megacells/accum32.bsf b/megacells/accum32.bsf
new file mode 100755
index 000000000..494a8200f
--- /dev/null
+++ b/megacells/accum32.bsf
@@ -0,0 +1,86 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 240 120)
+ (text "accum32" (rect 87 2 166 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 101 31 116)(font "Arial" ))
+ (port
+ (pt 0 40)
+ (input)
+ (text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "data[31..0]" (rect 20 24 82 40)(font "Arial" (font_size 8)))
+ (line (pt 0 40)(pt 16 40)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clock" (rect 20 40 51 56)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clken" (rect 20 56 51 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 80 41 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 240 56)
+ (output)
+ (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "result[31..0]" (rect 152 40 221 56)(font "Arial" (font_size 8)))
+ (line (pt 240 56)(pt 224 56)(line_width 3))
+ )
+ (drawing
+ (text "acc" (rect 102 48 123 64)(font "Arial" (font_size 8)))
+ (text "SIGNED" (rect 177 18 214 32)(font "Arial" ))
+ (line (pt 16 16)(pt 224 16)(line_width 1))
+ (line (pt 16 16)(pt 16 104)(line_width 1))
+ (line (pt 16 104)(pt 224 104)(line_width 1))
+ (line (pt 224 16)(pt 224 104)(line_width 1))
+ (line (pt 88 24)(pt 136 48)(line_width 1))
+ (line (pt 136 64)(pt 136 48)(line_width 1))
+ (line (pt 88 88)(pt 136 64)(line_width 1))
+ (line (pt 88 24)(pt 88 88)(line_width 1))
+ (line (pt 16 40)(pt 88 40)(line_width 1))
+ (line (pt 16 56)(pt 88 56)(line_width 1))
+ (line (pt 136 56)(pt 224 56)(line_width 1))
+ (line (pt 16 72)(pt 88 72)(line_width 1))
+ (line (pt 16 72)(pt 88 72)(line_width 1))
+ (line (pt 16 96)(pt 104 96)(line_width 1))
+ (line (pt 104 96)(pt 104 80)(line_width 1))
+ )
+)
diff --git a/megacells/accum32.cmp b/megacells/accum32.cmp
new file mode 100755
index 000000000..55b5fdc22
--- /dev/null
+++ b/megacells/accum32.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component accum32
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clock : IN STD_LOGIC := '0';
+ clken : IN STD_LOGIC := '1';
+ aclr : IN STD_LOGIC := '0';
+ result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/accum32.inc b/megacells/accum32.inc
new file mode 100755
index 000000000..6c6690025
--- /dev/null
+++ b/megacells/accum32.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION accum32
+(
+ data[31..0],
+ clock,
+ clken,
+ aclr
+)
+
+RETURNS (
+ result[31..0]
+);
diff --git a/megacells/accum32.v b/megacells/accum32.v
new file mode 100755
index 000000000..ce50cbbf1
--- /dev/null
+++ b/megacells/accum32.v
@@ -0,0 +1,765 @@
+// megafunction wizard: %ALTACCUMULATE%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altaccumulate
+
+// ============================================================
+// File Name: accum32.v
+// Megafunction Name(s):
+// altaccumulate
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
+//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
+
+//synthesis_resources = lut 32
+module accum32_accum_nta
+ (
+ aclr,
+ clken,
+ clock,
+ data,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clken;
+ input clock;
+ input [31:0] data;
+ output [31:0] result;
+
+ wire [0:0] wire_acc_cella_0cout;
+ wire [0:0] wire_acc_cella_1cout;
+ wire [0:0] wire_acc_cella_2cout;
+ wire [0:0] wire_acc_cella_3cout;
+ wire [0:0] wire_acc_cella_4cout;
+ wire [0:0] wire_acc_cella_5cout;
+ wire [0:0] wire_acc_cella_6cout;
+ wire [0:0] wire_acc_cella_7cout;
+ wire [0:0] wire_acc_cella_8cout;
+ wire [0:0] wire_acc_cella_9cout;
+ wire [0:0] wire_acc_cella_10cout;
+ wire [0:0] wire_acc_cella_11cout;
+ wire [0:0] wire_acc_cella_12cout;
+ wire [0:0] wire_acc_cella_13cout;
+ wire [0:0] wire_acc_cella_14cout;
+ wire [0:0] wire_acc_cella_15cout;
+ wire [0:0] wire_acc_cella_16cout;
+ wire [0:0] wire_acc_cella_17cout;
+ wire [0:0] wire_acc_cella_18cout;
+ wire [0:0] wire_acc_cella_19cout;
+ wire [0:0] wire_acc_cella_20cout;
+ wire [0:0] wire_acc_cella_21cout;
+ wire [0:0] wire_acc_cella_22cout;
+ wire [0:0] wire_acc_cella_23cout;
+ wire [0:0] wire_acc_cella_24cout;
+ wire [0:0] wire_acc_cella_25cout;
+ wire [0:0] wire_acc_cella_26cout;
+ wire [0:0] wire_acc_cella_27cout;
+ wire [0:0] wire_acc_cella_28cout;
+ wire [0:0] wire_acc_cella_29cout;
+ wire [0:0] wire_acc_cella_30cout;
+ wire [31:0] wire_acc_cella_dataa;
+ wire [31:0] wire_acc_cella_datab;
+ wire [31:0] wire_acc_cella_datac;
+ wire [31:0] wire_acc_cella_regout;
+ wire sload;
+
+ stratix_lcell acc_cella_0
+ (
+ .aclr(aclr),
+ .cin(1'b0),
+ .clk(clock),
+ .cout(wire_acc_cella_0cout[0:0]),
+ .dataa(wire_acc_cella_dataa[0:0]),
+ .datab(wire_acc_cella_datab[0:0]),
+ .datac(wire_acc_cella_datac[0:0]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[0:0]),
+ .sload(sload));
+ defparam
+ acc_cella_0.cin_used = "true",
+ acc_cella_0.lut_mask = "96e8",
+ acc_cella_0.operation_mode = "arithmetic",
+ acc_cella_0.sum_lutc_input = "cin",
+ acc_cella_0.synch_mode = "on",
+ acc_cella_0.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_1
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_0cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_1cout[0:0]),
+ .dataa(wire_acc_cella_dataa[1:1]),
+ .datab(wire_acc_cella_datab[1:1]),
+ .datac(wire_acc_cella_datac[1:1]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[1:1]),
+ .sload(sload));
+ defparam
+ acc_cella_1.cin_used = "true",
+ acc_cella_1.lut_mask = "96e8",
+ acc_cella_1.operation_mode = "arithmetic",
+ acc_cella_1.sum_lutc_input = "cin",
+ acc_cella_1.synch_mode = "on",
+ acc_cella_1.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_2
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_1cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_2cout[0:0]),
+ .dataa(wire_acc_cella_dataa[2:2]),
+ .datab(wire_acc_cella_datab[2:2]),
+ .datac(wire_acc_cella_datac[2:2]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[2:2]),
+ .sload(sload));
+ defparam
+ acc_cella_2.cin_used = "true",
+ acc_cella_2.lut_mask = "96e8",
+ acc_cella_2.operation_mode = "arithmetic",
+ acc_cella_2.sum_lutc_input = "cin",
+ acc_cella_2.synch_mode = "on",
+ acc_cella_2.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_3
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_2cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_3cout[0:0]),
+ .dataa(wire_acc_cella_dataa[3:3]),
+ .datab(wire_acc_cella_datab[3:3]),
+ .datac(wire_acc_cella_datac[3:3]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[3:3]),
+ .sload(sload));
+ defparam
+ acc_cella_3.cin_used = "true",
+ acc_cella_3.lut_mask = "96e8",
+ acc_cella_3.operation_mode = "arithmetic",
+ acc_cella_3.sum_lutc_input = "cin",
+ acc_cella_3.synch_mode = "on",
+ acc_cella_3.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_4
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_3cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_4cout[0:0]),
+ .dataa(wire_acc_cella_dataa[4:4]),
+ .datab(wire_acc_cella_datab[4:4]),
+ .datac(wire_acc_cella_datac[4:4]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[4:4]),
+ .sload(sload));
+ defparam
+ acc_cella_4.cin_used = "true",
+ acc_cella_4.lut_mask = "96e8",
+ acc_cella_4.operation_mode = "arithmetic",
+ acc_cella_4.sum_lutc_input = "cin",
+ acc_cella_4.synch_mode = "on",
+ acc_cella_4.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_5
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_4cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_5cout[0:0]),
+ .dataa(wire_acc_cella_dataa[5:5]),
+ .datab(wire_acc_cella_datab[5:5]),
+ .datac(wire_acc_cella_datac[5:5]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[5:5]),
+ .sload(sload));
+ defparam
+ acc_cella_5.cin_used = "true",
+ acc_cella_5.lut_mask = "96e8",
+ acc_cella_5.operation_mode = "arithmetic",
+ acc_cella_5.sum_lutc_input = "cin",
+ acc_cella_5.synch_mode = "on",
+ acc_cella_5.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_6
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_5cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_6cout[0:0]),
+ .dataa(wire_acc_cella_dataa[6:6]),
+ .datab(wire_acc_cella_datab[6:6]),
+ .datac(wire_acc_cella_datac[6:6]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[6:6]),
+ .sload(sload));
+ defparam
+ acc_cella_6.cin_used = "true",
+ acc_cella_6.lut_mask = "96e8",
+ acc_cella_6.operation_mode = "arithmetic",
+ acc_cella_6.sum_lutc_input = "cin",
+ acc_cella_6.synch_mode = "on",
+ acc_cella_6.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_7
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_6cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_7cout[0:0]),
+ .dataa(wire_acc_cella_dataa[7:7]),
+ .datab(wire_acc_cella_datab[7:7]),
+ .datac(wire_acc_cella_datac[7:7]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[7:7]),
+ .sload(sload));
+ defparam
+ acc_cella_7.cin_used = "true",
+ acc_cella_7.lut_mask = "96e8",
+ acc_cella_7.operation_mode = "arithmetic",
+ acc_cella_7.sum_lutc_input = "cin",
+ acc_cella_7.synch_mode = "on",
+ acc_cella_7.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_8
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_7cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_8cout[0:0]),
+ .dataa(wire_acc_cella_dataa[8:8]),
+ .datab(wire_acc_cella_datab[8:8]),
+ .datac(wire_acc_cella_datac[8:8]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[8:8]),
+ .sload(sload));
+ defparam
+ acc_cella_8.cin_used = "true",
+ acc_cella_8.lut_mask = "96e8",
+ acc_cella_8.operation_mode = "arithmetic",
+ acc_cella_8.sum_lutc_input = "cin",
+ acc_cella_8.synch_mode = "on",
+ acc_cella_8.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_9
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_8cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_9cout[0:0]),
+ .dataa(wire_acc_cella_dataa[9:9]),
+ .datab(wire_acc_cella_datab[9:9]),
+ .datac(wire_acc_cella_datac[9:9]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[9:9]),
+ .sload(sload));
+ defparam
+ acc_cella_9.cin_used = "true",
+ acc_cella_9.lut_mask = "96e8",
+ acc_cella_9.operation_mode = "arithmetic",
+ acc_cella_9.sum_lutc_input = "cin",
+ acc_cella_9.synch_mode = "on",
+ acc_cella_9.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_10
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_9cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_10cout[0:0]),
+ .dataa(wire_acc_cella_dataa[10:10]),
+ .datab(wire_acc_cella_datab[10:10]),
+ .datac(wire_acc_cella_datac[10:10]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[10:10]),
+ .sload(sload));
+ defparam
+ acc_cella_10.cin_used = "true",
+ acc_cella_10.lut_mask = "96e8",
+ acc_cella_10.operation_mode = "arithmetic",
+ acc_cella_10.sum_lutc_input = "cin",
+ acc_cella_10.synch_mode = "on",
+ acc_cella_10.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_11
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_10cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_11cout[0:0]),
+ .dataa(wire_acc_cella_dataa[11:11]),
+ .datab(wire_acc_cella_datab[11:11]),
+ .datac(wire_acc_cella_datac[11:11]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[11:11]),
+ .sload(sload));
+ defparam
+ acc_cella_11.cin_used = "true",
+ acc_cella_11.lut_mask = "96e8",
+ acc_cella_11.operation_mode = "arithmetic",
+ acc_cella_11.sum_lutc_input = "cin",
+ acc_cella_11.synch_mode = "on",
+ acc_cella_11.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_12
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_11cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_12cout[0:0]),
+ .dataa(wire_acc_cella_dataa[12:12]),
+ .datab(wire_acc_cella_datab[12:12]),
+ .datac(wire_acc_cella_datac[12:12]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[12:12]),
+ .sload(sload));
+ defparam
+ acc_cella_12.cin_used = "true",
+ acc_cella_12.lut_mask = "96e8",
+ acc_cella_12.operation_mode = "arithmetic",
+ acc_cella_12.sum_lutc_input = "cin",
+ acc_cella_12.synch_mode = "on",
+ acc_cella_12.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_13
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_12cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_13cout[0:0]),
+ .dataa(wire_acc_cella_dataa[13:13]),
+ .datab(wire_acc_cella_datab[13:13]),
+ .datac(wire_acc_cella_datac[13:13]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[13:13]),
+ .sload(sload));
+ defparam
+ acc_cella_13.cin_used = "true",
+ acc_cella_13.lut_mask = "96e8",
+ acc_cella_13.operation_mode = "arithmetic",
+ acc_cella_13.sum_lutc_input = "cin",
+ acc_cella_13.synch_mode = "on",
+ acc_cella_13.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_14
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_13cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_14cout[0:0]),
+ .dataa(wire_acc_cella_dataa[14:14]),
+ .datab(wire_acc_cella_datab[14:14]),
+ .datac(wire_acc_cella_datac[14:14]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[14:14]),
+ .sload(sload));
+ defparam
+ acc_cella_14.cin_used = "true",
+ acc_cella_14.lut_mask = "96e8",
+ acc_cella_14.operation_mode = "arithmetic",
+ acc_cella_14.sum_lutc_input = "cin",
+ acc_cella_14.synch_mode = "on",
+ acc_cella_14.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_15
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_14cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_15cout[0:0]),
+ .dataa(wire_acc_cella_dataa[15:15]),
+ .datab(wire_acc_cella_datab[15:15]),
+ .datac(wire_acc_cella_datac[15:15]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[15:15]),
+ .sload(sload));
+ defparam
+ acc_cella_15.cin_used = "true",
+ acc_cella_15.lut_mask = "96e8",
+ acc_cella_15.operation_mode = "arithmetic",
+ acc_cella_15.sum_lutc_input = "cin",
+ acc_cella_15.synch_mode = "on",
+ acc_cella_15.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_16
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_15cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_16cout[0:0]),
+ .dataa(wire_acc_cella_dataa[16:16]),
+ .datab(wire_acc_cella_datab[16:16]),
+ .datac(wire_acc_cella_datac[16:16]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[16:16]),
+ .sload(sload));
+ defparam
+ acc_cella_16.cin_used = "true",
+ acc_cella_16.lut_mask = "96e8",
+ acc_cella_16.operation_mode = "arithmetic",
+ acc_cella_16.sum_lutc_input = "cin",
+ acc_cella_16.synch_mode = "on",
+ acc_cella_16.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_17
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_16cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_17cout[0:0]),
+ .dataa(wire_acc_cella_dataa[17:17]),
+ .datab(wire_acc_cella_datab[17:17]),
+ .datac(wire_acc_cella_datac[17:17]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[17:17]),
+ .sload(sload));
+ defparam
+ acc_cella_17.cin_used = "true",
+ acc_cella_17.lut_mask = "96e8",
+ acc_cella_17.operation_mode = "arithmetic",
+ acc_cella_17.sum_lutc_input = "cin",
+ acc_cella_17.synch_mode = "on",
+ acc_cella_17.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_18
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_17cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_18cout[0:0]),
+ .dataa(wire_acc_cella_dataa[18:18]),
+ .datab(wire_acc_cella_datab[18:18]),
+ .datac(wire_acc_cella_datac[18:18]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[18:18]),
+ .sload(sload));
+ defparam
+ acc_cella_18.cin_used = "true",
+ acc_cella_18.lut_mask = "96e8",
+ acc_cella_18.operation_mode = "arithmetic",
+ acc_cella_18.sum_lutc_input = "cin",
+ acc_cella_18.synch_mode = "on",
+ acc_cella_18.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_19
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_18cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_19cout[0:0]),
+ .dataa(wire_acc_cella_dataa[19:19]),
+ .datab(wire_acc_cella_datab[19:19]),
+ .datac(wire_acc_cella_datac[19:19]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[19:19]),
+ .sload(sload));
+ defparam
+ acc_cella_19.cin_used = "true",
+ acc_cella_19.lut_mask = "96e8",
+ acc_cella_19.operation_mode = "arithmetic",
+ acc_cella_19.sum_lutc_input = "cin",
+ acc_cella_19.synch_mode = "on",
+ acc_cella_19.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_20
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_19cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_20cout[0:0]),
+ .dataa(wire_acc_cella_dataa[20:20]),
+ .datab(wire_acc_cella_datab[20:20]),
+ .datac(wire_acc_cella_datac[20:20]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[20:20]),
+ .sload(sload));
+ defparam
+ acc_cella_20.cin_used = "true",
+ acc_cella_20.lut_mask = "96e8",
+ acc_cella_20.operation_mode = "arithmetic",
+ acc_cella_20.sum_lutc_input = "cin",
+ acc_cella_20.synch_mode = "on",
+ acc_cella_20.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_21
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_20cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_21cout[0:0]),
+ .dataa(wire_acc_cella_dataa[21:21]),
+ .datab(wire_acc_cella_datab[21:21]),
+ .datac(wire_acc_cella_datac[21:21]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[21:21]),
+ .sload(sload));
+ defparam
+ acc_cella_21.cin_used = "true",
+ acc_cella_21.lut_mask = "96e8",
+ acc_cella_21.operation_mode = "arithmetic",
+ acc_cella_21.sum_lutc_input = "cin",
+ acc_cella_21.synch_mode = "on",
+ acc_cella_21.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_22
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_21cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_22cout[0:0]),
+ .dataa(wire_acc_cella_dataa[22:22]),
+ .datab(wire_acc_cella_datab[22:22]),
+ .datac(wire_acc_cella_datac[22:22]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[22:22]),
+ .sload(sload));
+ defparam
+ acc_cella_22.cin_used = "true",
+ acc_cella_22.lut_mask = "96e8",
+ acc_cella_22.operation_mode = "arithmetic",
+ acc_cella_22.sum_lutc_input = "cin",
+ acc_cella_22.synch_mode = "on",
+ acc_cella_22.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_23
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_22cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_23cout[0:0]),
+ .dataa(wire_acc_cella_dataa[23:23]),
+ .datab(wire_acc_cella_datab[23:23]),
+ .datac(wire_acc_cella_datac[23:23]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[23:23]),
+ .sload(sload));
+ defparam
+ acc_cella_23.cin_used = "true",
+ acc_cella_23.lut_mask = "96e8",
+ acc_cella_23.operation_mode = "arithmetic",
+ acc_cella_23.sum_lutc_input = "cin",
+ acc_cella_23.synch_mode = "on",
+ acc_cella_23.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_24
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_23cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_24cout[0:0]),
+ .dataa(wire_acc_cella_dataa[24:24]),
+ .datab(wire_acc_cella_datab[24:24]),
+ .datac(wire_acc_cella_datac[24:24]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[24:24]),
+ .sload(sload));
+ defparam
+ acc_cella_24.cin_used = "true",
+ acc_cella_24.lut_mask = "96e8",
+ acc_cella_24.operation_mode = "arithmetic",
+ acc_cella_24.sum_lutc_input = "cin",
+ acc_cella_24.synch_mode = "on",
+ acc_cella_24.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_25
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_24cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_25cout[0:0]),
+ .dataa(wire_acc_cella_dataa[25:25]),
+ .datab(wire_acc_cella_datab[25:25]),
+ .datac(wire_acc_cella_datac[25:25]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[25:25]),
+ .sload(sload));
+ defparam
+ acc_cella_25.cin_used = "true",
+ acc_cella_25.lut_mask = "96e8",
+ acc_cella_25.operation_mode = "arithmetic",
+ acc_cella_25.sum_lutc_input = "cin",
+ acc_cella_25.synch_mode = "on",
+ acc_cella_25.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_26
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_25cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_26cout[0:0]),
+ .dataa(wire_acc_cella_dataa[26:26]),
+ .datab(wire_acc_cella_datab[26:26]),
+ .datac(wire_acc_cella_datac[26:26]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[26:26]),
+ .sload(sload));
+ defparam
+ acc_cella_26.cin_used = "true",
+ acc_cella_26.lut_mask = "96e8",
+ acc_cella_26.operation_mode = "arithmetic",
+ acc_cella_26.sum_lutc_input = "cin",
+ acc_cella_26.synch_mode = "on",
+ acc_cella_26.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_27
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_26cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_27cout[0:0]),
+ .dataa(wire_acc_cella_dataa[27:27]),
+ .datab(wire_acc_cella_datab[27:27]),
+ .datac(wire_acc_cella_datac[27:27]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[27:27]),
+ .sload(sload));
+ defparam
+ acc_cella_27.cin_used = "true",
+ acc_cella_27.lut_mask = "96e8",
+ acc_cella_27.operation_mode = "arithmetic",
+ acc_cella_27.sum_lutc_input = "cin",
+ acc_cella_27.synch_mode = "on",
+ acc_cella_27.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_28
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_27cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_28cout[0:0]),
+ .dataa(wire_acc_cella_dataa[28:28]),
+ .datab(wire_acc_cella_datab[28:28]),
+ .datac(wire_acc_cella_datac[28:28]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[28:28]),
+ .sload(sload));
+ defparam
+ acc_cella_28.cin_used = "true",
+ acc_cella_28.lut_mask = "96e8",
+ acc_cella_28.operation_mode = "arithmetic",
+ acc_cella_28.sum_lutc_input = "cin",
+ acc_cella_28.synch_mode = "on",
+ acc_cella_28.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_29
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_28cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_29cout[0:0]),
+ .dataa(wire_acc_cella_dataa[29:29]),
+ .datab(wire_acc_cella_datab[29:29]),
+ .datac(wire_acc_cella_datac[29:29]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[29:29]),
+ .sload(sload));
+ defparam
+ acc_cella_29.cin_used = "true",
+ acc_cella_29.lut_mask = "96e8",
+ acc_cella_29.operation_mode = "arithmetic",
+ acc_cella_29.sum_lutc_input = "cin",
+ acc_cella_29.synch_mode = "on",
+ acc_cella_29.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_30
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_29cout[0:0]),
+ .clk(clock),
+ .cout(wire_acc_cella_30cout[0:0]),
+ .dataa(wire_acc_cella_dataa[30:30]),
+ .datab(wire_acc_cella_datab[30:30]),
+ .datac(wire_acc_cella_datac[30:30]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[30:30]),
+ .sload(sload));
+ defparam
+ acc_cella_30.cin_used = "true",
+ acc_cella_30.lut_mask = "96e8",
+ acc_cella_30.operation_mode = "arithmetic",
+ acc_cella_30.sum_lutc_input = "cin",
+ acc_cella_30.synch_mode = "on",
+ acc_cella_30.lpm_type = "stratix_lcell";
+ stratix_lcell acc_cella_31
+ (
+ .aclr(aclr),
+ .cin(wire_acc_cella_30cout[0:0]),
+ .clk(clock),
+ .dataa(wire_acc_cella_dataa[31:31]),
+ .datab(wire_acc_cella_datab[31:31]),
+ .datac(wire_acc_cella_datac[31:31]),
+ .ena(clken),
+ .regout(wire_acc_cella_regout[31:31]),
+ .sload(sload));
+ defparam
+ acc_cella_31.cin_used = "true",
+ acc_cella_31.lut_mask = "9696",
+ acc_cella_31.operation_mode = "normal",
+ acc_cella_31.sum_lutc_input = "cin",
+ acc_cella_31.synch_mode = "on",
+ acc_cella_31.lpm_type = "stratix_lcell";
+ assign
+ wire_acc_cella_dataa = data,
+ wire_acc_cella_datab = wire_acc_cella_regout,
+ wire_acc_cella_datac = data;
+ assign
+ result = wire_acc_cella_regout,
+ sload = 1'b0;
+endmodule //accum32_accum_nta
+//VALID FILE
+
+
+module accum32 (
+ data,
+ clock,
+ clken,
+ aclr,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [31:0] data;
+ input clock;
+ input clken;
+ input aclr;
+ output [31:0] result;
+
+ wire [31:0] sub_wire0;
+ wire [31:0] result = sub_wire0[31:0];
+
+ accum32_accum_nta accum32_accum_nta_component (
+ .clken (clken),
+ .aclr (aclr),
+ .clock (clock),
+ .data (data),
+ .result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
+// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
+// Retrieval info: PRIVATE: CIN NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: ACLR NUMERIC "1"
+// Retrieval info: PRIVATE: COUT NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
+// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
+// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
diff --git a/megacells/accum32_bb.v b/megacells/accum32_bb.v
new file mode 100755
index 000000000..142bde88c
--- /dev/null
+++ b/megacells/accum32_bb.v
@@ -0,0 +1,35 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module accum32 (
+ data,
+ clock,
+ clken,
+ aclr,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [31:0] data;
+ input clock;
+ input clken;
+ input aclr;
+ output [31:0] result;
+
+endmodule
+
diff --git a/megacells/accum32_inst.v b/megacells/accum32_inst.v
new file mode 100755
index 000000000..c354accae
--- /dev/null
+++ b/megacells/accum32_inst.v
@@ -0,0 +1,7 @@
+accum32 accum32_inst (
+ .data ( data_sig ),
+ .clock ( clock_sig ),
+ .clken ( clken_sig ),
+ .aclr ( aclr_sig ),
+ .result ( result_sig )
+ );
diff --git a/megacells/add32.bsf b/megacells/add32.bsf
new file mode 100755
index 000000000..b2da9fc2a
--- /dev/null
+++ b/megacells/add32.bsf
@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 96)
+ (text "add32" (rect 58 2 111 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 77 31 92)(font "Arial" ))
+ (port
+ (pt 0 40)
+ (input)
+ (text "dataa[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "dataa[7..0]" (rect 4 24 66 40)(font "Arial" (font_size 8)))
+ (line (pt 0 40)(pt 64 40)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "datab[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "datab[7..0]" (rect 4 56 66 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+ (text "result[7..0]" (rect 95 40 157 56)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 96 56)(line_width 3))
+ )
+ (drawing
+ (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
+ (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
+ (text "A+B" (rect 68 48 94 64)(font "Arial" (font_size 8)))
+ (line (pt 64 32)(pt 96 40)(line_width 1))
+ (line (pt 96 40)(pt 96 72)(line_width 1))
+ (line (pt 96 72)(pt 64 80)(line_width 1))
+ (line (pt 64 80)(pt 64 32)(line_width 1))
+ )
+)
diff --git a/megacells/add32.cmp b/megacells/add32.cmp
new file mode 100755
index 000000000..3b120176d
--- /dev/null
+++ b/megacells/add32.cmp
@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component add32
+ PORT
+ (
+ dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/add32.inc b/megacells/add32.inc
new file mode 100755
index 000000000..675525713
--- /dev/null
+++ b/megacells/add32.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION add32
+(
+ dataa[7..0],
+ datab[7..0]
+)
+
+RETURNS (
+ result[7..0]
+);
diff --git a/megacells/add32.v b/megacells/add32.v
new file mode 100755
index 000000000..d8090617a
--- /dev/null
+++ b/megacells/add32.v
@@ -0,0 +1,221 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub
+
+// ============================================================
+// File Name: add32.v
+// Megafunction Name(s):
+// lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
+
+//synthesis_resources = lut 8
+module add32_add_sub_nq7
+ (
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input [7:0] dataa;
+ input [7:0] datab;
+ output [7:0] result;
+
+ wire [7:0] wire_add_sub_cella_combout;
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [7:0] wire_add_sub_cella_dataa;
+ wire [7:0] wire_add_sub_cella_datab;
+
+ stratix_lcell add_sub_cella_0
+ (
+ .cin(1'b0),
+ .combout(wire_add_sub_cella_combout[0:0]),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]));
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "96e8",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_1
+ (
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .combout(wire_add_sub_cella_combout[1:1]),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]));
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "96e8",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_2
+ (
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .combout(wire_add_sub_cella_combout[2:2]),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]));
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "96e8",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_3
+ (
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .combout(wire_add_sub_cella_combout[3:3]),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]));
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "96e8",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_4
+ (
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .combout(wire_add_sub_cella_combout[4:4]),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]));
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "96e8",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_5
+ (
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .combout(wire_add_sub_cella_combout[5:5]),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]));
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "96e8",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_6
+ (
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .combout(wire_add_sub_cella_combout[6:6]),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]));
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "96e8",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_7
+ (
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .combout(wire_add_sub_cella_combout[7:7]),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]));
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "9696",
+ add_sub_cella_7.operation_mode = "normal",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "stratix_lcell";
+ assign
+ wire_add_sub_cella_dataa = dataa,
+ wire_add_sub_cella_datab = datab;
+ assign
+ result = wire_add_sub_cella_combout;
+endmodule //add32_add_sub_nq7
+//VALID FILE
+
+
+module add32 (
+ dataa,
+ datab,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [7:0] dataa;
+ input [7:0] datab;
+ output [7:0] result;
+
+ wire [7:0] sub_wire0;
+ wire [7:0] result = sub_wire0[7:0];
+
+ add32_add_sub_nq7 add32_add_sub_nq7_component (
+ .dataa (dataa),
+ .datab (datab),
+ .result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "8"
+// Retrieval info: PRIVATE: Function NUMERIC "0"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
+// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
+// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
+// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/megacells/add32_bb.v b/megacells/add32_bb.v
new file mode 100755
index 000000000..8d1588cc6
--- /dev/null
+++ b/megacells/add32_bb.v
@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module add32 (
+ dataa,
+ datab,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [7:0] dataa;
+ input [7:0] datab;
+ output [7:0] result;
+
+endmodule
+
diff --git a/megacells/add32_inst.v b/megacells/add32_inst.v
new file mode 100755
index 000000000..bc7e6d441
--- /dev/null
+++ b/megacells/add32_inst.v
@@ -0,0 +1,5 @@
+add32 add32_inst (
+ .dataa ( dataa_sig ),
+ .datab ( datab_sig ),
+ .result ( result_sig )
+ );
diff --git a/megacells/addsub16.bsf b/megacells/addsub16.bsf
new file mode 100755
index 000000000..9ed6b72ae
--- /dev/null
+++ b/megacells/addsub16.bsf
@@ -0,0 +1,96 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 144)
+ (text "addsub16" (rect 45 2 128 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 125 31 140)(font "Arial" ))
+ (port
+ (pt 0 56)
+ (input)
+ (text "dataa[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 64 56)(line_width 3))
+ )
+ (port
+ (pt 0 88)
+ (input)
+ (text "datab[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
+ (line (pt 0 88)(pt 64 88)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "add_sub" (rect 0 0 57 16)(font "Arial" (font_size 8)))
+ (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 80 32)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clken" (rect 4 96 35 112)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 74 112)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 4 112 25 128)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 85 128)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 96 72)(line_width 3))
+ )
+ (drawing
+ (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
+ (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
+ (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
+ (line (pt 64 48)(pt 96 56)(line_width 1))
+ (line (pt 96 56)(pt 96 88)(line_width 1))
+ (line (pt 96 88)(pt 64 96)(line_width 1))
+ (line (pt 64 96)(pt 64 48)(line_width 1))
+ (line (pt 80 32)(pt 80 52)(line_width 1))
+ (line (pt 106 40)(pt 125 40)(line_width 1))
+ (line (pt 74 112)(pt 74 93)(line_width 1))
+ (line (pt 85 128)(pt 85 90)(line_width 1))
+ (line (pt 64 66)(pt 70 72)(line_width 1))
+ (line (pt 70 72)(pt 64 78)(line_width 1))
+ )
+)
diff --git a/megacells/addsub16.cmp b/megacells/addsub16.cmp
new file mode 100755
index 000000000..e32e01b31
--- /dev/null
+++ b/megacells/addsub16.cmp
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component addsub16
+ PORT
+ (
+ add_sub : IN STD_LOGIC ;
+ dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ clock : IN STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clken : IN STD_LOGIC ;
+ result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/addsub16.inc b/megacells/addsub16.inc
new file mode 100755
index 000000000..846f301d2
--- /dev/null
+++ b/megacells/addsub16.inc
@@ -0,0 +1,34 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION addsub16
+(
+ add_sub,
+ dataa[15..0],
+ datab[15..0],
+ clock,
+ aclr,
+ clken
+)
+
+RETURNS (
+ result[15..0]
+);
diff --git a/megacells/addsub16.v b/megacells/addsub16.v
new file mode 100755
index 000000000..431af3e43
--- /dev/null
+++ b/megacells/addsub16.v
@@ -0,0 +1,438 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub
+
+// ============================================================
+// File Name: addsub16.v
+// Megafunction Name(s):
+// lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
+
+//synthesis_resources = lut 17
+module addsub16_add_sub_gp9
+ (
+ aclr,
+ add_sub,
+ clken,
+ clock,
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input add_sub;
+ input clken;
+ input clock;
+ input [15:0] dataa;
+ input [15:0] datab;
+ output [15:0] result;
+
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [0:0] wire_add_sub_cella_7cout;
+ wire [0:0] wire_add_sub_cella_8cout;
+ wire [0:0] wire_add_sub_cella_9cout;
+ wire [0:0] wire_add_sub_cella_10cout;
+ wire [0:0] wire_add_sub_cella_11cout;
+ wire [0:0] wire_add_sub_cella_12cout;
+ wire [0:0] wire_add_sub_cella_13cout;
+ wire [0:0] wire_add_sub_cella_14cout;
+ wire [15:0] wire_add_sub_cella_dataa;
+ wire [15:0] wire_add_sub_cella_datab;
+ wire [15:0] wire_add_sub_cella_regout;
+ wire wire_strx_lcell1_cout;
+
+ stratix_lcell add_sub_cella_0
+ (
+ .aclr(aclr),
+ .cin(wire_strx_lcell1_cout),
+ .clk(clock),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[0:0]));
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "96e8",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_1
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[1:1]));
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "96e8",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_2
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[2:2]));
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "96e8",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_3
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[3:3]));
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "96e8",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_4
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[4:4]));
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "96e8",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_5
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[5:5]));
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "96e8",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_6
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[6:6]));
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "96e8",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_7
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_7cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[7:7]));
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "96e8",
+ add_sub_cella_7.operation_mode = "arithmetic",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_8
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_7cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_8cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[8:8]),
+ .datab(wire_add_sub_cella_datab[8:8]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[8:8]));
+ defparam
+ add_sub_cella_8.cin_used = "true",
+ add_sub_cella_8.lut_mask = "96e8",
+ add_sub_cella_8.operation_mode = "arithmetic",
+ add_sub_cella_8.sum_lutc_input = "cin",
+ add_sub_cella_8.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_9
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_8cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_9cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[9:9]),
+ .datab(wire_add_sub_cella_datab[9:9]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[9:9]));
+ defparam
+ add_sub_cella_9.cin_used = "true",
+ add_sub_cella_9.lut_mask = "96e8",
+ add_sub_cella_9.operation_mode = "arithmetic",
+ add_sub_cella_9.sum_lutc_input = "cin",
+ add_sub_cella_9.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_10
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_9cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_10cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[10:10]),
+ .datab(wire_add_sub_cella_datab[10:10]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[10:10]));
+ defparam
+ add_sub_cella_10.cin_used = "true",
+ add_sub_cella_10.lut_mask = "96e8",
+ add_sub_cella_10.operation_mode = "arithmetic",
+ add_sub_cella_10.sum_lutc_input = "cin",
+ add_sub_cella_10.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_11
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_10cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_11cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[11:11]),
+ .datab(wire_add_sub_cella_datab[11:11]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[11:11]));
+ defparam
+ add_sub_cella_11.cin_used = "true",
+ add_sub_cella_11.lut_mask = "96e8",
+ add_sub_cella_11.operation_mode = "arithmetic",
+ add_sub_cella_11.sum_lutc_input = "cin",
+ add_sub_cella_11.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_12
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_11cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_12cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[12:12]),
+ .datab(wire_add_sub_cella_datab[12:12]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[12:12]));
+ defparam
+ add_sub_cella_12.cin_used = "true",
+ add_sub_cella_12.lut_mask = "96e8",
+ add_sub_cella_12.operation_mode = "arithmetic",
+ add_sub_cella_12.sum_lutc_input = "cin",
+ add_sub_cella_12.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_13
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_12cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_13cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[13:13]),
+ .datab(wire_add_sub_cella_datab[13:13]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[13:13]));
+ defparam
+ add_sub_cella_13.cin_used = "true",
+ add_sub_cella_13.lut_mask = "96e8",
+ add_sub_cella_13.operation_mode = "arithmetic",
+ add_sub_cella_13.sum_lutc_input = "cin",
+ add_sub_cella_13.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_14
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_13cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_14cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[14:14]),
+ .datab(wire_add_sub_cella_datab[14:14]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[14:14]));
+ defparam
+ add_sub_cella_14.cin_used = "true",
+ add_sub_cella_14.lut_mask = "96e8",
+ add_sub_cella_14.operation_mode = "arithmetic",
+ add_sub_cella_14.sum_lutc_input = "cin",
+ add_sub_cella_14.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_15
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_14cout[0:0]),
+ .clk(clock),
+ .dataa(wire_add_sub_cella_dataa[15:15]),
+ .datab(wire_add_sub_cella_datab[15:15]),
+ .ena(clken),
+ .inverta((~ add_sub)),
+ .regout(wire_add_sub_cella_regout[15:15]));
+ defparam
+ add_sub_cella_15.cin_used = "true",
+ add_sub_cella_15.lut_mask = "9696",
+ add_sub_cella_15.operation_mode = "normal",
+ add_sub_cella_15.sum_lutc_input = "cin",
+ add_sub_cella_15.lpm_type = "stratix_lcell";
+ assign
+ wire_add_sub_cella_dataa = datab,
+ wire_add_sub_cella_datab = dataa;
+ stratix_lcell strx_lcell1
+ (
+ .cout(wire_strx_lcell1_cout),
+ .dataa(1'b0),
+ .datab((~ add_sub)),
+ .inverta((~ add_sub)));
+ defparam
+ strx_lcell1.cin_used = "false",
+ strx_lcell1.lut_mask = "00cc",
+ strx_lcell1.operation_mode = "arithmetic",
+ strx_lcell1.lpm_type = "stratix_lcell";
+ assign
+ result = wire_add_sub_cella_regout;
+endmodule //addsub16_add_sub_gp9
+//VALID FILE
+
+
+module addsub16 (
+ add_sub,
+ dataa,
+ datab,
+ clock,
+ aclr,
+ clken,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input add_sub;
+ input [15:0] dataa;
+ input [15:0] datab;
+ input clock;
+ input aclr;
+ input clken;
+ output [15:0] result;
+
+ wire [15:0] sub_wire0;
+ wire [15:0] result = sub_wire0[15:0];
+
+ addsub16_add_sub_gp9 addsub16_add_sub_gp9_component (
+ .dataa (dataa),
+ .add_sub (add_sub),
+ .datab (datab),
+ .clken (clken),
+ .aclr (aclr),
+ .clock (clock),
+ .result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: Function NUMERIC "2"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "1"
+// Retrieval info: PRIVATE: clken NUMERIC "1"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/megacells/addsub16_bb.v b/megacells/addsub16_bb.v
new file mode 100755
index 000000000..8e1e7c69f
--- /dev/null
+++ b/megacells/addsub16_bb.v
@@ -0,0 +1,39 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module addsub16 (
+ add_sub,
+ dataa,
+ datab,
+ clock,
+ aclr,
+ clken,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input add_sub;
+ input [15:0] dataa;
+ input [15:0] datab;
+ input clock;
+ input aclr;
+ input clken;
+ output [15:0] result;
+
+endmodule
+
diff --git a/megacells/addsub16_inst.v b/megacells/addsub16_inst.v
new file mode 100755
index 000000000..4a81ff2ee
--- /dev/null
+++ b/megacells/addsub16_inst.v
@@ -0,0 +1,9 @@
+addsub16 addsub16_inst (
+ .add_sub ( add_sub_sig ),
+ .dataa ( dataa_sig ),
+ .datab ( datab_sig ),
+ .clock ( clock_sig ),
+ .aclr ( aclr_sig ),
+ .clken ( clken_sig ),
+ .result ( result_sig )
+ );
diff --git a/megacells/bustri.bsf b/megacells/bustri.bsf
new file mode 100755
index 000000000..f1bc3ca7f
--- /dev/null
+++ b/megacells/bustri.bsf
@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 80 40)
+ (text "bustri" (rect 24 1 61 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 24 25 36)(font "Arial" ))
+ (port
+ (pt 40 40)
+ (input)
+ (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+ (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+ (line (pt 40 40)(pt 40 28)(line_width 1))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+ (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+ (line (pt 0 24)(pt 32 24)(line_width 3))
+ )
+ (port
+ (pt 80 24)
+ (bidir)
+ (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+ (text "tridata[15..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+ (line (pt 80 24)(pt 48 24)(line_width 3))
+ )
+ (drawing
+ (text "16" (rect 61 25 71 37)(font "Arial" ))
+ (text "16" (rect 13 25 23 37)(font "Arial" ))
+ (line (pt 32 16)(pt 48 24)(line_width 1))
+ (line (pt 48 24)(pt 32 32)(line_width 1))
+ (line (pt 32 32)(pt 32 16)(line_width 1))
+ (line (pt 56 28)(pt 64 20)(line_width 1))
+ (line (pt 8 28)(pt 16 20)(line_width 1))
+ )
+)
diff --git a/megacells/bustri.cmp b/megacells/bustri.cmp
new file mode 100755
index 000000000..87599ca66
--- /dev/null
+++ b/megacells/bustri.cmp
@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component bustri
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ enabledt : IN STD_LOGIC ;
+ tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/bustri.inc b/megacells/bustri.inc
new file mode 100755
index 000000000..399950389
--- /dev/null
+++ b/megacells/bustri.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION bustri
+(
+ data[15..0],
+ enabledt
+)
+
+RETURNS (
+ tridata[15..0]
+);
diff --git a/megacells/bustri.v b/megacells/bustri.v
new file mode 100755
index 000000000..e40c69476
--- /dev/null
+++ b/megacells/bustri.v
@@ -0,0 +1,71 @@
+// megafunction wizard: %LPM_BUSTRI%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_bustri
+
+// ============================================================
+// File Name: bustri.v
+// Megafunction Name(s):
+// lpm_bustri
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module bustri (
+ data,
+ enabledt,
+ tridata);
+
+ input [15:0] data;
+ input enabledt;
+ inout [15:0] tridata;
+
+
+ lpm_bustri lpm_bustri_component (
+ .tridata (tridata),
+ .enabledt (enabledt),
+ .data (data));
+ defparam
+ lpm_bustri_component.lpm_width = 16,
+ lpm_bustri_component.lpm_type = "LPM_BUSTRI";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: BiDir NUMERIC "0"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/megacells/bustri_bb.v b/megacells/bustri_bb.v
new file mode 100755
index 000000000..4cbc1609c
--- /dev/null
+++ b/megacells/bustri_bb.v
@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module bustri (
+ data,
+ enabledt,
+ tridata);
+
+ input [15:0] data;
+ input enabledt;
+ inout [15:0] tridata;
+
+endmodule
+
diff --git a/megacells/bustri_inst.v b/megacells/bustri_inst.v
new file mode 100755
index 000000000..2b4e49638
--- /dev/null
+++ b/megacells/bustri_inst.v
@@ -0,0 +1,5 @@
+bustri bustri_inst (
+ .data ( data_sig ),
+ .enabledt ( enabledt_sig ),
+ .tridata ( tridata_sig )
+ );
diff --git a/megacells/clk_doubler.v b/megacells/clk_doubler.v
new file mode 100644
index 000000000..b3762a960
--- /dev/null
+++ b/megacells/clk_doubler.v
@@ -0,0 +1,198 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module clk_doubler (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .activeclock (),
+ .areset (),
+ .clkbad (),
+ .clkena (),
+ .clkloss (),
+ .clkswitch (),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena (),
+ .fbin (),
+ .locked (),
+ .pfdena (),
+ .pllena (),
+ .scanaclr (),
+ .scanclk (),
+ .scandata (),
+ .scandataout (),
+ .scandone (),
+ .scanread (),
+ .scanwrite (),
+ .sclkout0 (),
+ .sclkout1 ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.inclk0_input_frequency = 15625,
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.pll_type = "AUTO",
+ altpll_component.intended_device_family = "Cyclone",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
diff --git a/megacells/clk_doubler_bb.v b/megacells/clk_doubler_bb.v
new file mode 100644
index 000000000..48c52e795
--- /dev/null
+++ b/megacells/clk_doubler_bb.v
@@ -0,0 +1,143 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module clk_doubler (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
diff --git a/megacells/dspclkpll.v b/megacells/dspclkpll.v
new file mode 100644
index 000000000..81e622137
--- /dev/null
+++ b/megacells/dspclkpll.v
@@ -0,0 +1,237 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: dspclkpll.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dspclkpll (
+ inclk0,
+ c0,
+ c1);
+
+ input inclk0;
+ output c0;
+ output c1;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .clk (sub_wire0)
+ // synopsys translate_off
+,
+ .fbin (),
+ .pllena (),
+ .clkswitch (),
+ .areset (),
+ .pfdena (),
+ .clkena (),
+ .extclkena (),
+ .scanclk (),
+ .scanaclr (),
+ .scandata (),
+ .scanread (),
+ .scanwrite (),
+ .extclk (),
+ .clkbad (),
+ .activeclock (),
+ .locked (),
+ .clkloss (),
+ .scandataout (),
+ .scandone (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .enable0 (),
+ .enable1 ()
+ // synopsys translate_on
+
+);
+ defparam
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.inclk0_input_frequency = 15625,
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.pll_type = "AUTO",
+ altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk0_time_delay = "0",
+ altpll_component.intended_device_family = "Cyclone",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk1_time_delay = "0",
+ altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
diff --git a/megacells/dspclkpll_bb.v b/megacells/dspclkpll_bb.v
new file mode 100644
index 000000000..489be7bd4
--- /dev/null
+++ b/megacells/dspclkpll_bb.v
@@ -0,0 +1,31 @@
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module dspclkpll (
+ inclk0,
+ c0,
+ c1);
+
+ input inclk0;
+ output c0;
+ output c1;
+
+endmodule
+
diff --git a/megacells/fifo_2k.v b/megacells/fifo_2k.v
new file mode 100644
index 000000000..5e2a38520
--- /dev/null
+++ b/megacells/fifo_2k.v
@@ -0,0 +1,3343 @@
+// megafunction wizard: %FIFO%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_2k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+
+//a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
+
+//synthesis_resources =
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_a_gray2bin_8m4
+ (
+ bin,
+ gray) /* synthesis synthesis_clearbox=1 */;
+ output [10:0] bin;
+ input [10:0] gray;
+
+ wire xor0;
+ wire xor1;
+ wire xor2;
+ wire xor3;
+ wire xor4;
+ wire xor5;
+ wire xor6;
+ wire xor7;
+ wire xor8;
+ wire xor9;
+
+ assign
+ bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+ xor0 = (gray[0] ^ xor1),
+ xor1 = (gray[1] ^ xor2),
+ xor2 = (gray[2] ^ xor3),
+ xor3 = (gray[3] ^ xor4),
+ xor4 = (gray[4] ^ xor5),
+ xor5 = (gray[5] ^ xor6),
+ xor6 = (gray[6] ^ xor7),
+ xor7 = (gray[7] ^ xor8),
+ xor8 = (gray[8] ^ xor9),
+ xor9 = (gray[10] ^ gray[9]);
+endmodule //fifo_2k_a_gray2bin_8m4
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_a_graycounter_726
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [10:0] q;
+
+ wire [0:0] wire_countera_0cout;
+ wire [0:0] wire_countera_1cout;
+ wire [0:0] wire_countera_2cout;
+ wire [0:0] wire_countera_3cout;
+ wire [0:0] wire_countera_4cout;
+ wire [0:0] wire_countera_5cout;
+ wire [0:0] wire_countera_6cout;
+ wire [0:0] wire_countera_7cout;
+ wire [0:0] wire_countera_8cout;
+ wire [0:0] wire_countera_9cout;
+ wire [10:0] wire_countera_regout;
+ wire wire_parity_cout;
+ wire wire_parity_regout;
+ wire [10:0] power_modified_counter_values;
+ wire sclr;
+ wire updown;
+
+ cyclone_lcell countera_0
+ (
+ .aclr(aclr),
+ .cin(wire_parity_cout),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_0cout[0:0]),
+ .dataa(cnt_en),
+ .datab(wire_countera_regout[0:0]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[0:0]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_0.cin_used = "true",
+ countera_0.lut_mask = "c6a0",
+ countera_0.operation_mode = "arithmetic",
+ countera_0.sum_lutc_input = "cin",
+ countera_0.synch_mode = "on",
+ countera_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_1
+ (
+ .aclr(aclr),
+ .cin(wire_countera_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_1cout[0:0]),
+ .dataa(power_modified_counter_values[0]),
+ .datab(power_modified_counter_values[1]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[1:1]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_1.cin_used = "true",
+ countera_1.lut_mask = "6c50",
+ countera_1.operation_mode = "arithmetic",
+ countera_1.sum_lutc_input = "cin",
+ countera_1.synch_mode = "on",
+ countera_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_2
+ (
+ .aclr(aclr),
+ .cin(wire_countera_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_2cout[0:0]),
+ .dataa(power_modified_counter_values[1]),
+ .datab(power_modified_counter_values[2]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[2:2]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_2.cin_used = "true",
+ countera_2.lut_mask = "6c50",
+ countera_2.operation_mode = "arithmetic",
+ countera_2.sum_lutc_input = "cin",
+ countera_2.synch_mode = "on",
+ countera_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_3
+ (
+ .aclr(aclr),
+ .cin(wire_countera_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_3cout[0:0]),
+ .dataa(power_modified_counter_values[2]),
+ .datab(power_modified_counter_values[3]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[3:3]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_3.cin_used = "true",
+ countera_3.lut_mask = "6c50",
+ countera_3.operation_mode = "arithmetic",
+ countera_3.sum_lutc_input = "cin",
+ countera_3.synch_mode = "on",
+ countera_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_4
+ (
+ .aclr(aclr),
+ .cin(wire_countera_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_4cout[0:0]),
+ .dataa(power_modified_counter_values[3]),
+ .datab(power_modified_counter_values[4]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[4:4]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_4.cin_used = "true",
+ countera_4.lut_mask = "6c50",
+ countera_4.operation_mode = "arithmetic",
+ countera_4.sum_lutc_input = "cin",
+ countera_4.synch_mode = "on",
+ countera_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_5
+ (
+ .aclr(aclr),
+ .cin(wire_countera_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_5cout[0:0]),
+ .dataa(power_modified_counter_values[4]),
+ .datab(power_modified_counter_values[5]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[5:5]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_5.cin_used = "true",
+ countera_5.lut_mask = "6c50",
+ countera_5.operation_mode = "arithmetic",
+ countera_5.sum_lutc_input = "cin",
+ countera_5.synch_mode = "on",
+ countera_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_6
+ (
+ .aclr(aclr),
+ .cin(wire_countera_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_6cout[0:0]),
+ .dataa(power_modified_counter_values[5]),
+ .datab(power_modified_counter_values[6]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[6:6]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_6.cin_used = "true",
+ countera_6.lut_mask = "6c50",
+ countera_6.operation_mode = "arithmetic",
+ countera_6.sum_lutc_input = "cin",
+ countera_6.synch_mode = "on",
+ countera_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_7
+ (
+ .aclr(aclr),
+ .cin(wire_countera_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_7cout[0:0]),
+ .dataa(power_modified_counter_values[6]),
+ .datab(power_modified_counter_values[7]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[7:7]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_7.cin_used = "true",
+ countera_7.lut_mask = "6c50",
+ countera_7.operation_mode = "arithmetic",
+ countera_7.sum_lutc_input = "cin",
+ countera_7.synch_mode = "on",
+ countera_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_8
+ (
+ .aclr(aclr),
+ .cin(wire_countera_7cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_8cout[0:0]),
+ .dataa(power_modified_counter_values[7]),
+ .datab(power_modified_counter_values[8]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[8:8]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_8.cin_used = "true",
+ countera_8.lut_mask = "6c50",
+ countera_8.operation_mode = "arithmetic",
+ countera_8.sum_lutc_input = "cin",
+ countera_8.synch_mode = "on",
+ countera_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_9
+ (
+ .aclr(aclr),
+ .cin(wire_countera_8cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_9cout[0:0]),
+ .dataa(power_modified_counter_values[8]),
+ .datab(power_modified_counter_values[9]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[9:9]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_9.cin_used = "true",
+ countera_9.lut_mask = "6c50",
+ countera_9.operation_mode = "arithmetic",
+ countera_9.sum_lutc_input = "cin",
+ countera_9.synch_mode = "on",
+ countera_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_10
+ (
+ .aclr(aclr),
+ .cin(wire_countera_9cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(power_modified_counter_values[10]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[10:10]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datab(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_10.cin_used = "true",
+ countera_10.lut_mask = "5a5a",
+ countera_10.operation_mode = "normal",
+ countera_10.sum_lutc_input = "cin",
+ countera_10.synch_mode = "on",
+ countera_10.lpm_type = "cyclone_lcell";
+ cyclone_lcell parity
+ (
+ .aclr(aclr),
+ .cin(updown),
+ .clk(clock),
+ .combout(),
+ .cout(wire_parity_cout),
+ .dataa(cnt_en),
+ .datab(wire_parity_regout),
+ .ena(1'b1),
+ .regout(wire_parity_regout),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ parity.cin_used = "true",
+ parity.lut_mask = "6682",
+ parity.operation_mode = "arithmetic",
+ parity.synch_mode = "on",
+ parity.lpm_type = "cyclone_lcell";
+ assign
+ power_modified_counter_values = {wire_countera_regout[10:0]},
+ q = power_modified_counter_values,
+ sclr = 1'b0,
+ updown = 1'b1;
+endmodule //fifo_2k_a_graycounter_726
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_a_graycounter_2r6
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [10:0] q;
+
+ wire [0:0] wire_countera_0cout;
+ wire [0:0] wire_countera_1cout;
+ wire [0:0] wire_countera_2cout;
+ wire [0:0] wire_countera_3cout;
+ wire [0:0] wire_countera_4cout;
+ wire [0:0] wire_countera_5cout;
+ wire [0:0] wire_countera_6cout;
+ wire [0:0] wire_countera_7cout;
+ wire [0:0] wire_countera_8cout;
+ wire [0:0] wire_countera_9cout;
+ wire [10:0] wire_countera_regout;
+ wire wire_parity_cout;
+ wire wire_parity_regout;
+ wire [10:0] power_modified_counter_values;
+ wire sclr;
+ wire updown;
+
+ cyclone_lcell countera_0
+ (
+ .aclr(aclr),
+ .cin(wire_parity_cout),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_0cout[0:0]),
+ .dataa(cnt_en),
+ .datab(wire_countera_regout[0:0]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[0:0]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_0.cin_used = "true",
+ countera_0.lut_mask = "c6a0",
+ countera_0.operation_mode = "arithmetic",
+ countera_0.sum_lutc_input = "cin",
+ countera_0.synch_mode = "on",
+ countera_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_1
+ (
+ .aclr(aclr),
+ .cin(wire_countera_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_1cout[0:0]),
+ .dataa(power_modified_counter_values[0]),
+ .datab(power_modified_counter_values[1]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[1:1]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_1.cin_used = "true",
+ countera_1.lut_mask = "6c50",
+ countera_1.operation_mode = "arithmetic",
+ countera_1.sum_lutc_input = "cin",
+ countera_1.synch_mode = "on",
+ countera_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_2
+ (
+ .aclr(aclr),
+ .cin(wire_countera_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_2cout[0:0]),
+ .dataa(power_modified_counter_values[1]),
+ .datab(power_modified_counter_values[2]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[2:2]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_2.cin_used = "true",
+ countera_2.lut_mask = "6c50",
+ countera_2.operation_mode = "arithmetic",
+ countera_2.sum_lutc_input = "cin",
+ countera_2.synch_mode = "on",
+ countera_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_3
+ (
+ .aclr(aclr),
+ .cin(wire_countera_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_3cout[0:0]),
+ .dataa(power_modified_counter_values[2]),
+ .datab(power_modified_counter_values[3]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[3:3]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_3.cin_used = "true",
+ countera_3.lut_mask = "6c50",
+ countera_3.operation_mode = "arithmetic",
+ countera_3.sum_lutc_input = "cin",
+ countera_3.synch_mode = "on",
+ countera_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_4
+ (
+ .aclr(aclr),
+ .cin(wire_countera_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_4cout[0:0]),
+ .dataa(power_modified_counter_values[3]),
+ .datab(power_modified_counter_values[4]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[4:4]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_4.cin_used = "true",
+ countera_4.lut_mask = "6c50",
+ countera_4.operation_mode = "arithmetic",
+ countera_4.sum_lutc_input = "cin",
+ countera_4.synch_mode = "on",
+ countera_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_5
+ (
+ .aclr(aclr),
+ .cin(wire_countera_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_5cout[0:0]),
+ .dataa(power_modified_counter_values[4]),
+ .datab(power_modified_counter_values[5]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[5:5]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_5.cin_used = "true",
+ countera_5.lut_mask = "6c50",
+ countera_5.operation_mode = "arithmetic",
+ countera_5.sum_lutc_input = "cin",
+ countera_5.synch_mode = "on",
+ countera_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_6
+ (
+ .aclr(aclr),
+ .cin(wire_countera_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_6cout[0:0]),
+ .dataa(power_modified_counter_values[5]),
+ .datab(power_modified_counter_values[6]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[6:6]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_6.cin_used = "true",
+ countera_6.lut_mask = "6c50",
+ countera_6.operation_mode = "arithmetic",
+ countera_6.sum_lutc_input = "cin",
+ countera_6.synch_mode = "on",
+ countera_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_7
+ (
+ .aclr(aclr),
+ .cin(wire_countera_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_7cout[0:0]),
+ .dataa(power_modified_counter_values[6]),
+ .datab(power_modified_counter_values[7]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[7:7]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_7.cin_used = "true",
+ countera_7.lut_mask = "6c50",
+ countera_7.operation_mode = "arithmetic",
+ countera_7.sum_lutc_input = "cin",
+ countera_7.synch_mode = "on",
+ countera_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_8
+ (
+ .aclr(aclr),
+ .cin(wire_countera_7cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_8cout[0:0]),
+ .dataa(power_modified_counter_values[7]),
+ .datab(power_modified_counter_values[8]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[8:8]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_8.cin_used = "true",
+ countera_8.lut_mask = "6c50",
+ countera_8.operation_mode = "arithmetic",
+ countera_8.sum_lutc_input = "cin",
+ countera_8.synch_mode = "on",
+ countera_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_9
+ (
+ .aclr(aclr),
+ .cin(wire_countera_8cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_9cout[0:0]),
+ .dataa(power_modified_counter_values[8]),
+ .datab(power_modified_counter_values[9]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[9:9]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_9.cin_used = "true",
+ countera_9.lut_mask = "6c50",
+ countera_9.operation_mode = "arithmetic",
+ countera_9.sum_lutc_input = "cin",
+ countera_9.synch_mode = "on",
+ countera_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_10
+ (
+ .aclr(aclr),
+ .cin(wire_countera_9cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(power_modified_counter_values[10]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[10:10]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datab(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_10.cin_used = "true",
+ countera_10.lut_mask = "5a5a",
+ countera_10.operation_mode = "normal",
+ countera_10.sum_lutc_input = "cin",
+ countera_10.synch_mode = "on",
+ countera_10.lpm_type = "cyclone_lcell";
+ cyclone_lcell parity
+ (
+ .aclr(aclr),
+ .cin(updown),
+ .clk(clock),
+ .combout(),
+ .cout(wire_parity_cout),
+ .dataa(cnt_en),
+ .datab((~ wire_parity_regout)),
+ .ena(1'b1),
+ .regout(wire_parity_regout),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ parity.cin_used = "true",
+ parity.lut_mask = "9982",
+ parity.operation_mode = "arithmetic",
+ parity.synch_mode = "on",
+ parity.lpm_type = "cyclone_lcell";
+ assign
+ power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
+ q = power_modified_counter_values,
+ sclr = 1'b0,
+ updown = 1'b1;
+endmodule //fifo_2k_a_graycounter_2r6
+
+
+//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
+//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = M4K 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_altsyncram_6pl
+ (
+ address_a,
+ address_b,
+ clock0,
+ clock1,
+ clocken1,
+ data_a,
+ q_b,
+ wren_a) /* synthesis synthesis_clearbox=1 */;
+ input [10:0] address_a;
+ input [10:0] address_b;
+ input clock0;
+ input clock1;
+ input clocken1;
+ input [15:0] data_a;
+ output [15:0] q_b;
+ input wren_a;
+
+ wire [0:0] wire_ram_block3a_0portbdataout;
+ wire [0:0] wire_ram_block3a_1portbdataout;
+ wire [0:0] wire_ram_block3a_2portbdataout;
+ wire [0:0] wire_ram_block3a_3portbdataout;
+ wire [0:0] wire_ram_block3a_4portbdataout;
+ wire [0:0] wire_ram_block3a_5portbdataout;
+ wire [0:0] wire_ram_block3a_6portbdataout;
+ wire [0:0] wire_ram_block3a_7portbdataout;
+ wire [0:0] wire_ram_block3a_8portbdataout;
+ wire [0:0] wire_ram_block3a_9portbdataout;
+ wire [0:0] wire_ram_block3a_10portbdataout;
+ wire [0:0] wire_ram_block3a_11portbdataout;
+ wire [0:0] wire_ram_block3a_12portbdataout;
+ wire [0:0] wire_ram_block3a_13portbdataout;
+ wire [0:0] wire_ram_block3a_14portbdataout;
+ wire [0:0] wire_ram_block3a_15portbdataout;
+ wire [10:0] address_a_wire;
+ wire [10:0] address_b_wire;
+
+ cyclone_ram_block ram_block3a_0
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[0]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_0portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_0.connectivity_checking = "OFF",
+ ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_0.operation_mode = "dual_port",
+ ram_block3a_0.port_a_address_width = 11,
+ ram_block3a_0.port_a_data_width = 1,
+ ram_block3a_0.port_a_first_address = 0,
+ ram_block3a_0.port_a_first_bit_number = 0,
+ ram_block3a_0.port_a_last_address = 2047,
+ ram_block3a_0.port_a_logical_ram_depth = 2048,
+ ram_block3a_0.port_a_logical_ram_width = 16,
+ ram_block3a_0.port_b_address_clear = "none",
+ ram_block3a_0.port_b_address_clock = "clock1",
+ ram_block3a_0.port_b_address_width = 11,
+ ram_block3a_0.port_b_data_out_clear = "none",
+ ram_block3a_0.port_b_data_out_clock = "none",
+ ram_block3a_0.port_b_data_width = 1,
+ ram_block3a_0.port_b_first_address = 0,
+ ram_block3a_0.port_b_first_bit_number = 0,
+ ram_block3a_0.port_b_last_address = 2047,
+ ram_block3a_0.port_b_logical_ram_depth = 2048,
+ ram_block3a_0.port_b_logical_ram_width = 16,
+ ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_0.ram_block_type = "auto",
+ ram_block3a_0.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_1
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[1]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_1portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_1.connectivity_checking = "OFF",
+ ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_1.operation_mode = "dual_port",
+ ram_block3a_1.port_a_address_width = 11,
+ ram_block3a_1.port_a_data_width = 1,
+ ram_block3a_1.port_a_first_address = 0,
+ ram_block3a_1.port_a_first_bit_number = 1,
+ ram_block3a_1.port_a_last_address = 2047,
+ ram_block3a_1.port_a_logical_ram_depth = 2048,
+ ram_block3a_1.port_a_logical_ram_width = 16,
+ ram_block3a_1.port_b_address_clear = "none",
+ ram_block3a_1.port_b_address_clock = "clock1",
+ ram_block3a_1.port_b_address_width = 11,
+ ram_block3a_1.port_b_data_out_clear = "none",
+ ram_block3a_1.port_b_data_out_clock = "none",
+ ram_block3a_1.port_b_data_width = 1,
+ ram_block3a_1.port_b_first_address = 0,
+ ram_block3a_1.port_b_first_bit_number = 1,
+ ram_block3a_1.port_b_last_address = 2047,
+ ram_block3a_1.port_b_logical_ram_depth = 2048,
+ ram_block3a_1.port_b_logical_ram_width = 16,
+ ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_1.ram_block_type = "auto",
+ ram_block3a_1.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_2
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[2]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_2portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_2.connectivity_checking = "OFF",
+ ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_2.operation_mode = "dual_port",
+ ram_block3a_2.port_a_address_width = 11,
+ ram_block3a_2.port_a_data_width = 1,
+ ram_block3a_2.port_a_first_address = 0,
+ ram_block3a_2.port_a_first_bit_number = 2,
+ ram_block3a_2.port_a_last_address = 2047,
+ ram_block3a_2.port_a_logical_ram_depth = 2048,
+ ram_block3a_2.port_a_logical_ram_width = 16,
+ ram_block3a_2.port_b_address_clear = "none",
+ ram_block3a_2.port_b_address_clock = "clock1",
+ ram_block3a_2.port_b_address_width = 11,
+ ram_block3a_2.port_b_data_out_clear = "none",
+ ram_block3a_2.port_b_data_out_clock = "none",
+ ram_block3a_2.port_b_data_width = 1,
+ ram_block3a_2.port_b_first_address = 0,
+ ram_block3a_2.port_b_first_bit_number = 2,
+ ram_block3a_2.port_b_last_address = 2047,
+ ram_block3a_2.port_b_logical_ram_depth = 2048,
+ ram_block3a_2.port_b_logical_ram_width = 16,
+ ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_2.ram_block_type = "auto",
+ ram_block3a_2.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_3
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[3]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_3portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_3.connectivity_checking = "OFF",
+ ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_3.operation_mode = "dual_port",
+ ram_block3a_3.port_a_address_width = 11,
+ ram_block3a_3.port_a_data_width = 1,
+ ram_block3a_3.port_a_first_address = 0,
+ ram_block3a_3.port_a_first_bit_number = 3,
+ ram_block3a_3.port_a_last_address = 2047,
+ ram_block3a_3.port_a_logical_ram_depth = 2048,
+ ram_block3a_3.port_a_logical_ram_width = 16,
+ ram_block3a_3.port_b_address_clear = "none",
+ ram_block3a_3.port_b_address_clock = "clock1",
+ ram_block3a_3.port_b_address_width = 11,
+ ram_block3a_3.port_b_data_out_clear = "none",
+ ram_block3a_3.port_b_data_out_clock = "none",
+ ram_block3a_3.port_b_data_width = 1,
+ ram_block3a_3.port_b_first_address = 0,
+ ram_block3a_3.port_b_first_bit_number = 3,
+ ram_block3a_3.port_b_last_address = 2047,
+ ram_block3a_3.port_b_logical_ram_depth = 2048,
+ ram_block3a_3.port_b_logical_ram_width = 16,
+ ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_3.ram_block_type = "auto",
+ ram_block3a_3.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_4
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[4]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_4portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_4.connectivity_checking = "OFF",
+ ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_4.operation_mode = "dual_port",
+ ram_block3a_4.port_a_address_width = 11,
+ ram_block3a_4.port_a_data_width = 1,
+ ram_block3a_4.port_a_first_address = 0,
+ ram_block3a_4.port_a_first_bit_number = 4,
+ ram_block3a_4.port_a_last_address = 2047,
+ ram_block3a_4.port_a_logical_ram_depth = 2048,
+ ram_block3a_4.port_a_logical_ram_width = 16,
+ ram_block3a_4.port_b_address_clear = "none",
+ ram_block3a_4.port_b_address_clock = "clock1",
+ ram_block3a_4.port_b_address_width = 11,
+ ram_block3a_4.port_b_data_out_clear = "none",
+ ram_block3a_4.port_b_data_out_clock = "none",
+ ram_block3a_4.port_b_data_width = 1,
+ ram_block3a_4.port_b_first_address = 0,
+ ram_block3a_4.port_b_first_bit_number = 4,
+ ram_block3a_4.port_b_last_address = 2047,
+ ram_block3a_4.port_b_logical_ram_depth = 2048,
+ ram_block3a_4.port_b_logical_ram_width = 16,
+ ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_4.ram_block_type = "auto",
+ ram_block3a_4.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_5
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[5]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_5portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_5.connectivity_checking = "OFF",
+ ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_5.operation_mode = "dual_port",
+ ram_block3a_5.port_a_address_width = 11,
+ ram_block3a_5.port_a_data_width = 1,
+ ram_block3a_5.port_a_first_address = 0,
+ ram_block3a_5.port_a_first_bit_number = 5,
+ ram_block3a_5.port_a_last_address = 2047,
+ ram_block3a_5.port_a_logical_ram_depth = 2048,
+ ram_block3a_5.port_a_logical_ram_width = 16,
+ ram_block3a_5.port_b_address_clear = "none",
+ ram_block3a_5.port_b_address_clock = "clock1",
+ ram_block3a_5.port_b_address_width = 11,
+ ram_block3a_5.port_b_data_out_clear = "none",
+ ram_block3a_5.port_b_data_out_clock = "none",
+ ram_block3a_5.port_b_data_width = 1,
+ ram_block3a_5.port_b_first_address = 0,
+ ram_block3a_5.port_b_first_bit_number = 5,
+ ram_block3a_5.port_b_last_address = 2047,
+ ram_block3a_5.port_b_logical_ram_depth = 2048,
+ ram_block3a_5.port_b_logical_ram_width = 16,
+ ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_5.ram_block_type = "auto",
+ ram_block3a_5.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_6
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[6]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_6portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_6.connectivity_checking = "OFF",
+ ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_6.operation_mode = "dual_port",
+ ram_block3a_6.port_a_address_width = 11,
+ ram_block3a_6.port_a_data_width = 1,
+ ram_block3a_6.port_a_first_address = 0,
+ ram_block3a_6.port_a_first_bit_number = 6,
+ ram_block3a_6.port_a_last_address = 2047,
+ ram_block3a_6.port_a_logical_ram_depth = 2048,
+ ram_block3a_6.port_a_logical_ram_width = 16,
+ ram_block3a_6.port_b_address_clear = "none",
+ ram_block3a_6.port_b_address_clock = "clock1",
+ ram_block3a_6.port_b_address_width = 11,
+ ram_block3a_6.port_b_data_out_clear = "none",
+ ram_block3a_6.port_b_data_out_clock = "none",
+ ram_block3a_6.port_b_data_width = 1,
+ ram_block3a_6.port_b_first_address = 0,
+ ram_block3a_6.port_b_first_bit_number = 6,
+ ram_block3a_6.port_b_last_address = 2047,
+ ram_block3a_6.port_b_logical_ram_depth = 2048,
+ ram_block3a_6.port_b_logical_ram_width = 16,
+ ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_6.ram_block_type = "auto",
+ ram_block3a_6.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_7
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[7]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_7portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_7.connectivity_checking = "OFF",
+ ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_7.operation_mode = "dual_port",
+ ram_block3a_7.port_a_address_width = 11,
+ ram_block3a_7.port_a_data_width = 1,
+ ram_block3a_7.port_a_first_address = 0,
+ ram_block3a_7.port_a_first_bit_number = 7,
+ ram_block3a_7.port_a_last_address = 2047,
+ ram_block3a_7.port_a_logical_ram_depth = 2048,
+ ram_block3a_7.port_a_logical_ram_width = 16,
+ ram_block3a_7.port_b_address_clear = "none",
+ ram_block3a_7.port_b_address_clock = "clock1",
+ ram_block3a_7.port_b_address_width = 11,
+ ram_block3a_7.port_b_data_out_clear = "none",
+ ram_block3a_7.port_b_data_out_clock = "none",
+ ram_block3a_7.port_b_data_width = 1,
+ ram_block3a_7.port_b_first_address = 0,
+ ram_block3a_7.port_b_first_bit_number = 7,
+ ram_block3a_7.port_b_last_address = 2047,
+ ram_block3a_7.port_b_logical_ram_depth = 2048,
+ ram_block3a_7.port_b_logical_ram_width = 16,
+ ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_7.ram_block_type = "auto",
+ ram_block3a_7.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_8
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[8]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_8portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_8.connectivity_checking = "OFF",
+ ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_8.operation_mode = "dual_port",
+ ram_block3a_8.port_a_address_width = 11,
+ ram_block3a_8.port_a_data_width = 1,
+ ram_block3a_8.port_a_first_address = 0,
+ ram_block3a_8.port_a_first_bit_number = 8,
+ ram_block3a_8.port_a_last_address = 2047,
+ ram_block3a_8.port_a_logical_ram_depth = 2048,
+ ram_block3a_8.port_a_logical_ram_width = 16,
+ ram_block3a_8.port_b_address_clear = "none",
+ ram_block3a_8.port_b_address_clock = "clock1",
+ ram_block3a_8.port_b_address_width = 11,
+ ram_block3a_8.port_b_data_out_clear = "none",
+ ram_block3a_8.port_b_data_out_clock = "none",
+ ram_block3a_8.port_b_data_width = 1,
+ ram_block3a_8.port_b_first_address = 0,
+ ram_block3a_8.port_b_first_bit_number = 8,
+ ram_block3a_8.port_b_last_address = 2047,
+ ram_block3a_8.port_b_logical_ram_depth = 2048,
+ ram_block3a_8.port_b_logical_ram_width = 16,
+ ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_8.ram_block_type = "auto",
+ ram_block3a_8.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_9
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[9]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_9portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_9.connectivity_checking = "OFF",
+ ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_9.operation_mode = "dual_port",
+ ram_block3a_9.port_a_address_width = 11,
+ ram_block3a_9.port_a_data_width = 1,
+ ram_block3a_9.port_a_first_address = 0,
+ ram_block3a_9.port_a_first_bit_number = 9,
+ ram_block3a_9.port_a_last_address = 2047,
+ ram_block3a_9.port_a_logical_ram_depth = 2048,
+ ram_block3a_9.port_a_logical_ram_width = 16,
+ ram_block3a_9.port_b_address_clear = "none",
+ ram_block3a_9.port_b_address_clock = "clock1",
+ ram_block3a_9.port_b_address_width = 11,
+ ram_block3a_9.port_b_data_out_clear = "none",
+ ram_block3a_9.port_b_data_out_clock = "none",
+ ram_block3a_9.port_b_data_width = 1,
+ ram_block3a_9.port_b_first_address = 0,
+ ram_block3a_9.port_b_first_bit_number = 9,
+ ram_block3a_9.port_b_last_address = 2047,
+ ram_block3a_9.port_b_logical_ram_depth = 2048,
+ ram_block3a_9.port_b_logical_ram_width = 16,
+ ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_9.ram_block_type = "auto",
+ ram_block3a_9.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_10
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[10]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_10portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_10.connectivity_checking = "OFF",
+ ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_10.operation_mode = "dual_port",
+ ram_block3a_10.port_a_address_width = 11,
+ ram_block3a_10.port_a_data_width = 1,
+ ram_block3a_10.port_a_first_address = 0,
+ ram_block3a_10.port_a_first_bit_number = 10,
+ ram_block3a_10.port_a_last_address = 2047,
+ ram_block3a_10.port_a_logical_ram_depth = 2048,
+ ram_block3a_10.port_a_logical_ram_width = 16,
+ ram_block3a_10.port_b_address_clear = "none",
+ ram_block3a_10.port_b_address_clock = "clock1",
+ ram_block3a_10.port_b_address_width = 11,
+ ram_block3a_10.port_b_data_out_clear = "none",
+ ram_block3a_10.port_b_data_out_clock = "none",
+ ram_block3a_10.port_b_data_width = 1,
+ ram_block3a_10.port_b_first_address = 0,
+ ram_block3a_10.port_b_first_bit_number = 10,
+ ram_block3a_10.port_b_last_address = 2047,
+ ram_block3a_10.port_b_logical_ram_depth = 2048,
+ ram_block3a_10.port_b_logical_ram_width = 16,
+ ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_10.ram_block_type = "auto",
+ ram_block3a_10.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_11
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[11]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_11portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_11.connectivity_checking = "OFF",
+ ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_11.operation_mode = "dual_port",
+ ram_block3a_11.port_a_address_width = 11,
+ ram_block3a_11.port_a_data_width = 1,
+ ram_block3a_11.port_a_first_address = 0,
+ ram_block3a_11.port_a_first_bit_number = 11,
+ ram_block3a_11.port_a_last_address = 2047,
+ ram_block3a_11.port_a_logical_ram_depth = 2048,
+ ram_block3a_11.port_a_logical_ram_width = 16,
+ ram_block3a_11.port_b_address_clear = "none",
+ ram_block3a_11.port_b_address_clock = "clock1",
+ ram_block3a_11.port_b_address_width = 11,
+ ram_block3a_11.port_b_data_out_clear = "none",
+ ram_block3a_11.port_b_data_out_clock = "none",
+ ram_block3a_11.port_b_data_width = 1,
+ ram_block3a_11.port_b_first_address = 0,
+ ram_block3a_11.port_b_first_bit_number = 11,
+ ram_block3a_11.port_b_last_address = 2047,
+ ram_block3a_11.port_b_logical_ram_depth = 2048,
+ ram_block3a_11.port_b_logical_ram_width = 16,
+ ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_11.ram_block_type = "auto",
+ ram_block3a_11.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_12
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[12]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_12portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_12.connectivity_checking = "OFF",
+ ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_12.operation_mode = "dual_port",
+ ram_block3a_12.port_a_address_width = 11,
+ ram_block3a_12.port_a_data_width = 1,
+ ram_block3a_12.port_a_first_address = 0,
+ ram_block3a_12.port_a_first_bit_number = 12,
+ ram_block3a_12.port_a_last_address = 2047,
+ ram_block3a_12.port_a_logical_ram_depth = 2048,
+ ram_block3a_12.port_a_logical_ram_width = 16,
+ ram_block3a_12.port_b_address_clear = "none",
+ ram_block3a_12.port_b_address_clock = "clock1",
+ ram_block3a_12.port_b_address_width = 11,
+ ram_block3a_12.port_b_data_out_clear = "none",
+ ram_block3a_12.port_b_data_out_clock = "none",
+ ram_block3a_12.port_b_data_width = 1,
+ ram_block3a_12.port_b_first_address = 0,
+ ram_block3a_12.port_b_first_bit_number = 12,
+ ram_block3a_12.port_b_last_address = 2047,
+ ram_block3a_12.port_b_logical_ram_depth = 2048,
+ ram_block3a_12.port_b_logical_ram_width = 16,
+ ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_12.ram_block_type = "auto",
+ ram_block3a_12.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_13
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[13]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_13portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_13.connectivity_checking = "OFF",
+ ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_13.operation_mode = "dual_port",
+ ram_block3a_13.port_a_address_width = 11,
+ ram_block3a_13.port_a_data_width = 1,
+ ram_block3a_13.port_a_first_address = 0,
+ ram_block3a_13.port_a_first_bit_number = 13,
+ ram_block3a_13.port_a_last_address = 2047,
+ ram_block3a_13.port_a_logical_ram_depth = 2048,
+ ram_block3a_13.port_a_logical_ram_width = 16,
+ ram_block3a_13.port_b_address_clear = "none",
+ ram_block3a_13.port_b_address_clock = "clock1",
+ ram_block3a_13.port_b_address_width = 11,
+ ram_block3a_13.port_b_data_out_clear = "none",
+ ram_block3a_13.port_b_data_out_clock = "none",
+ ram_block3a_13.port_b_data_width = 1,
+ ram_block3a_13.port_b_first_address = 0,
+ ram_block3a_13.port_b_first_bit_number = 13,
+ ram_block3a_13.port_b_last_address = 2047,
+ ram_block3a_13.port_b_logical_ram_depth = 2048,
+ ram_block3a_13.port_b_logical_ram_width = 16,
+ ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_13.ram_block_type = "auto",
+ ram_block3a_13.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_14
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[14]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_14portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_14.connectivity_checking = "OFF",
+ ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_14.operation_mode = "dual_port",
+ ram_block3a_14.port_a_address_width = 11,
+ ram_block3a_14.port_a_data_width = 1,
+ ram_block3a_14.port_a_first_address = 0,
+ ram_block3a_14.port_a_first_bit_number = 14,
+ ram_block3a_14.port_a_last_address = 2047,
+ ram_block3a_14.port_a_logical_ram_depth = 2048,
+ ram_block3a_14.port_a_logical_ram_width = 16,
+ ram_block3a_14.port_b_address_clear = "none",
+ ram_block3a_14.port_b_address_clock = "clock1",
+ ram_block3a_14.port_b_address_width = 11,
+ ram_block3a_14.port_b_data_out_clear = "none",
+ ram_block3a_14.port_b_data_out_clock = "none",
+ ram_block3a_14.port_b_data_width = 1,
+ ram_block3a_14.port_b_first_address = 0,
+ ram_block3a_14.port_b_first_bit_number = 14,
+ ram_block3a_14.port_b_last_address = 2047,
+ ram_block3a_14.port_b_logical_ram_depth = 2048,
+ ram_block3a_14.port_b_logical_ram_width = 16,
+ ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_14.ram_block_type = "auto",
+ ram_block3a_14.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_15
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[10:0]}),
+ .portadatain({data_a[15]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[10:0]}),
+ .portbdataout(wire_ram_block3a_15portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_15.connectivity_checking = "OFF",
+ ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_15.operation_mode = "dual_port",
+ ram_block3a_15.port_a_address_width = 11,
+ ram_block3a_15.port_a_data_width = 1,
+ ram_block3a_15.port_a_first_address = 0,
+ ram_block3a_15.port_a_first_bit_number = 15,
+ ram_block3a_15.port_a_last_address = 2047,
+ ram_block3a_15.port_a_logical_ram_depth = 2048,
+ ram_block3a_15.port_a_logical_ram_width = 16,
+ ram_block3a_15.port_b_address_clear = "none",
+ ram_block3a_15.port_b_address_clock = "clock1",
+ ram_block3a_15.port_b_address_width = 11,
+ ram_block3a_15.port_b_data_out_clear = "none",
+ ram_block3a_15.port_b_data_out_clock = "none",
+ ram_block3a_15.port_b_data_width = 1,
+ ram_block3a_15.port_b_first_address = 0,
+ ram_block3a_15.port_b_first_bit_number = 15,
+ ram_block3a_15.port_b_last_address = 2047,
+ ram_block3a_15.port_b_logical_ram_depth = 2048,
+ ram_block3a_15.port_b_logical_ram_width = 16,
+ ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_15.ram_block_type = "auto",
+ ram_block3a_15.lpm_type = "cyclone_ram_block";
+ assign
+ address_a_wire = address_a,
+ address_b_wire = address_b,
+ q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
+endmodule //fifo_2k_altsyncram_6pl
+
+
+//dffpipe DELAY=1 WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = lut 11
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_dffpipe_ab3
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [10:0] d;
+ output [10:0] q;
+
+ wire [10:0] wire_dffe4a_D;
+ reg [10:0] dffe4a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe4a[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
+ // synopsys translate_off
+ initial
+ dffe4a[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
+ // synopsys translate_off
+ initial
+ dffe4a[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
+ // synopsys translate_off
+ initial
+ dffe4a[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
+ // synopsys translate_off
+ initial
+ dffe4a[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
+ // synopsys translate_off
+ initial
+ dffe4a[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
+ // synopsys translate_off
+ initial
+ dffe4a[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
+ // synopsys translate_off
+ initial
+ dffe4a[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
+ // synopsys translate_off
+ initial
+ dffe4a[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
+ // synopsys translate_off
+ initial
+ dffe4a[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
+ // synopsys translate_off
+ initial
+ dffe4a[10:10] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
+ assign
+ wire_dffe4a_D = (d & {11{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe4a,
+ sclr = 1'b0;
+endmodule //fifo_2k_dffpipe_ab3
+
+
+//dffpipe WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+
+//dffpipe WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = lut 11
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_dffpipe_dm2
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [10:0] d;
+ output [10:0] q;
+
+ wire [10:0] wire_dffe6a_D;
+ reg [10:0] dffe6a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe6a[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
+ // synopsys translate_off
+ initial
+ dffe6a[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
+ // synopsys translate_off
+ initial
+ dffe6a[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
+ // synopsys translate_off
+ initial
+ dffe6a[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
+ // synopsys translate_off
+ initial
+ dffe6a[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
+ // synopsys translate_off
+ initial
+ dffe6a[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
+ // synopsys translate_off
+ initial
+ dffe6a[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
+ // synopsys translate_off
+ initial
+ dffe6a[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
+ // synopsys translate_off
+ initial
+ dffe6a[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
+ // synopsys translate_off
+ initial
+ dffe6a[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
+ // synopsys translate_off
+ initial
+ dffe6a[10:10] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
+ assign
+ wire_dffe6a_D = (d & {11{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe6a,
+ sclr = 1'b0;
+endmodule //fifo_2k_dffpipe_dm2
+
+//synthesis_resources = lut 11
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_alt_synch_pipe_dm2
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
+ input clock;
+ input clrn;
+ input [10:0] d;
+ output [10:0] q;
+
+ wire [10:0] wire_dffpipe5_q;
+
+ fifo_2k_dffpipe_dm2 dffpipe5
+ (
+ .clock(clock),
+ .clrn(clrn),
+ .d(d),
+ .q(wire_dffpipe5_q));
+ assign
+ q = wire_dffpipe5_q;
+endmodule //fifo_2k_alt_synch_pipe_dm2
+
+
+//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 11
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_add_sub_a18
+ (
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input [10:0] dataa;
+ input [10:0] datab;
+ output [10:0] result;
+
+ wire [10:0] wire_add_sub_cella_combout;
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [0:0] wire_add_sub_cella_7cout;
+ wire [0:0] wire_add_sub_cella_8cout;
+ wire [0:0] wire_add_sub_cella_9cout;
+ wire [10:0] wire_add_sub_cella_dataa;
+ wire [10:0] wire_add_sub_cella_datab;
+
+ cyclone_lcell add_sub_cella_0
+ (
+ .cin(1'b1),
+ .combout(wire_add_sub_cella_combout[0:0]),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "69b2",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_1
+ (
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .combout(wire_add_sub_cella_combout[1:1]),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "69b2",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_2
+ (
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .combout(wire_add_sub_cella_combout[2:2]),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "69b2",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_3
+ (
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .combout(wire_add_sub_cella_combout[3:3]),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "69b2",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_4
+ (
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .combout(wire_add_sub_cella_combout[4:4]),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "69b2",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_5
+ (
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .combout(wire_add_sub_cella_combout[5:5]),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "69b2",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_6
+ (
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .combout(wire_add_sub_cella_combout[6:6]),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "69b2",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_7
+ (
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .combout(wire_add_sub_cella_combout[7:7]),
+ .cout(wire_add_sub_cella_7cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "69b2",
+ add_sub_cella_7.operation_mode = "arithmetic",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_8
+ (
+ .cin(wire_add_sub_cella_7cout[0:0]),
+ .combout(wire_add_sub_cella_combout[8:8]),
+ .cout(wire_add_sub_cella_8cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[8:8]),
+ .datab(wire_add_sub_cella_datab[8:8]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_8.cin_used = "true",
+ add_sub_cella_8.lut_mask = "69b2",
+ add_sub_cella_8.operation_mode = "arithmetic",
+ add_sub_cella_8.sum_lutc_input = "cin",
+ add_sub_cella_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_9
+ (
+ .cin(wire_add_sub_cella_8cout[0:0]),
+ .combout(wire_add_sub_cella_combout[9:9]),
+ .cout(wire_add_sub_cella_9cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[9:9]),
+ .datab(wire_add_sub_cella_datab[9:9]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_9.cin_used = "true",
+ add_sub_cella_9.lut_mask = "69b2",
+ add_sub_cella_9.operation_mode = "arithmetic",
+ add_sub_cella_9.sum_lutc_input = "cin",
+ add_sub_cella_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_10
+ (
+ .cin(wire_add_sub_cella_9cout[0:0]),
+ .combout(wire_add_sub_cella_combout[10:10]),
+ .cout(),
+ .dataa(wire_add_sub_cella_dataa[10:10]),
+ .datab(wire_add_sub_cella_datab[10:10]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_10.cin_used = "true",
+ add_sub_cella_10.lut_mask = "6969",
+ add_sub_cella_10.operation_mode = "normal",
+ add_sub_cella_10.sum_lutc_input = "cin",
+ add_sub_cella_10.lpm_type = "cyclone_lcell";
+ assign
+ wire_add_sub_cella_dataa = dataa,
+ wire_add_sub_cella_datab = datab;
+ assign
+ result = wire_add_sub_cella_combout;
+endmodule //fifo_2k_add_sub_a18
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 97 M4K 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_2k_dcfifo_0cq
+ (
+ aclr,
+ data,
+ q,
+ rdclk,
+ rdempty,
+ rdreq,
+ rdusedw,
+ wrclk,
+ wrfull,
+ wrreq,
+ wrusedw) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
+ input aclr;
+ input [15:0] data;
+ output [15:0] q;
+ input rdclk;
+ output rdempty;
+ input rdreq;
+ output [10:0] rdusedw;
+ input wrclk;
+ output wrfull;
+ input wrreq;
+ output [10:0] wrusedw;
+
+ wire [10:0] wire_rdptr_g_gray2bin_bin;
+ wire [10:0] wire_rs_dgwp_gray2bin_bin;
+ wire [10:0] wire_wrptr_g_gray2bin_bin;
+ wire [10:0] wire_ws_dgrp_gray2bin_bin;
+ wire [10:0] wire_rdptr_g_q;
+ wire [10:0] wire_rdptr_g1p_q;
+ wire [10:0] wire_wrptr_g1p_q;
+ wire [15:0] wire_fifo_ram_q_b;
+ reg [10:0] delayed_wrptr_g;
+ reg [10:0] wrptr_g;
+ wire [10:0] wire_rs_brp_q;
+ wire [10:0] wire_rs_bwp_q;
+ wire [10:0] wire_rs_dgwp_q;
+ wire [10:0] wire_ws_brp_q;
+ wire [10:0] wire_ws_bwp_q;
+ wire [10:0] wire_ws_dgrp_q;
+ wire [10:0] wire_rdusedw_sub_result;
+ wire [10:0] wire_wrusedw_sub_result;
+ reg wire_rdempty_eq_comp_aeb_int;
+ wire wire_rdempty_eq_comp_aeb;
+ wire [10:0] wire_rdempty_eq_comp_dataa;
+ wire [10:0] wire_rdempty_eq_comp_datab;
+ reg wire_wrfull_eq_comp_aeb_int;
+ wire wire_wrfull_eq_comp_aeb;
+ wire [10:0] wire_wrfull_eq_comp_dataa;
+ wire [10:0] wire_wrfull_eq_comp_datab;
+ wire int_rdempty;
+ wire int_wrfull;
+ wire valid_rdreq;
+ wire valid_wrreq;
+
+ fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin
+ (
+ .bin(wire_rdptr_g_gray2bin_bin),
+ .gray(wire_rdptr_g_q));
+ fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin
+ (
+ .bin(wire_rs_dgwp_gray2bin_bin),
+ .gray(wire_rs_dgwp_q));
+ fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin
+ (
+ .bin(wire_wrptr_g_gray2bin_bin),
+ .gray(wrptr_g));
+ fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin
+ (
+ .bin(wire_ws_dgrp_gray2bin_bin),
+ .gray(wire_ws_dgrp_q));
+ fifo_2k_a_graycounter_726 rdptr_g
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rdreq),
+ .q(wire_rdptr_g_q));
+ fifo_2k_a_graycounter_2r6 rdptr_g1p
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rdreq),
+ .q(wire_rdptr_g1p_q));
+ fifo_2k_a_graycounter_2r6 wrptr_g1p
+ (
+ .aclr(aclr),
+ .clock(wrclk),
+ .cnt_en(valid_wrreq),
+ .q(wire_wrptr_g1p_q));
+ fifo_2k_altsyncram_6pl fifo_ram
+ (
+ .address_a(wrptr_g),
+ .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
+ .clock0(wrclk),
+ .clock1(rdclk),
+ .clocken1((valid_rdreq | int_rdempty)),
+ .data_a(data),
+ .q_b(wire_fifo_ram_q_b),
+ .wren_a(valid_wrreq));
+ // synopsys translate_off
+ initial
+ delayed_wrptr_g = 0;
+ // synopsys translate_on
+ always @ ( posedge wrclk or posedge aclr)
+ if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
+ else delayed_wrptr_g <= wrptr_g;
+ // synopsys translate_off
+ initial
+ wrptr_g = 0;
+ // synopsys translate_on
+ always @ ( posedge wrclk or posedge aclr)
+ if (aclr == 1'b1) wrptr_g <= 11'b0;
+ else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
+ fifo_2k_dffpipe_ab3 rs_brp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(wire_rdptr_g_gray2bin_bin),
+ .q(wire_rs_brp_q));
+ fifo_2k_dffpipe_ab3 rs_bwp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(wire_rs_dgwp_gray2bin_bin),
+ .q(wire_rs_bwp_q));
+ fifo_2k_alt_synch_pipe_dm2 rs_dgwp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(delayed_wrptr_g),
+ .q(wire_rs_dgwp_q));
+ fifo_2k_dffpipe_ab3 ws_brp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_ws_dgrp_gray2bin_bin),
+ .q(wire_ws_brp_q));
+ fifo_2k_dffpipe_ab3 ws_bwp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_wrptr_g_gray2bin_bin),
+ .q(wire_ws_bwp_q));
+ fifo_2k_alt_synch_pipe_dm2 ws_dgrp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_rdptr_g_q),
+ .q(wire_ws_dgrp_q));
+ fifo_2k_add_sub_a18 rdusedw_sub
+ (
+ .dataa(wire_rs_bwp_q),
+ .datab(wire_rs_brp_q),
+ .result(wire_rdusedw_sub_result));
+ fifo_2k_add_sub_a18 wrusedw_sub
+ (
+ .dataa(wire_ws_bwp_q),
+ .datab(wire_ws_brp_q),
+ .result(wire_wrusedw_sub_result));
+ always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
+ if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
+ begin
+ wire_rdempty_eq_comp_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_rdempty_eq_comp_aeb_int = 1'b0;
+ end
+ assign
+ wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
+ assign
+ wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
+ wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
+ always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
+ if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
+ begin
+ wire_wrfull_eq_comp_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_wrfull_eq_comp_aeb_int = 1'b0;
+ end
+ assign
+ wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
+ assign
+ wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
+ wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
+ assign
+ int_rdempty = wire_rdempty_eq_comp_aeb,
+ int_wrfull = wire_wrfull_eq_comp_aeb,
+ q = wire_fifo_ram_q_b,
+ rdempty = int_rdempty,
+ rdusedw = wire_rdusedw_sub_result,
+ valid_rdreq = rdreq,
+ valid_wrreq = wrreq,
+ wrfull = int_wrfull,
+ wrusedw = wire_wrusedw_sub_result;
+endmodule //fifo_2k_dcfifo_0cq
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_2k (
+ data,
+ wrreq,
+ rdreq,
+ rdclk,
+ wrclk,
+ aclr,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [15:0] q;
+ output rdempty;
+ output [10:0] rdusedw;
+ output wrfull;
+ output [10:0] wrusedw;
+
+ wire sub_wire0;
+ wire [10:0] sub_wire1;
+ wire sub_wire2;
+ wire [15:0] sub_wire3;
+ wire [10:0] sub_wire4;
+ wire rdempty = sub_wire0;
+ wire [10:0] wrusedw = sub_wire1[10:0];
+ wire wrfull = sub_wire2;
+ wire [15:0] q = sub_wire3[15:0];
+ wire [10:0] rdusedw = sub_wire4[10:0];
+
+ fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdempty (sub_wire0),
+ .wrusedw (sub_wire1),
+ .wrfull (sub_wire2),
+ .q (sub_wire3),
+ .rdusedw (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
diff --git a/megacells/fifo_2k_bb.v b/megacells/fifo_2k_bb.v
new file mode 100644
index 000000000..3fcc2a496
--- /dev/null
+++ b/megacells/fifo_2k_bb.v
@@ -0,0 +1,131 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_2k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_2k (
+ data,
+ wrreq,
+ rdreq,
+ rdclk,
+ wrclk,
+ aclr,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [15:0] q;
+ output rdempty;
+ output [10:0] rdusedw;
+ output wrfull;
+ output [10:0] wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
diff --git a/megacells/fifo_4k.v b/megacells/fifo_4k.v
new file mode 100644
index 000000000..a5ab46677
--- /dev/null
+++ b/megacells/fifo_4k.v
@@ -0,0 +1,3495 @@
+// megafunction wizard: %FIFO%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+
+//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
+
+//synthesis_resources =
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_a_gray2bin_9m4
+ (
+ bin,
+ gray) /* synthesis synthesis_clearbox=1 */;
+ output [11:0] bin;
+ input [11:0] gray;
+
+ wire xor0;
+ wire xor1;
+ wire xor10;
+ wire xor2;
+ wire xor3;
+ wire xor4;
+ wire xor5;
+ wire xor6;
+ wire xor7;
+ wire xor8;
+ wire xor9;
+
+ assign
+ bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+ xor0 = (gray[0] ^ xor1),
+ xor1 = (gray[1] ^ xor2),
+ xor10 = (gray[11] ^ gray[10]),
+ xor2 = (gray[2] ^ xor3),
+ xor3 = (gray[3] ^ xor4),
+ xor4 = (gray[4] ^ xor5),
+ xor5 = (gray[5] ^ xor6),
+ xor6 = (gray[6] ^ xor7),
+ xor7 = (gray[7] ^ xor8),
+ xor8 = (gray[8] ^ xor9),
+ xor9 = (gray[9] ^ xor10);
+endmodule //fifo_4k_a_gray2bin_9m4
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 13
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_a_graycounter_826
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [11:0] q;
+
+ wire [0:0] wire_countera_0cout;
+ wire [0:0] wire_countera_1cout;
+ wire [0:0] wire_countera_2cout;
+ wire [0:0] wire_countera_3cout;
+ wire [0:0] wire_countera_4cout;
+ wire [0:0] wire_countera_5cout;
+ wire [0:0] wire_countera_6cout;
+ wire [0:0] wire_countera_7cout;
+ wire [0:0] wire_countera_8cout;
+ wire [0:0] wire_countera_9cout;
+ wire [0:0] wire_countera_10cout;
+ wire [11:0] wire_countera_regout;
+ wire wire_parity_cout;
+ wire wire_parity_regout;
+ wire [11:0] power_modified_counter_values;
+ wire sclr;
+ wire updown;
+
+ cyclone_lcell countera_0
+ (
+ .aclr(aclr),
+ .cin(wire_parity_cout),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_0cout[0:0]),
+ .dataa(cnt_en),
+ .datab(wire_countera_regout[0:0]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[0:0]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_0.cin_used = "true",
+ countera_0.lut_mask = "c6a0",
+ countera_0.operation_mode = "arithmetic",
+ countera_0.sum_lutc_input = "cin",
+ countera_0.synch_mode = "on",
+ countera_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_1
+ (
+ .aclr(aclr),
+ .cin(wire_countera_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_1cout[0:0]),
+ .dataa(power_modified_counter_values[0]),
+ .datab(power_modified_counter_values[1]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[1:1]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_1.cin_used = "true",
+ countera_1.lut_mask = "6c50",
+ countera_1.operation_mode = "arithmetic",
+ countera_1.sum_lutc_input = "cin",
+ countera_1.synch_mode = "on",
+ countera_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_2
+ (
+ .aclr(aclr),
+ .cin(wire_countera_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_2cout[0:0]),
+ .dataa(power_modified_counter_values[1]),
+ .datab(power_modified_counter_values[2]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[2:2]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_2.cin_used = "true",
+ countera_2.lut_mask = "6c50",
+ countera_2.operation_mode = "arithmetic",
+ countera_2.sum_lutc_input = "cin",
+ countera_2.synch_mode = "on",
+ countera_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_3
+ (
+ .aclr(aclr),
+ .cin(wire_countera_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_3cout[0:0]),
+ .dataa(power_modified_counter_values[2]),
+ .datab(power_modified_counter_values[3]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[3:3]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_3.cin_used = "true",
+ countera_3.lut_mask = "6c50",
+ countera_3.operation_mode = "arithmetic",
+ countera_3.sum_lutc_input = "cin",
+ countera_3.synch_mode = "on",
+ countera_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_4
+ (
+ .aclr(aclr),
+ .cin(wire_countera_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_4cout[0:0]),
+ .dataa(power_modified_counter_values[3]),
+ .datab(power_modified_counter_values[4]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[4:4]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_4.cin_used = "true",
+ countera_4.lut_mask = "6c50",
+ countera_4.operation_mode = "arithmetic",
+ countera_4.sum_lutc_input = "cin",
+ countera_4.synch_mode = "on",
+ countera_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_5
+ (
+ .aclr(aclr),
+ .cin(wire_countera_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_5cout[0:0]),
+ .dataa(power_modified_counter_values[4]),
+ .datab(power_modified_counter_values[5]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[5:5]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_5.cin_used = "true",
+ countera_5.lut_mask = "6c50",
+ countera_5.operation_mode = "arithmetic",
+ countera_5.sum_lutc_input = "cin",
+ countera_5.synch_mode = "on",
+ countera_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_6
+ (
+ .aclr(aclr),
+ .cin(wire_countera_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_6cout[0:0]),
+ .dataa(power_modified_counter_values[5]),
+ .datab(power_modified_counter_values[6]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[6:6]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_6.cin_used = "true",
+ countera_6.lut_mask = "6c50",
+ countera_6.operation_mode = "arithmetic",
+ countera_6.sum_lutc_input = "cin",
+ countera_6.synch_mode = "on",
+ countera_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_7
+ (
+ .aclr(aclr),
+ .cin(wire_countera_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_7cout[0:0]),
+ .dataa(power_modified_counter_values[6]),
+ .datab(power_modified_counter_values[7]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[7:7]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_7.cin_used = "true",
+ countera_7.lut_mask = "6c50",
+ countera_7.operation_mode = "arithmetic",
+ countera_7.sum_lutc_input = "cin",
+ countera_7.synch_mode = "on",
+ countera_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_8
+ (
+ .aclr(aclr),
+ .cin(wire_countera_7cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_8cout[0:0]),
+ .dataa(power_modified_counter_values[7]),
+ .datab(power_modified_counter_values[8]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[8:8]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_8.cin_used = "true",
+ countera_8.lut_mask = "6c50",
+ countera_8.operation_mode = "arithmetic",
+ countera_8.sum_lutc_input = "cin",
+ countera_8.synch_mode = "on",
+ countera_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_9
+ (
+ .aclr(aclr),
+ .cin(wire_countera_8cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_9cout[0:0]),
+ .dataa(power_modified_counter_values[8]),
+ .datab(power_modified_counter_values[9]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[9:9]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_9.cin_used = "true",
+ countera_9.lut_mask = "6c50",
+ countera_9.operation_mode = "arithmetic",
+ countera_9.sum_lutc_input = "cin",
+ countera_9.synch_mode = "on",
+ countera_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_10
+ (
+ .aclr(aclr),
+ .cin(wire_countera_9cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_10cout[0:0]),
+ .dataa(power_modified_counter_values[9]),
+ .datab(power_modified_counter_values[10]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[10:10]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_10.cin_used = "true",
+ countera_10.lut_mask = "6c50",
+ countera_10.operation_mode = "arithmetic",
+ countera_10.sum_lutc_input = "cin",
+ countera_10.synch_mode = "on",
+ countera_10.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_11
+ (
+ .aclr(aclr),
+ .cin(wire_countera_10cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(power_modified_counter_values[11]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[11:11]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datab(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_11.cin_used = "true",
+ countera_11.lut_mask = "5a5a",
+ countera_11.operation_mode = "normal",
+ countera_11.sum_lutc_input = "cin",
+ countera_11.synch_mode = "on",
+ countera_11.lpm_type = "cyclone_lcell";
+ cyclone_lcell parity
+ (
+ .aclr(aclr),
+ .cin(updown),
+ .clk(clock),
+ .combout(),
+ .cout(wire_parity_cout),
+ .dataa(cnt_en),
+ .datab(wire_parity_regout),
+ .ena(1'b1),
+ .regout(wire_parity_regout),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ parity.cin_used = "true",
+ parity.lut_mask = "6682",
+ parity.operation_mode = "arithmetic",
+ parity.synch_mode = "on",
+ parity.lpm_type = "cyclone_lcell";
+ assign
+ power_modified_counter_values = {wire_countera_regout[11:0]},
+ q = power_modified_counter_values,
+ sclr = 1'b0,
+ updown = 1'b1;
+endmodule //fifo_4k_a_graycounter_826
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 13
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_a_graycounter_3r6
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [11:0] q;
+
+ wire [0:0] wire_countera_0cout;
+ wire [0:0] wire_countera_1cout;
+ wire [0:0] wire_countera_2cout;
+ wire [0:0] wire_countera_3cout;
+ wire [0:0] wire_countera_4cout;
+ wire [0:0] wire_countera_5cout;
+ wire [0:0] wire_countera_6cout;
+ wire [0:0] wire_countera_7cout;
+ wire [0:0] wire_countera_8cout;
+ wire [0:0] wire_countera_9cout;
+ wire [0:0] wire_countera_10cout;
+ wire [11:0] wire_countera_regout;
+ wire wire_parity_cout;
+ wire wire_parity_regout;
+ wire [11:0] power_modified_counter_values;
+ wire sclr;
+ wire updown;
+
+ cyclone_lcell countera_0
+ (
+ .aclr(aclr),
+ .cin(wire_parity_cout),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_0cout[0:0]),
+ .dataa(cnt_en),
+ .datab(wire_countera_regout[0:0]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[0:0]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_0.cin_used = "true",
+ countera_0.lut_mask = "c6a0",
+ countera_0.operation_mode = "arithmetic",
+ countera_0.sum_lutc_input = "cin",
+ countera_0.synch_mode = "on",
+ countera_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_1
+ (
+ .aclr(aclr),
+ .cin(wire_countera_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_1cout[0:0]),
+ .dataa(power_modified_counter_values[0]),
+ .datab(power_modified_counter_values[1]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[1:1]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_1.cin_used = "true",
+ countera_1.lut_mask = "6c50",
+ countera_1.operation_mode = "arithmetic",
+ countera_1.sum_lutc_input = "cin",
+ countera_1.synch_mode = "on",
+ countera_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_2
+ (
+ .aclr(aclr),
+ .cin(wire_countera_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_2cout[0:0]),
+ .dataa(power_modified_counter_values[1]),
+ .datab(power_modified_counter_values[2]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[2:2]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_2.cin_used = "true",
+ countera_2.lut_mask = "6c50",
+ countera_2.operation_mode = "arithmetic",
+ countera_2.sum_lutc_input = "cin",
+ countera_2.synch_mode = "on",
+ countera_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_3
+ (
+ .aclr(aclr),
+ .cin(wire_countera_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_3cout[0:0]),
+ .dataa(power_modified_counter_values[2]),
+ .datab(power_modified_counter_values[3]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[3:3]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_3.cin_used = "true",
+ countera_3.lut_mask = "6c50",
+ countera_3.operation_mode = "arithmetic",
+ countera_3.sum_lutc_input = "cin",
+ countera_3.synch_mode = "on",
+ countera_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_4
+ (
+ .aclr(aclr),
+ .cin(wire_countera_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_4cout[0:0]),
+ .dataa(power_modified_counter_values[3]),
+ .datab(power_modified_counter_values[4]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[4:4]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_4.cin_used = "true",
+ countera_4.lut_mask = "6c50",
+ countera_4.operation_mode = "arithmetic",
+ countera_4.sum_lutc_input = "cin",
+ countera_4.synch_mode = "on",
+ countera_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_5
+ (
+ .aclr(aclr),
+ .cin(wire_countera_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_5cout[0:0]),
+ .dataa(power_modified_counter_values[4]),
+ .datab(power_modified_counter_values[5]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[5:5]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_5.cin_used = "true",
+ countera_5.lut_mask = "6c50",
+ countera_5.operation_mode = "arithmetic",
+ countera_5.sum_lutc_input = "cin",
+ countera_5.synch_mode = "on",
+ countera_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_6
+ (
+ .aclr(aclr),
+ .cin(wire_countera_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_6cout[0:0]),
+ .dataa(power_modified_counter_values[5]),
+ .datab(power_modified_counter_values[6]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[6:6]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_6.cin_used = "true",
+ countera_6.lut_mask = "6c50",
+ countera_6.operation_mode = "arithmetic",
+ countera_6.sum_lutc_input = "cin",
+ countera_6.synch_mode = "on",
+ countera_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_7
+ (
+ .aclr(aclr),
+ .cin(wire_countera_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_7cout[0:0]),
+ .dataa(power_modified_counter_values[6]),
+ .datab(power_modified_counter_values[7]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[7:7]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_7.cin_used = "true",
+ countera_7.lut_mask = "6c50",
+ countera_7.operation_mode = "arithmetic",
+ countera_7.sum_lutc_input = "cin",
+ countera_7.synch_mode = "on",
+ countera_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_8
+ (
+ .aclr(aclr),
+ .cin(wire_countera_7cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_8cout[0:0]),
+ .dataa(power_modified_counter_values[7]),
+ .datab(power_modified_counter_values[8]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[8:8]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_8.cin_used = "true",
+ countera_8.lut_mask = "6c50",
+ countera_8.operation_mode = "arithmetic",
+ countera_8.sum_lutc_input = "cin",
+ countera_8.synch_mode = "on",
+ countera_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_9
+ (
+ .aclr(aclr),
+ .cin(wire_countera_8cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_9cout[0:0]),
+ .dataa(power_modified_counter_values[8]),
+ .datab(power_modified_counter_values[9]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[9:9]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_9.cin_used = "true",
+ countera_9.lut_mask = "6c50",
+ countera_9.operation_mode = "arithmetic",
+ countera_9.sum_lutc_input = "cin",
+ countera_9.synch_mode = "on",
+ countera_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_10
+ (
+ .aclr(aclr),
+ .cin(wire_countera_9cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_10cout[0:0]),
+ .dataa(power_modified_counter_values[9]),
+ .datab(power_modified_counter_values[10]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[10:10]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_10.cin_used = "true",
+ countera_10.lut_mask = "6c50",
+ countera_10.operation_mode = "arithmetic",
+ countera_10.sum_lutc_input = "cin",
+ countera_10.synch_mode = "on",
+ countera_10.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_11
+ (
+ .aclr(aclr),
+ .cin(wire_countera_10cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(power_modified_counter_values[11]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[11:11]),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datab(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_11.cin_used = "true",
+ countera_11.lut_mask = "5a5a",
+ countera_11.operation_mode = "normal",
+ countera_11.sum_lutc_input = "cin",
+ countera_11.synch_mode = "on",
+ countera_11.lpm_type = "cyclone_lcell";
+ cyclone_lcell parity
+ (
+ .aclr(aclr),
+ .cin(updown),
+ .clk(clock),
+ .combout(),
+ .cout(wire_parity_cout),
+ .dataa(cnt_en),
+ .datab((~ wire_parity_regout)),
+ .ena(1'b1),
+ .regout(wire_parity_regout),
+ .sclr(sclr)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ parity.cin_used = "true",
+ parity.lut_mask = "9982",
+ parity.operation_mode = "arithmetic",
+ parity.synch_mode = "on",
+ parity.lpm_type = "cyclone_lcell";
+ assign
+ power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
+ q = power_modified_counter_values,
+ sclr = 1'b0,
+ updown = 1'b1;
+endmodule //fifo_4k_a_graycounter_3r6
+
+
+//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
+//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = M4K 16
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_altsyncram_8pl
+ (
+ address_a,
+ address_b,
+ clock0,
+ clock1,
+ clocken1,
+ data_a,
+ q_b,
+ wren_a) /* synthesis synthesis_clearbox=1 */;
+ input [11:0] address_a;
+ input [11:0] address_b;
+ input clock0;
+ input clock1;
+ input clocken1;
+ input [15:0] data_a;
+ output [15:0] q_b;
+ input wren_a;
+
+ wire [0:0] wire_ram_block3a_0portbdataout;
+ wire [0:0] wire_ram_block3a_1portbdataout;
+ wire [0:0] wire_ram_block3a_2portbdataout;
+ wire [0:0] wire_ram_block3a_3portbdataout;
+ wire [0:0] wire_ram_block3a_4portbdataout;
+ wire [0:0] wire_ram_block3a_5portbdataout;
+ wire [0:0] wire_ram_block3a_6portbdataout;
+ wire [0:0] wire_ram_block3a_7portbdataout;
+ wire [0:0] wire_ram_block3a_8portbdataout;
+ wire [0:0] wire_ram_block3a_9portbdataout;
+ wire [0:0] wire_ram_block3a_10portbdataout;
+ wire [0:0] wire_ram_block3a_11portbdataout;
+ wire [0:0] wire_ram_block3a_12portbdataout;
+ wire [0:0] wire_ram_block3a_13portbdataout;
+ wire [0:0] wire_ram_block3a_14portbdataout;
+ wire [0:0] wire_ram_block3a_15portbdataout;
+ wire [11:0] address_a_wire;
+ wire [11:0] address_b_wire;
+
+ cyclone_ram_block ram_block3a_0
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[0]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_0portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_0.connectivity_checking = "OFF",
+ ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_0.operation_mode = "dual_port",
+ ram_block3a_0.port_a_address_width = 12,
+ ram_block3a_0.port_a_data_width = 1,
+ ram_block3a_0.port_a_first_address = 0,
+ ram_block3a_0.port_a_first_bit_number = 0,
+ ram_block3a_0.port_a_last_address = 4095,
+ ram_block3a_0.port_a_logical_ram_depth = 4096,
+ ram_block3a_0.port_a_logical_ram_width = 16,
+ ram_block3a_0.port_b_address_clear = "none",
+ ram_block3a_0.port_b_address_clock = "clock1",
+ ram_block3a_0.port_b_address_width = 12,
+ ram_block3a_0.port_b_data_out_clear = "none",
+ ram_block3a_0.port_b_data_out_clock = "none",
+ ram_block3a_0.port_b_data_width = 1,
+ ram_block3a_0.port_b_first_address = 0,
+ ram_block3a_0.port_b_first_bit_number = 0,
+ ram_block3a_0.port_b_last_address = 4095,
+ ram_block3a_0.port_b_logical_ram_depth = 4096,
+ ram_block3a_0.port_b_logical_ram_width = 16,
+ ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_0.ram_block_type = "auto",
+ ram_block3a_0.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_1
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[1]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_1portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_1.connectivity_checking = "OFF",
+ ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_1.operation_mode = "dual_port",
+ ram_block3a_1.port_a_address_width = 12,
+ ram_block3a_1.port_a_data_width = 1,
+ ram_block3a_1.port_a_first_address = 0,
+ ram_block3a_1.port_a_first_bit_number = 1,
+ ram_block3a_1.port_a_last_address = 4095,
+ ram_block3a_1.port_a_logical_ram_depth = 4096,
+ ram_block3a_1.port_a_logical_ram_width = 16,
+ ram_block3a_1.port_b_address_clear = "none",
+ ram_block3a_1.port_b_address_clock = "clock1",
+ ram_block3a_1.port_b_address_width = 12,
+ ram_block3a_1.port_b_data_out_clear = "none",
+ ram_block3a_1.port_b_data_out_clock = "none",
+ ram_block3a_1.port_b_data_width = 1,
+ ram_block3a_1.port_b_first_address = 0,
+ ram_block3a_1.port_b_first_bit_number = 1,
+ ram_block3a_1.port_b_last_address = 4095,
+ ram_block3a_1.port_b_logical_ram_depth = 4096,
+ ram_block3a_1.port_b_logical_ram_width = 16,
+ ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_1.ram_block_type = "auto",
+ ram_block3a_1.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_2
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[2]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_2portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_2.connectivity_checking = "OFF",
+ ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_2.operation_mode = "dual_port",
+ ram_block3a_2.port_a_address_width = 12,
+ ram_block3a_2.port_a_data_width = 1,
+ ram_block3a_2.port_a_first_address = 0,
+ ram_block3a_2.port_a_first_bit_number = 2,
+ ram_block3a_2.port_a_last_address = 4095,
+ ram_block3a_2.port_a_logical_ram_depth = 4096,
+ ram_block3a_2.port_a_logical_ram_width = 16,
+ ram_block3a_2.port_b_address_clear = "none",
+ ram_block3a_2.port_b_address_clock = "clock1",
+ ram_block3a_2.port_b_address_width = 12,
+ ram_block3a_2.port_b_data_out_clear = "none",
+ ram_block3a_2.port_b_data_out_clock = "none",
+ ram_block3a_2.port_b_data_width = 1,
+ ram_block3a_2.port_b_first_address = 0,
+ ram_block3a_2.port_b_first_bit_number = 2,
+ ram_block3a_2.port_b_last_address = 4095,
+ ram_block3a_2.port_b_logical_ram_depth = 4096,
+ ram_block3a_2.port_b_logical_ram_width = 16,
+ ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_2.ram_block_type = "auto",
+ ram_block3a_2.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_3
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[3]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_3portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_3.connectivity_checking = "OFF",
+ ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_3.operation_mode = "dual_port",
+ ram_block3a_3.port_a_address_width = 12,
+ ram_block3a_3.port_a_data_width = 1,
+ ram_block3a_3.port_a_first_address = 0,
+ ram_block3a_3.port_a_first_bit_number = 3,
+ ram_block3a_3.port_a_last_address = 4095,
+ ram_block3a_3.port_a_logical_ram_depth = 4096,
+ ram_block3a_3.port_a_logical_ram_width = 16,
+ ram_block3a_3.port_b_address_clear = "none",
+ ram_block3a_3.port_b_address_clock = "clock1",
+ ram_block3a_3.port_b_address_width = 12,
+ ram_block3a_3.port_b_data_out_clear = "none",
+ ram_block3a_3.port_b_data_out_clock = "none",
+ ram_block3a_3.port_b_data_width = 1,
+ ram_block3a_3.port_b_first_address = 0,
+ ram_block3a_3.port_b_first_bit_number = 3,
+ ram_block3a_3.port_b_last_address = 4095,
+ ram_block3a_3.port_b_logical_ram_depth = 4096,
+ ram_block3a_3.port_b_logical_ram_width = 16,
+ ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_3.ram_block_type = "auto",
+ ram_block3a_3.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_4
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[4]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_4portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_4.connectivity_checking = "OFF",
+ ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_4.operation_mode = "dual_port",
+ ram_block3a_4.port_a_address_width = 12,
+ ram_block3a_4.port_a_data_width = 1,
+ ram_block3a_4.port_a_first_address = 0,
+ ram_block3a_4.port_a_first_bit_number = 4,
+ ram_block3a_4.port_a_last_address = 4095,
+ ram_block3a_4.port_a_logical_ram_depth = 4096,
+ ram_block3a_4.port_a_logical_ram_width = 16,
+ ram_block3a_4.port_b_address_clear = "none",
+ ram_block3a_4.port_b_address_clock = "clock1",
+ ram_block3a_4.port_b_address_width = 12,
+ ram_block3a_4.port_b_data_out_clear = "none",
+ ram_block3a_4.port_b_data_out_clock = "none",
+ ram_block3a_4.port_b_data_width = 1,
+ ram_block3a_4.port_b_first_address = 0,
+ ram_block3a_4.port_b_first_bit_number = 4,
+ ram_block3a_4.port_b_last_address = 4095,
+ ram_block3a_4.port_b_logical_ram_depth = 4096,
+ ram_block3a_4.port_b_logical_ram_width = 16,
+ ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_4.ram_block_type = "auto",
+ ram_block3a_4.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_5
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[5]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_5portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_5.connectivity_checking = "OFF",
+ ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_5.operation_mode = "dual_port",
+ ram_block3a_5.port_a_address_width = 12,
+ ram_block3a_5.port_a_data_width = 1,
+ ram_block3a_5.port_a_first_address = 0,
+ ram_block3a_5.port_a_first_bit_number = 5,
+ ram_block3a_5.port_a_last_address = 4095,
+ ram_block3a_5.port_a_logical_ram_depth = 4096,
+ ram_block3a_5.port_a_logical_ram_width = 16,
+ ram_block3a_5.port_b_address_clear = "none",
+ ram_block3a_5.port_b_address_clock = "clock1",
+ ram_block3a_5.port_b_address_width = 12,
+ ram_block3a_5.port_b_data_out_clear = "none",
+ ram_block3a_5.port_b_data_out_clock = "none",
+ ram_block3a_5.port_b_data_width = 1,
+ ram_block3a_5.port_b_first_address = 0,
+ ram_block3a_5.port_b_first_bit_number = 5,
+ ram_block3a_5.port_b_last_address = 4095,
+ ram_block3a_5.port_b_logical_ram_depth = 4096,
+ ram_block3a_5.port_b_logical_ram_width = 16,
+ ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_5.ram_block_type = "auto",
+ ram_block3a_5.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_6
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[6]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_6portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_6.connectivity_checking = "OFF",
+ ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_6.operation_mode = "dual_port",
+ ram_block3a_6.port_a_address_width = 12,
+ ram_block3a_6.port_a_data_width = 1,
+ ram_block3a_6.port_a_first_address = 0,
+ ram_block3a_6.port_a_first_bit_number = 6,
+ ram_block3a_6.port_a_last_address = 4095,
+ ram_block3a_6.port_a_logical_ram_depth = 4096,
+ ram_block3a_6.port_a_logical_ram_width = 16,
+ ram_block3a_6.port_b_address_clear = "none",
+ ram_block3a_6.port_b_address_clock = "clock1",
+ ram_block3a_6.port_b_address_width = 12,
+ ram_block3a_6.port_b_data_out_clear = "none",
+ ram_block3a_6.port_b_data_out_clock = "none",
+ ram_block3a_6.port_b_data_width = 1,
+ ram_block3a_6.port_b_first_address = 0,
+ ram_block3a_6.port_b_first_bit_number = 6,
+ ram_block3a_6.port_b_last_address = 4095,
+ ram_block3a_6.port_b_logical_ram_depth = 4096,
+ ram_block3a_6.port_b_logical_ram_width = 16,
+ ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_6.ram_block_type = "auto",
+ ram_block3a_6.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_7
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[7]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_7portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_7.connectivity_checking = "OFF",
+ ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_7.operation_mode = "dual_port",
+ ram_block3a_7.port_a_address_width = 12,
+ ram_block3a_7.port_a_data_width = 1,
+ ram_block3a_7.port_a_first_address = 0,
+ ram_block3a_7.port_a_first_bit_number = 7,
+ ram_block3a_7.port_a_last_address = 4095,
+ ram_block3a_7.port_a_logical_ram_depth = 4096,
+ ram_block3a_7.port_a_logical_ram_width = 16,
+ ram_block3a_7.port_b_address_clear = "none",
+ ram_block3a_7.port_b_address_clock = "clock1",
+ ram_block3a_7.port_b_address_width = 12,
+ ram_block3a_7.port_b_data_out_clear = "none",
+ ram_block3a_7.port_b_data_out_clock = "none",
+ ram_block3a_7.port_b_data_width = 1,
+ ram_block3a_7.port_b_first_address = 0,
+ ram_block3a_7.port_b_first_bit_number = 7,
+ ram_block3a_7.port_b_last_address = 4095,
+ ram_block3a_7.port_b_logical_ram_depth = 4096,
+ ram_block3a_7.port_b_logical_ram_width = 16,
+ ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_7.ram_block_type = "auto",
+ ram_block3a_7.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_8
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[8]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_8portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_8.connectivity_checking = "OFF",
+ ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_8.operation_mode = "dual_port",
+ ram_block3a_8.port_a_address_width = 12,
+ ram_block3a_8.port_a_data_width = 1,
+ ram_block3a_8.port_a_first_address = 0,
+ ram_block3a_8.port_a_first_bit_number = 8,
+ ram_block3a_8.port_a_last_address = 4095,
+ ram_block3a_8.port_a_logical_ram_depth = 4096,
+ ram_block3a_8.port_a_logical_ram_width = 16,
+ ram_block3a_8.port_b_address_clear = "none",
+ ram_block3a_8.port_b_address_clock = "clock1",
+ ram_block3a_8.port_b_address_width = 12,
+ ram_block3a_8.port_b_data_out_clear = "none",
+ ram_block3a_8.port_b_data_out_clock = "none",
+ ram_block3a_8.port_b_data_width = 1,
+ ram_block3a_8.port_b_first_address = 0,
+ ram_block3a_8.port_b_first_bit_number = 8,
+ ram_block3a_8.port_b_last_address = 4095,
+ ram_block3a_8.port_b_logical_ram_depth = 4096,
+ ram_block3a_8.port_b_logical_ram_width = 16,
+ ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_8.ram_block_type = "auto",
+ ram_block3a_8.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_9
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[9]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_9portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_9.connectivity_checking = "OFF",
+ ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_9.operation_mode = "dual_port",
+ ram_block3a_9.port_a_address_width = 12,
+ ram_block3a_9.port_a_data_width = 1,
+ ram_block3a_9.port_a_first_address = 0,
+ ram_block3a_9.port_a_first_bit_number = 9,
+ ram_block3a_9.port_a_last_address = 4095,
+ ram_block3a_9.port_a_logical_ram_depth = 4096,
+ ram_block3a_9.port_a_logical_ram_width = 16,
+ ram_block3a_9.port_b_address_clear = "none",
+ ram_block3a_9.port_b_address_clock = "clock1",
+ ram_block3a_9.port_b_address_width = 12,
+ ram_block3a_9.port_b_data_out_clear = "none",
+ ram_block3a_9.port_b_data_out_clock = "none",
+ ram_block3a_9.port_b_data_width = 1,
+ ram_block3a_9.port_b_first_address = 0,
+ ram_block3a_9.port_b_first_bit_number = 9,
+ ram_block3a_9.port_b_last_address = 4095,
+ ram_block3a_9.port_b_logical_ram_depth = 4096,
+ ram_block3a_9.port_b_logical_ram_width = 16,
+ ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_9.ram_block_type = "auto",
+ ram_block3a_9.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_10
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[10]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_10portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_10.connectivity_checking = "OFF",
+ ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_10.operation_mode = "dual_port",
+ ram_block3a_10.port_a_address_width = 12,
+ ram_block3a_10.port_a_data_width = 1,
+ ram_block3a_10.port_a_first_address = 0,
+ ram_block3a_10.port_a_first_bit_number = 10,
+ ram_block3a_10.port_a_last_address = 4095,
+ ram_block3a_10.port_a_logical_ram_depth = 4096,
+ ram_block3a_10.port_a_logical_ram_width = 16,
+ ram_block3a_10.port_b_address_clear = "none",
+ ram_block3a_10.port_b_address_clock = "clock1",
+ ram_block3a_10.port_b_address_width = 12,
+ ram_block3a_10.port_b_data_out_clear = "none",
+ ram_block3a_10.port_b_data_out_clock = "none",
+ ram_block3a_10.port_b_data_width = 1,
+ ram_block3a_10.port_b_first_address = 0,
+ ram_block3a_10.port_b_first_bit_number = 10,
+ ram_block3a_10.port_b_last_address = 4095,
+ ram_block3a_10.port_b_logical_ram_depth = 4096,
+ ram_block3a_10.port_b_logical_ram_width = 16,
+ ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_10.ram_block_type = "auto",
+ ram_block3a_10.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_11
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[11]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_11portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_11.connectivity_checking = "OFF",
+ ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_11.operation_mode = "dual_port",
+ ram_block3a_11.port_a_address_width = 12,
+ ram_block3a_11.port_a_data_width = 1,
+ ram_block3a_11.port_a_first_address = 0,
+ ram_block3a_11.port_a_first_bit_number = 11,
+ ram_block3a_11.port_a_last_address = 4095,
+ ram_block3a_11.port_a_logical_ram_depth = 4096,
+ ram_block3a_11.port_a_logical_ram_width = 16,
+ ram_block3a_11.port_b_address_clear = "none",
+ ram_block3a_11.port_b_address_clock = "clock1",
+ ram_block3a_11.port_b_address_width = 12,
+ ram_block3a_11.port_b_data_out_clear = "none",
+ ram_block3a_11.port_b_data_out_clock = "none",
+ ram_block3a_11.port_b_data_width = 1,
+ ram_block3a_11.port_b_first_address = 0,
+ ram_block3a_11.port_b_first_bit_number = 11,
+ ram_block3a_11.port_b_last_address = 4095,
+ ram_block3a_11.port_b_logical_ram_depth = 4096,
+ ram_block3a_11.port_b_logical_ram_width = 16,
+ ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_11.ram_block_type = "auto",
+ ram_block3a_11.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_12
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[12]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_12portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_12.connectivity_checking = "OFF",
+ ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_12.operation_mode = "dual_port",
+ ram_block3a_12.port_a_address_width = 12,
+ ram_block3a_12.port_a_data_width = 1,
+ ram_block3a_12.port_a_first_address = 0,
+ ram_block3a_12.port_a_first_bit_number = 12,
+ ram_block3a_12.port_a_last_address = 4095,
+ ram_block3a_12.port_a_logical_ram_depth = 4096,
+ ram_block3a_12.port_a_logical_ram_width = 16,
+ ram_block3a_12.port_b_address_clear = "none",
+ ram_block3a_12.port_b_address_clock = "clock1",
+ ram_block3a_12.port_b_address_width = 12,
+ ram_block3a_12.port_b_data_out_clear = "none",
+ ram_block3a_12.port_b_data_out_clock = "none",
+ ram_block3a_12.port_b_data_width = 1,
+ ram_block3a_12.port_b_first_address = 0,
+ ram_block3a_12.port_b_first_bit_number = 12,
+ ram_block3a_12.port_b_last_address = 4095,
+ ram_block3a_12.port_b_logical_ram_depth = 4096,
+ ram_block3a_12.port_b_logical_ram_width = 16,
+ ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_12.ram_block_type = "auto",
+ ram_block3a_12.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_13
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[13]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_13portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_13.connectivity_checking = "OFF",
+ ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_13.operation_mode = "dual_port",
+ ram_block3a_13.port_a_address_width = 12,
+ ram_block3a_13.port_a_data_width = 1,
+ ram_block3a_13.port_a_first_address = 0,
+ ram_block3a_13.port_a_first_bit_number = 13,
+ ram_block3a_13.port_a_last_address = 4095,
+ ram_block3a_13.port_a_logical_ram_depth = 4096,
+ ram_block3a_13.port_a_logical_ram_width = 16,
+ ram_block3a_13.port_b_address_clear = "none",
+ ram_block3a_13.port_b_address_clock = "clock1",
+ ram_block3a_13.port_b_address_width = 12,
+ ram_block3a_13.port_b_data_out_clear = "none",
+ ram_block3a_13.port_b_data_out_clock = "none",
+ ram_block3a_13.port_b_data_width = 1,
+ ram_block3a_13.port_b_first_address = 0,
+ ram_block3a_13.port_b_first_bit_number = 13,
+ ram_block3a_13.port_b_last_address = 4095,
+ ram_block3a_13.port_b_logical_ram_depth = 4096,
+ ram_block3a_13.port_b_logical_ram_width = 16,
+ ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_13.ram_block_type = "auto",
+ ram_block3a_13.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_14
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[14]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_14portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_14.connectivity_checking = "OFF",
+ ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_14.operation_mode = "dual_port",
+ ram_block3a_14.port_a_address_width = 12,
+ ram_block3a_14.port_a_data_width = 1,
+ ram_block3a_14.port_a_first_address = 0,
+ ram_block3a_14.port_a_first_bit_number = 14,
+ ram_block3a_14.port_a_last_address = 4095,
+ ram_block3a_14.port_a_logical_ram_depth = 4096,
+ ram_block3a_14.port_a_logical_ram_width = 16,
+ ram_block3a_14.port_b_address_clear = "none",
+ ram_block3a_14.port_b_address_clock = "clock1",
+ ram_block3a_14.port_b_address_width = 12,
+ ram_block3a_14.port_b_data_out_clear = "none",
+ ram_block3a_14.port_b_data_out_clock = "none",
+ ram_block3a_14.port_b_data_width = 1,
+ ram_block3a_14.port_b_first_address = 0,
+ ram_block3a_14.port_b_first_bit_number = 14,
+ ram_block3a_14.port_b_last_address = 4095,
+ ram_block3a_14.port_b_logical_ram_depth = 4096,
+ ram_block3a_14.port_b_logical_ram_width = 16,
+ ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_14.ram_block_type = "auto",
+ ram_block3a_14.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block3a_15
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[11:0]}),
+ .portadatain({data_a[15]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[11:0]}),
+ .portbdataout(wire_ram_block3a_15portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks(1'b1),
+ .portbbyteenamasks(1'b1),
+ .portbdatain(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block3a_15.connectivity_checking = "OFF",
+ ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
+ ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
+ ram_block3a_15.operation_mode = "dual_port",
+ ram_block3a_15.port_a_address_width = 12,
+ ram_block3a_15.port_a_data_width = 1,
+ ram_block3a_15.port_a_first_address = 0,
+ ram_block3a_15.port_a_first_bit_number = 15,
+ ram_block3a_15.port_a_last_address = 4095,
+ ram_block3a_15.port_a_logical_ram_depth = 4096,
+ ram_block3a_15.port_a_logical_ram_width = 16,
+ ram_block3a_15.port_b_address_clear = "none",
+ ram_block3a_15.port_b_address_clock = "clock1",
+ ram_block3a_15.port_b_address_width = 12,
+ ram_block3a_15.port_b_data_out_clear = "none",
+ ram_block3a_15.port_b_data_out_clock = "none",
+ ram_block3a_15.port_b_data_width = 1,
+ ram_block3a_15.port_b_first_address = 0,
+ ram_block3a_15.port_b_first_bit_number = 15,
+ ram_block3a_15.port_b_last_address = 4095,
+ ram_block3a_15.port_b_logical_ram_depth = 4096,
+ ram_block3a_15.port_b_logical_ram_width = 16,
+ ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block3a_15.ram_block_type = "auto",
+ ram_block3a_15.lpm_type = "cyclone_ram_block";
+ assign
+ address_a_wire = address_a,
+ address_b_wire = address_b,
+ q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
+endmodule //fifo_4k_altsyncram_8pl
+
+
+//dffpipe DELAY=1 WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_dffpipe_bb3
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [11:0] d;
+ output [11:0] q;
+
+ wire [11:0] wire_dffe4a_D;
+ reg [11:0] dffe4a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe4a[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
+ // synopsys translate_off
+ initial
+ dffe4a[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
+ // synopsys translate_off
+ initial
+ dffe4a[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
+ // synopsys translate_off
+ initial
+ dffe4a[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
+ // synopsys translate_off
+ initial
+ dffe4a[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
+ // synopsys translate_off
+ initial
+ dffe4a[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
+ // synopsys translate_off
+ initial
+ dffe4a[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
+ // synopsys translate_off
+ initial
+ dffe4a[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
+ // synopsys translate_off
+ initial
+ dffe4a[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
+ // synopsys translate_off
+ initial
+ dffe4a[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
+ // synopsys translate_off
+ initial
+ dffe4a[10:10] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
+ // synopsys translate_off
+ initial
+ dffe4a[11:11] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
+ else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
+ else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
+ assign
+ wire_dffe4a_D = (d & {12{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe4a,
+ sclr = 1'b0;
+endmodule //fifo_4k_dffpipe_bb3
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_dffpipe_em2
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [11:0] d;
+ output [11:0] q;
+
+ wire [11:0] wire_dffe6a_D;
+ reg [11:0] dffe6a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe6a[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
+ // synopsys translate_off
+ initial
+ dffe6a[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
+ // synopsys translate_off
+ initial
+ dffe6a[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
+ // synopsys translate_off
+ initial
+ dffe6a[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
+ // synopsys translate_off
+ initial
+ dffe6a[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
+ // synopsys translate_off
+ initial
+ dffe6a[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
+ // synopsys translate_off
+ initial
+ dffe6a[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
+ // synopsys translate_off
+ initial
+ dffe6a[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
+ // synopsys translate_off
+ initial
+ dffe6a[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
+ // synopsys translate_off
+ initial
+ dffe6a[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
+ // synopsys translate_off
+ initial
+ dffe6a[10:10] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
+ // synopsys translate_off
+ initial
+ dffe6a[11:11] = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
+ else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
+ else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
+ assign
+ wire_dffe6a_D = (d & {12{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe6a,
+ sclr = 1'b0;
+endmodule //fifo_4k_dffpipe_em2
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_alt_synch_pipe_em2
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
+ input clock;
+ input clrn;
+ input [11:0] d;
+ output [11:0] q;
+
+ wire [11:0] wire_dffpipe5_q;
+
+ fifo_4k_dffpipe_em2 dffpipe5
+ (
+ .clock(clock),
+ .clrn(clrn),
+ .d(d),
+ .q(wire_dffpipe5_q));
+ assign
+ q = wire_dffpipe5_q;
+endmodule //fifo_4k_alt_synch_pipe_em2
+
+
+//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 12
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_add_sub_b18
+ (
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input [11:0] dataa;
+ input [11:0] datab;
+ output [11:0] result;
+
+ wire [11:0] wire_add_sub_cella_combout;
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [0:0] wire_add_sub_cella_7cout;
+ wire [0:0] wire_add_sub_cella_8cout;
+ wire [0:0] wire_add_sub_cella_9cout;
+ wire [0:0] wire_add_sub_cella_10cout;
+ wire [11:0] wire_add_sub_cella_dataa;
+ wire [11:0] wire_add_sub_cella_datab;
+
+ cyclone_lcell add_sub_cella_0
+ (
+ .cin(1'b1),
+ .combout(wire_add_sub_cella_combout[0:0]),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "69b2",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_1
+ (
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .combout(wire_add_sub_cella_combout[1:1]),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "69b2",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_2
+ (
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .combout(wire_add_sub_cella_combout[2:2]),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "69b2",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_3
+ (
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .combout(wire_add_sub_cella_combout[3:3]),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "69b2",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_4
+ (
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .combout(wire_add_sub_cella_combout[4:4]),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "69b2",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_5
+ (
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .combout(wire_add_sub_cella_combout[5:5]),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "69b2",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_6
+ (
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .combout(wire_add_sub_cella_combout[6:6]),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "69b2",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_7
+ (
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .combout(wire_add_sub_cella_combout[7:7]),
+ .cout(wire_add_sub_cella_7cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "69b2",
+ add_sub_cella_7.operation_mode = "arithmetic",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_8
+ (
+ .cin(wire_add_sub_cella_7cout[0:0]),
+ .combout(wire_add_sub_cella_combout[8:8]),
+ .cout(wire_add_sub_cella_8cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[8:8]),
+ .datab(wire_add_sub_cella_datab[8:8]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_8.cin_used = "true",
+ add_sub_cella_8.lut_mask = "69b2",
+ add_sub_cella_8.operation_mode = "arithmetic",
+ add_sub_cella_8.sum_lutc_input = "cin",
+ add_sub_cella_8.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_9
+ (
+ .cin(wire_add_sub_cella_8cout[0:0]),
+ .combout(wire_add_sub_cella_combout[9:9]),
+ .cout(wire_add_sub_cella_9cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[9:9]),
+ .datab(wire_add_sub_cella_datab[9:9]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_9.cin_used = "true",
+ add_sub_cella_9.lut_mask = "69b2",
+ add_sub_cella_9.operation_mode = "arithmetic",
+ add_sub_cella_9.sum_lutc_input = "cin",
+ add_sub_cella_9.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_10
+ (
+ .cin(wire_add_sub_cella_9cout[0:0]),
+ .combout(wire_add_sub_cella_combout[10:10]),
+ .cout(wire_add_sub_cella_10cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[10:10]),
+ .datab(wire_add_sub_cella_datab[10:10]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_10.cin_used = "true",
+ add_sub_cella_10.lut_mask = "69b2",
+ add_sub_cella_10.operation_mode = "arithmetic",
+ add_sub_cella_10.sum_lutc_input = "cin",
+ add_sub_cella_10.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_11
+ (
+ .cin(wire_add_sub_cella_10cout[0:0]),
+ .combout(wire_add_sub_cella_combout[11:11]),
+ .cout(),
+ .dataa(wire_add_sub_cella_dataa[11:11]),
+ .datab(wire_add_sub_cella_datab[11:11]),
+ .regout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_11.cin_used = "true",
+ add_sub_cella_11.lut_mask = "6969",
+ add_sub_cella_11.operation_mode = "normal",
+ add_sub_cella_11.sum_lutc_input = "cin",
+ add_sub_cella_11.lpm_type = "cyclone_lcell";
+ assign
+ wire_add_sub_cella_dataa = dataa,
+ wire_add_sub_cella_datab = datab;
+ assign
+ result = wire_add_sub_cella_combout;
+endmodule //fifo_4k_add_sub_b18
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
+
+//synthesis_resources = lut 104 M4K 16
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_4k_dcfifo_6cq
+ (
+ aclr,
+ data,
+ q,
+ rdclk,
+ rdempty,
+ rdreq,
+ rdusedw,
+ wrclk,
+ wrfull,
+ wrreq,
+ wrusedw) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
+ input aclr;
+ input [15:0] data;
+ output [15:0] q;
+ input rdclk;
+ output rdempty;
+ input rdreq;
+ output [11:0] rdusedw;
+ input wrclk;
+ output wrfull;
+ input wrreq;
+ output [11:0] wrusedw;
+
+ wire [11:0] wire_rdptr_g_gray2bin_bin;
+ wire [11:0] wire_rs_dgwp_gray2bin_bin;
+ wire [11:0] wire_wrptr_g_gray2bin_bin;
+ wire [11:0] wire_ws_dgrp_gray2bin_bin;
+ wire [11:0] wire_rdptr_g_q;
+ wire [11:0] wire_rdptr_g1p_q;
+ wire [11:0] wire_wrptr_g1p_q;
+ wire [15:0] wire_fifo_ram_q_b;
+ reg [11:0] delayed_wrptr_g;
+ reg [11:0] wrptr_g;
+ wire [11:0] wire_rs_brp_q;
+ wire [11:0] wire_rs_bwp_q;
+ wire [11:0] wire_rs_dgwp_q;
+ wire [11:0] wire_ws_brp_q;
+ wire [11:0] wire_ws_bwp_q;
+ wire [11:0] wire_ws_dgrp_q;
+ wire [11:0] wire_rdusedw_sub_result;
+ wire [11:0] wire_wrusedw_sub_result;
+ reg wire_rdempty_eq_comp_aeb_int;
+ wire wire_rdempty_eq_comp_aeb;
+ wire [11:0] wire_rdempty_eq_comp_dataa;
+ wire [11:0] wire_rdempty_eq_comp_datab;
+ reg wire_wrfull_eq_comp_aeb_int;
+ wire wire_wrfull_eq_comp_aeb;
+ wire [11:0] wire_wrfull_eq_comp_dataa;
+ wire [11:0] wire_wrfull_eq_comp_datab;
+ wire int_rdempty;
+ wire int_wrfull;
+ wire valid_rdreq;
+ wire valid_wrreq;
+
+ fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
+ (
+ .bin(wire_rdptr_g_gray2bin_bin),
+ .gray(wire_rdptr_g_q));
+ fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
+ (
+ .bin(wire_rs_dgwp_gray2bin_bin),
+ .gray(wire_rs_dgwp_q));
+ fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
+ (
+ .bin(wire_wrptr_g_gray2bin_bin),
+ .gray(wrptr_g));
+ fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
+ (
+ .bin(wire_ws_dgrp_gray2bin_bin),
+ .gray(wire_ws_dgrp_q));
+ fifo_4k_a_graycounter_826 rdptr_g
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rdreq),
+ .q(wire_rdptr_g_q));
+ fifo_4k_a_graycounter_3r6 rdptr_g1p
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rdreq),
+ .q(wire_rdptr_g1p_q));
+ fifo_4k_a_graycounter_3r6 wrptr_g1p
+ (
+ .aclr(aclr),
+ .clock(wrclk),
+ .cnt_en(valid_wrreq),
+ .q(wire_wrptr_g1p_q));
+ fifo_4k_altsyncram_8pl fifo_ram
+ (
+ .address_a(wrptr_g),
+ .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
+ .clock0(wrclk),
+ .clock1(rdclk),
+ .clocken1((valid_rdreq | int_rdempty)),
+ .data_a(data),
+ .q_b(wire_fifo_ram_q_b),
+ .wren_a(valid_wrreq));
+ // synopsys translate_off
+ initial
+ delayed_wrptr_g = 0;
+ // synopsys translate_on
+ always @ ( posedge wrclk or posedge aclr)
+ if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
+ else delayed_wrptr_g <= wrptr_g;
+ // synopsys translate_off
+ initial
+ wrptr_g = 0;
+ // synopsys translate_on
+ always @ ( posedge wrclk or posedge aclr)
+ if (aclr == 1'b1) wrptr_g <= 12'b0;
+ else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
+ fifo_4k_dffpipe_bb3 rs_brp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(wire_rdptr_g_gray2bin_bin),
+ .q(wire_rs_brp_q));
+ fifo_4k_dffpipe_bb3 rs_bwp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(wire_rs_dgwp_gray2bin_bin),
+ .q(wire_rs_bwp_q));
+ fifo_4k_alt_synch_pipe_em2 rs_dgwp
+ (
+ .clock(rdclk),
+ .clrn((~ aclr)),
+ .d(delayed_wrptr_g),
+ .q(wire_rs_dgwp_q));
+ fifo_4k_dffpipe_bb3 ws_brp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_ws_dgrp_gray2bin_bin),
+ .q(wire_ws_brp_q));
+ fifo_4k_dffpipe_bb3 ws_bwp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_wrptr_g_gray2bin_bin),
+ .q(wire_ws_bwp_q));
+ fifo_4k_alt_synch_pipe_em2 ws_dgrp
+ (
+ .clock(wrclk),
+ .clrn((~ aclr)),
+ .d(wire_rdptr_g_q),
+ .q(wire_ws_dgrp_q));
+ fifo_4k_add_sub_b18 rdusedw_sub
+ (
+ .dataa(wire_rs_bwp_q),
+ .datab(wire_rs_brp_q),
+ .result(wire_rdusedw_sub_result));
+ fifo_4k_add_sub_b18 wrusedw_sub
+ (
+ .dataa(wire_ws_bwp_q),
+ .datab(wire_ws_brp_q),
+ .result(wire_wrusedw_sub_result));
+ always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
+ if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
+ begin
+ wire_rdempty_eq_comp_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_rdempty_eq_comp_aeb_int = 1'b0;
+ end
+ assign
+ wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
+ assign
+ wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
+ wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
+ always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
+ if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
+ begin
+ wire_wrfull_eq_comp_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_wrfull_eq_comp_aeb_int = 1'b0;
+ end
+ assign
+ wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
+ assign
+ wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
+ wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
+ assign
+ int_rdempty = wire_rdempty_eq_comp_aeb,
+ int_wrfull = wire_wrfull_eq_comp_aeb,
+ q = wire_fifo_ram_q_b,
+ rdempty = int_rdempty,
+ rdusedw = wire_rdusedw_sub_result,
+ valid_rdreq = rdreq,
+ valid_wrreq = wrreq,
+ wrfull = int_wrfull,
+ wrusedw = wire_wrusedw_sub_result;
+endmodule //fifo_4k_dcfifo_6cq
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4k (
+ data,
+ wrreq,
+ rdreq,
+ rdclk,
+ wrclk,
+ aclr,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [15:0] q;
+ output rdempty;
+ output [11:0] rdusedw;
+ output wrfull;
+ output [11:0] wrusedw;
+
+ wire sub_wire0;
+ wire [11:0] sub_wire1;
+ wire sub_wire2;
+ wire [15:0] sub_wire3;
+ wire [11:0] sub_wire4;
+ wire rdempty = sub_wire0;
+ wire [11:0] wrusedw = sub_wire1[11:0];
+ wire wrfull = sub_wire2;
+ wire [15:0] q = sub_wire3[15:0];
+ wire [11:0] rdusedw = sub_wire4[11:0];
+
+ fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdempty (sub_wire0),
+ .wrusedw (sub_wire1),
+ .wrfull (sub_wire2),
+ .q (sub_wire3),
+ .rdusedw (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
diff --git a/megacells/fifo_4k_bb.v b/megacells/fifo_4k_bb.v
new file mode 100644
index 000000000..fc4ca9797
--- /dev/null
+++ b/megacells/fifo_4k_bb.v
@@ -0,0 +1,131 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_4k (
+ data,
+ wrreq,
+ rdreq,
+ rdclk,
+ wrclk,
+ aclr,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [15:0] q;
+ output rdempty;
+ output [11:0] rdusedw;
+ output wrfull;
+ output [11:0] wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
diff --git a/megacells/mylpm_addsub.bsf b/megacells/mylpm_addsub.bsf
new file mode 100755
index 000000000..e5c1ded7f
--- /dev/null
+++ b/megacells/mylpm_addsub.bsf
@@ -0,0 +1,80 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 112)
+ (text "mylpm_addsub" (rect 26 2 145 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 93 30 108)(font "Arial" ))
+ (port
+ (pt 0 56)
+ (input)
+ (text "dataa[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+ (text "dataa[15..0]" (rect 4 40 73 56)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 64 56)(line_width 3))
+ )
+ (port
+ (pt 0 88)
+ (input)
+ (text "datab[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+ (text "datab[15..0]" (rect 4 72 73 88)(font "Arial" (font_size 8)))
+ (line (pt 0 88)(pt 64 88)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "clock" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 56 35 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "add_sub" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+ (text "add_sub" (rect 4 16 53 32)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 80 32)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "result[15..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+ (text "result[15..0]" (rect 88 56 157 72)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 96 72)(line_width 3))
+ )
+ (drawing
+ (text "A" (rect 66 48 75 64)(font "Arial" (font_size 8)))
+ (text "B" (rect 66 80 75 96)(font "Arial" (font_size 8)))
+ (text "A+B/A-B" (rect 82 37 134 53)(font "Arial" (font_size 8)))
+ (line (pt 64 48)(pt 96 56)(line_width 1))
+ (line (pt 96 56)(pt 96 88)(line_width 1))
+ (line (pt 96 88)(pt 64 96)(line_width 1))
+ (line (pt 64 96)(pt 64 48)(line_width 1))
+ (line (pt 80 32)(pt 80 52)(line_width 1))
+ (line (pt 106 40)(pt 125 40)(line_width 1))
+ (line (pt 64 66)(pt 70 72)(line_width 1))
+ (line (pt 70 72)(pt 64 78)(line_width 1))
+ )
+)
diff --git a/megacells/mylpm_addsub.cmp b/megacells/mylpm_addsub.cmp
new file mode 100755
index 000000000..311c54a5b
--- /dev/null
+++ b/megacells/mylpm_addsub.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component mylpm_addsub
+ PORT
+ (
+ add_sub : IN STD_LOGIC ;
+ dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ clock : IN STD_LOGIC ;
+ result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/mylpm_addsub.inc b/megacells/mylpm_addsub.inc
new file mode 100755
index 000000000..d8b283f49
--- /dev/null
+++ b/megacells/mylpm_addsub.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION mylpm_addsub
+(
+ add_sub,
+ dataa[15..0],
+ datab[15..0],
+ clock
+)
+
+RETURNS (
+ result[15..0]
+);
diff --git a/megacells/mylpm_addsub.v b/megacells/mylpm_addsub.v
new file mode 100755
index 000000000..0566f7e57
--- /dev/null
+++ b/megacells/mylpm_addsub.v
@@ -0,0 +1,102 @@
+// megafunction wizard: %LPM_ADD_SUB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub
+
+// ============================================================
+// File Name: mylpm_addsub.v
+// Megafunction Name(s):
+// lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module mylpm_addsub (
+ add_sub,
+ dataa,
+ datab,
+ clock,
+ result);
+
+ input add_sub;
+ input [15:0] dataa;
+ input [15:0] datab;
+ input clock;
+ output [15:0] result;
+
+ wire [15:0] sub_wire0;
+ wire [15:0] result = sub_wire0[15:0];
+
+ lpm_add_sub lpm_add_sub_component (
+ .dataa (dataa),
+ .add_sub (add_sub),
+ .datab (datab),
+ .clock (clock),
+ .result (sub_wire0));
+ defparam
+ lpm_add_sub_component.lpm_width = 16,
+ lpm_add_sub_component.lpm_direction = "UNUSED",
+ lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
+ lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
+ lpm_add_sub_component.lpm_pipeline = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "16"
+// Retrieval info: PRIVATE: Function NUMERIC "2"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/megacells/mylpm_addsub_bb.v b/megacells/mylpm_addsub_bb.v
new file mode 100755
index 000000000..598d3da52
--- /dev/null
+++ b/megacells/mylpm_addsub_bb.v
@@ -0,0 +1,35 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module mylpm_addsub (
+ add_sub,
+ dataa,
+ datab,
+ clock,
+ result);
+
+ input add_sub;
+ input [15:0] dataa;
+ input [15:0] datab;
+ input clock;
+ output [15:0] result;
+
+endmodule
+
diff --git a/megacells/mylpm_addsub_inst.v b/megacells/mylpm_addsub_inst.v
new file mode 100755
index 000000000..dd732bd6d
--- /dev/null
+++ b/megacells/mylpm_addsub_inst.v
@@ -0,0 +1,7 @@
+mylpm_addsub mylpm_addsub_inst (
+ .add_sub ( add_sub_sig ),
+ .dataa ( dataa_sig ),
+ .datab ( datab_sig ),
+ .clock ( clock_sig ),
+ .result ( result_sig )
+ );
diff --git a/megacells/pll.v b/megacells/pll.v
new file mode 100644
index 000000000..dacd11f23
--- /dev/null
+++ b/megacells/pll.v
@@ -0,0 +1,207 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0)
+ // synopsys translate_off
+,
+ .fbin (),
+ .pllena (),
+ .clkswitch (),
+ .areset (),
+ .pfdena (),
+ .clkena (),
+ .extclkena (),
+ .scanclk (),
+ .scanaclr (),
+ .scandata (),
+ .scanread (),
+ .scanwrite (),
+ .extclk (),
+ .clkbad (),
+ .activeclock (),
+ .locked (),
+ .clkloss (),
+ .scandataout (),
+ .scandone (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .enable0 (),
+ .enable1 ()
+ // synopsys translate_on
+
+);
+ defparam
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.inclk0_input_frequency = 20833,
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.pll_type = "AUTO",
+ altpll_component.clk0_time_delay = "0",
+ altpll_component.intended_device_family = "Cyclone",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk0_phase_shift = "-3000";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
diff --git a/megacells/pll_bb.v b/megacells/pll_bb.v
new file mode 100644
index 000000000..debadaa25
--- /dev/null
+++ b/megacells/pll_bb.v
@@ -0,0 +1,29 @@
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+endmodule
+
diff --git a/megacells/pll_inst.v b/megacells/pll_inst.v
new file mode 100644
index 000000000..97db58ba0
--- /dev/null
+++ b/megacells/pll_inst.v
@@ -0,0 +1,4 @@
+pll pll_inst (
+ .inclk0 ( inclk0_sig ),
+ .c0 ( c0_sig )
+ );
diff --git a/megacells/sub32.bsf b/megacells/sub32.bsf
new file mode 100755
index 000000000..753fdc738
--- /dev/null
+++ b/megacells/sub32.bsf
@@ -0,0 +1,87 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 128)
+ (text "sub32" (rect 58 2 109 21)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 109 31 124)(font "Arial" ))
+ (port
+ (pt 0 40)
+ (input)
+ (text "dataa[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "dataa[31..0]" (rect 4 24 73 40)(font "Arial" (font_size 8)))
+ (line (pt 0 40)(pt 64 40)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "datab[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "datab[31..0]" (rect 4 56 73 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 40 35 56)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 64 56)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+ (text "clken" (rect 4 80 35 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 74 96)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 4 96 25 112)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 85 112)(line_width 1))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+ (text "result[31..0]" (rect 88 40 157 56)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 96 56)(line_width 3))
+ )
+ (drawing
+ (text "A" (rect 66 32 75 48)(font "Arial" (font_size 8)))
+ (text "B" (rect 66 64 75 80)(font "Arial" (font_size 8)))
+ (text "A-B" (rect 72 48 94 64)(font "Arial" (font_size 8)))
+ (line (pt 64 32)(pt 96 40)(line_width 1))
+ (line (pt 96 40)(pt 96 72)(line_width 1))
+ (line (pt 96 72)(pt 64 80)(line_width 1))
+ (line (pt 64 80)(pt 64 32)(line_width 1))
+ (line (pt 74 96)(pt 74 77)(line_width 1))
+ (line (pt 85 112)(pt 85 74)(line_width 1))
+ (line (pt 64 50)(pt 70 56)(line_width 1))
+ (line (pt 70 56)(pt 64 62)(line_width 1))
+ )
+)
diff --git a/megacells/sub32.cmp b/megacells/sub32.cmp
new file mode 100755
index 000000000..0d5b62ef9
--- /dev/null
+++ b/megacells/sub32.cmp
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component sub32
+ PORT
+ (
+ dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ clock : IN STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clken : IN STD_LOGIC ;
+ result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
+end component;
diff --git a/megacells/sub32.inc b/megacells/sub32.inc
new file mode 100755
index 000000000..3c64e21c5
--- /dev/null
+++ b/megacells/sub32.inc
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION sub32
+(
+ dataa[31..0],
+ datab[31..0],
+ clock,
+ aclr,
+ clken
+)
+
+RETURNS (
+ result[31..0]
+);
diff --git a/megacells/sub32.v b/megacells/sub32.v
new file mode 100755
index 000000000..dd825d91a
--- /dev/null
+++ b/megacells/sub32.v
@@ -0,0 +1,675 @@
+// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub
+
+// ============================================================
+// File Name: sub32.v
+// Megafunction Name(s):
+// lpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
+
+//synthesis_resources = lut 32
+module sub32_add_sub_cqa
+ (
+ aclr,
+ clken,
+ clock,
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clken;
+ input clock;
+ input [31:0] dataa;
+ input [31:0] datab;
+ output [31:0] result;
+
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [0:0] wire_add_sub_cella_7cout;
+ wire [0:0] wire_add_sub_cella_8cout;
+ wire [0:0] wire_add_sub_cella_9cout;
+ wire [0:0] wire_add_sub_cella_10cout;
+ wire [0:0] wire_add_sub_cella_11cout;
+ wire [0:0] wire_add_sub_cella_12cout;
+ wire [0:0] wire_add_sub_cella_13cout;
+ wire [0:0] wire_add_sub_cella_14cout;
+ wire [0:0] wire_add_sub_cella_15cout;
+ wire [0:0] wire_add_sub_cella_16cout;
+ wire [0:0] wire_add_sub_cella_17cout;
+ wire [0:0] wire_add_sub_cella_18cout;
+ wire [0:0] wire_add_sub_cella_19cout;
+ wire [0:0] wire_add_sub_cella_20cout;
+ wire [0:0] wire_add_sub_cella_21cout;
+ wire [0:0] wire_add_sub_cella_22cout;
+ wire [0:0] wire_add_sub_cella_23cout;
+ wire [0:0] wire_add_sub_cella_24cout;
+ wire [0:0] wire_add_sub_cella_25cout;
+ wire [0:0] wire_add_sub_cella_26cout;
+ wire [0:0] wire_add_sub_cella_27cout;
+ wire [0:0] wire_add_sub_cella_28cout;
+ wire [0:0] wire_add_sub_cella_29cout;
+ wire [0:0] wire_add_sub_cella_30cout;
+ wire [31:0] wire_add_sub_cella_dataa;
+ wire [31:0] wire_add_sub_cella_datab;
+ wire [31:0] wire_add_sub_cella_regout;
+
+ stratix_lcell add_sub_cella_0
+ (
+ .aclr(aclr),
+ .cin(1'b1),
+ .clk(clock),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[0:0]));
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "69b2",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_1
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[1:1]));
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "69b2",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_2
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[2:2]));
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "69b2",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_3
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[3:3]));
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "69b2",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_4
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[4:4]));
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "69b2",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_5
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[5:5]));
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "69b2",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_6
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[6:6]));
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "69b2",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_7
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_7cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[7:7]));
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "69b2",
+ add_sub_cella_7.operation_mode = "arithmetic",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_8
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_7cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_8cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[8:8]),
+ .datab(wire_add_sub_cella_datab[8:8]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[8:8]));
+ defparam
+ add_sub_cella_8.cin_used = "true",
+ add_sub_cella_8.lut_mask = "69b2",
+ add_sub_cella_8.operation_mode = "arithmetic",
+ add_sub_cella_8.sum_lutc_input = "cin",
+ add_sub_cella_8.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_9
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_8cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_9cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[9:9]),
+ .datab(wire_add_sub_cella_datab[9:9]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[9:9]));
+ defparam
+ add_sub_cella_9.cin_used = "true",
+ add_sub_cella_9.lut_mask = "69b2",
+ add_sub_cella_9.operation_mode = "arithmetic",
+ add_sub_cella_9.sum_lutc_input = "cin",
+ add_sub_cella_9.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_10
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_9cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_10cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[10:10]),
+ .datab(wire_add_sub_cella_datab[10:10]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[10:10]));
+ defparam
+ add_sub_cella_10.cin_used = "true",
+ add_sub_cella_10.lut_mask = "69b2",
+ add_sub_cella_10.operation_mode = "arithmetic",
+ add_sub_cella_10.sum_lutc_input = "cin",
+ add_sub_cella_10.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_11
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_10cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_11cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[11:11]),
+ .datab(wire_add_sub_cella_datab[11:11]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[11:11]));
+ defparam
+ add_sub_cella_11.cin_used = "true",
+ add_sub_cella_11.lut_mask = "69b2",
+ add_sub_cella_11.operation_mode = "arithmetic",
+ add_sub_cella_11.sum_lutc_input = "cin",
+ add_sub_cella_11.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_12
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_11cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_12cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[12:12]),
+ .datab(wire_add_sub_cella_datab[12:12]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[12:12]));
+ defparam
+ add_sub_cella_12.cin_used = "true",
+ add_sub_cella_12.lut_mask = "69b2",
+ add_sub_cella_12.operation_mode = "arithmetic",
+ add_sub_cella_12.sum_lutc_input = "cin",
+ add_sub_cella_12.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_13
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_12cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_13cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[13:13]),
+ .datab(wire_add_sub_cella_datab[13:13]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[13:13]));
+ defparam
+ add_sub_cella_13.cin_used = "true",
+ add_sub_cella_13.lut_mask = "69b2",
+ add_sub_cella_13.operation_mode = "arithmetic",
+ add_sub_cella_13.sum_lutc_input = "cin",
+ add_sub_cella_13.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_14
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_13cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_14cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[14:14]),
+ .datab(wire_add_sub_cella_datab[14:14]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[14:14]));
+ defparam
+ add_sub_cella_14.cin_used = "true",
+ add_sub_cella_14.lut_mask = "69b2",
+ add_sub_cella_14.operation_mode = "arithmetic",
+ add_sub_cella_14.sum_lutc_input = "cin",
+ add_sub_cella_14.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_15
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_14cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_15cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[15:15]),
+ .datab(wire_add_sub_cella_datab[15:15]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[15:15]));
+ defparam
+ add_sub_cella_15.cin_used = "true",
+ add_sub_cella_15.lut_mask = "69b2",
+ add_sub_cella_15.operation_mode = "arithmetic",
+ add_sub_cella_15.sum_lutc_input = "cin",
+ add_sub_cella_15.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_16
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_15cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_16cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[16:16]),
+ .datab(wire_add_sub_cella_datab[16:16]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[16:16]));
+ defparam
+ add_sub_cella_16.cin_used = "true",
+ add_sub_cella_16.lut_mask = "69b2",
+ add_sub_cella_16.operation_mode = "arithmetic",
+ add_sub_cella_16.sum_lutc_input = "cin",
+ add_sub_cella_16.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_17
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_16cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_17cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[17:17]),
+ .datab(wire_add_sub_cella_datab[17:17]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[17:17]));
+ defparam
+ add_sub_cella_17.cin_used = "true",
+ add_sub_cella_17.lut_mask = "69b2",
+ add_sub_cella_17.operation_mode = "arithmetic",
+ add_sub_cella_17.sum_lutc_input = "cin",
+ add_sub_cella_17.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_18
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_17cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_18cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[18:18]),
+ .datab(wire_add_sub_cella_datab[18:18]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[18:18]));
+ defparam
+ add_sub_cella_18.cin_used = "true",
+ add_sub_cella_18.lut_mask = "69b2",
+ add_sub_cella_18.operation_mode = "arithmetic",
+ add_sub_cella_18.sum_lutc_input = "cin",
+ add_sub_cella_18.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_19
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_18cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_19cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[19:19]),
+ .datab(wire_add_sub_cella_datab[19:19]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[19:19]));
+ defparam
+ add_sub_cella_19.cin_used = "true",
+ add_sub_cella_19.lut_mask = "69b2",
+ add_sub_cella_19.operation_mode = "arithmetic",
+ add_sub_cella_19.sum_lutc_input = "cin",
+ add_sub_cella_19.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_20
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_19cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_20cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[20:20]),
+ .datab(wire_add_sub_cella_datab[20:20]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[20:20]));
+ defparam
+ add_sub_cella_20.cin_used = "true",
+ add_sub_cella_20.lut_mask = "69b2",
+ add_sub_cella_20.operation_mode = "arithmetic",
+ add_sub_cella_20.sum_lutc_input = "cin",
+ add_sub_cella_20.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_21
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_20cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_21cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[21:21]),
+ .datab(wire_add_sub_cella_datab[21:21]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[21:21]));
+ defparam
+ add_sub_cella_21.cin_used = "true",
+ add_sub_cella_21.lut_mask = "69b2",
+ add_sub_cella_21.operation_mode = "arithmetic",
+ add_sub_cella_21.sum_lutc_input = "cin",
+ add_sub_cella_21.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_22
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_21cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_22cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[22:22]),
+ .datab(wire_add_sub_cella_datab[22:22]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[22:22]));
+ defparam
+ add_sub_cella_22.cin_used = "true",
+ add_sub_cella_22.lut_mask = "69b2",
+ add_sub_cella_22.operation_mode = "arithmetic",
+ add_sub_cella_22.sum_lutc_input = "cin",
+ add_sub_cella_22.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_23
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_22cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_23cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[23:23]),
+ .datab(wire_add_sub_cella_datab[23:23]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[23:23]));
+ defparam
+ add_sub_cella_23.cin_used = "true",
+ add_sub_cella_23.lut_mask = "69b2",
+ add_sub_cella_23.operation_mode = "arithmetic",
+ add_sub_cella_23.sum_lutc_input = "cin",
+ add_sub_cella_23.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_24
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_23cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_24cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[24:24]),
+ .datab(wire_add_sub_cella_datab[24:24]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[24:24]));
+ defparam
+ add_sub_cella_24.cin_used = "true",
+ add_sub_cella_24.lut_mask = "69b2",
+ add_sub_cella_24.operation_mode = "arithmetic",
+ add_sub_cella_24.sum_lutc_input = "cin",
+ add_sub_cella_24.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_25
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_24cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_25cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[25:25]),
+ .datab(wire_add_sub_cella_datab[25:25]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[25:25]));
+ defparam
+ add_sub_cella_25.cin_used = "true",
+ add_sub_cella_25.lut_mask = "69b2",
+ add_sub_cella_25.operation_mode = "arithmetic",
+ add_sub_cella_25.sum_lutc_input = "cin",
+ add_sub_cella_25.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_26
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_25cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_26cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[26:26]),
+ .datab(wire_add_sub_cella_datab[26:26]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[26:26]));
+ defparam
+ add_sub_cella_26.cin_used = "true",
+ add_sub_cella_26.lut_mask = "69b2",
+ add_sub_cella_26.operation_mode = "arithmetic",
+ add_sub_cella_26.sum_lutc_input = "cin",
+ add_sub_cella_26.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_27
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_26cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_27cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[27:27]),
+ .datab(wire_add_sub_cella_datab[27:27]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[27:27]));
+ defparam
+ add_sub_cella_27.cin_used = "true",
+ add_sub_cella_27.lut_mask = "69b2",
+ add_sub_cella_27.operation_mode = "arithmetic",
+ add_sub_cella_27.sum_lutc_input = "cin",
+ add_sub_cella_27.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_28
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_27cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_28cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[28:28]),
+ .datab(wire_add_sub_cella_datab[28:28]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[28:28]));
+ defparam
+ add_sub_cella_28.cin_used = "true",
+ add_sub_cella_28.lut_mask = "69b2",
+ add_sub_cella_28.operation_mode = "arithmetic",
+ add_sub_cella_28.sum_lutc_input = "cin",
+ add_sub_cella_28.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_29
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_28cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_29cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[29:29]),
+ .datab(wire_add_sub_cella_datab[29:29]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[29:29]));
+ defparam
+ add_sub_cella_29.cin_used = "true",
+ add_sub_cella_29.lut_mask = "69b2",
+ add_sub_cella_29.operation_mode = "arithmetic",
+ add_sub_cella_29.sum_lutc_input = "cin",
+ add_sub_cella_29.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_30
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_29cout[0:0]),
+ .clk(clock),
+ .cout(wire_add_sub_cella_30cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[30:30]),
+ .datab(wire_add_sub_cella_datab[30:30]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[30:30]));
+ defparam
+ add_sub_cella_30.cin_used = "true",
+ add_sub_cella_30.lut_mask = "69b2",
+ add_sub_cella_30.operation_mode = "arithmetic",
+ add_sub_cella_30.sum_lutc_input = "cin",
+ add_sub_cella_30.lpm_type = "stratix_lcell";
+ stratix_lcell add_sub_cella_31
+ (
+ .aclr(aclr),
+ .cin(wire_add_sub_cella_30cout[0:0]),
+ .clk(clock),
+ .dataa(wire_add_sub_cella_dataa[31:31]),
+ .datab(wire_add_sub_cella_datab[31:31]),
+ .ena(clken),
+ .regout(wire_add_sub_cella_regout[31:31]));
+ defparam
+ add_sub_cella_31.cin_used = "true",
+ add_sub_cella_31.lut_mask = "6969",
+ add_sub_cella_31.operation_mode = "normal",
+ add_sub_cella_31.sum_lutc_input = "cin",
+ add_sub_cella_31.lpm_type = "stratix_lcell";
+ assign
+ wire_add_sub_cella_dataa = dataa,
+ wire_add_sub_cella_datab = datab;
+ assign
+ result = wire_add_sub_cella_regout;
+endmodule //sub32_add_sub_cqa
+//VALID FILE
+
+
+module sub32 (
+ dataa,
+ datab,
+ clock,
+ aclr,
+ clken,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [31:0] dataa;
+ input [31:0] datab;
+ input clock;
+ input aclr;
+ input clken;
+ output [31:0] result;
+
+ wire [31:0] sub_wire0;
+ wire [31:0] result = sub_wire0[31:0];
+
+ sub32_add_sub_cqa sub32_add_sub_cqa_component (
+ .dataa (dataa),
+ .datab (datab),
+ .clken (clken),
+ .aclr (aclr),
+ .clock (clock),
+ .result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC "32"
+// Retrieval info: PRIVATE: Function NUMERIC "1"
+// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Overflow NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "1"
+// Retrieval info: PRIVATE: aclr NUMERIC "1"
+// Retrieval info: PRIVATE: clken NUMERIC "1"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
diff --git a/megacells/sub32_bb.v b/megacells/sub32_bb.v
new file mode 100755
index 000000000..488ab51cf
--- /dev/null
+++ b/megacells/sub32_bb.v
@@ -0,0 +1,37 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module sub32 (
+ dataa,
+ datab,
+ clock,
+ aclr,
+ clken,
+ result)/* synthesis synthesis_clearbox = 1 */;
+
+ input [31:0] dataa;
+ input [31:0] datab;
+ input clock;
+ input aclr;
+ input clken;
+ output [31:0] result;
+
+endmodule
+
diff --git a/megacells/sub32_inst.v b/megacells/sub32_inst.v
new file mode 100755
index 000000000..1916fc524
--- /dev/null
+++ b/megacells/sub32_inst.v
@@ -0,0 +1,8 @@
+sub32 sub32_inst (
+ .dataa ( dataa_sig ),
+ .datab ( datab_sig ),
+ .clock ( clock_sig ),
+ .aclr ( aclr_sig ),
+ .clken ( clken_sig ),
+ .result ( result_sig )
+ );
diff --git a/models/bustri.v b/models/bustri.v
new file mode 100644
index 000000000..6e5a0f74c
--- /dev/null
+++ b/models/bustri.v
@@ -0,0 +1,17 @@
+
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+ enabledt,
+ tridata);
+
+ input [15:0] data;
+ input enabledt;
+ inout [15:0] tridata;
+
+ assign tridata = enabledt ? data :16'bz;
+
+endmodule // bustri
+
+
diff --git a/models/fifo.v b/models/fifo.v
new file mode 100644
index 000000000..a04e7da6c
--- /dev/null
+++ b/models/fifo.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 16;
+ parameter depth = 1024;
+ parameter addr_bits = 10;
+
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [width-1:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [width-1:0] q;
+ output rdfull;
+ output rdempty;
+ output reg [addr_bits-1:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output reg [addr_bits-1:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [addr_bits-1:0] rdptr;
+ reg [addr_bits-1:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_1k
+
diff --git a/models/fifo_1c_1k.v b/models/fifo_1c_1k.v
new file mode 100644
index 000000000..d11040b54
--- /dev/null
+++ b/models/fifo_1c_1k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 1024;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [9:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [9:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [9:0] rdusedw;
+ reg [9:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_1k
diff --git a/models/fifo_1c_2k.v b/models/fifo_1c_2k.v
new file mode 100644
index 000000000..5c3acfef5
--- /dev/null
+++ b/models/fifo_1c_2k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 2048;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [10:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [10:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [10:0] rdusedw;
+ reg [10:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+ assign wrempty = (wrusedw == 0);
+ assign wrfull = (wrusedw == depth-1);
+
+ assign rdempty = (rdusedw == 0);
+ assign rdfull = (rdusedw == depth-1);
+
+endmodule // fifo_1c_2k
diff --git a/models/fifo_1c_4k.v b/models/fifo_1c_4k.v
new file mode 100644
index 000000000..3e5ddd052
--- /dev/null
+++ b/models/fifo_1c_4k.v
@@ -0,0 +1,76 @@
+// Model of FIFO in Altera
+
+module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+ parameter width = 32;
+ parameter depth = 4096;
+ //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
+
+ input [31:0] data;
+ input wrreq;
+ input rdreq;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ output [31:0] q;
+ output rdfull;
+ output rdempty;
+ output [7:0] rdusedw;
+ output wrfull;
+ output wrempty;
+ output [7:0] wrusedw;
+
+ reg [width-1:0] mem [0:depth-1];
+ reg [7:0] rdptr;
+ reg [7:0] wrptr;
+
+`ifdef rd_req
+ reg [width-1:0] q;
+`else
+ wire [width-1:0] q;
+`endif
+
+ reg [7:0] rdusedw;
+ reg [7:0] wrusedw;
+
+ integer i;
+
+ always @( aclr)
+ begin
+ wrptr <= #1 0;
+ rdptr <= #1 0;
+ for(i=0;i<depth;i=i+1)
+ mem[i] <= #1 0;
+ end
+
+ always @(posedge wrclk)
+ if(wrreq)
+ begin
+ wrptr <= #1 wrptr+1;
+ mem[wrptr] <= #1 data;
+ end
+
+ always @(posedge rdclk)
+ if(rdreq)
+ begin
+ rdptr <= #1 rdptr+1;
+`ifdef rd_req
+ q <= #1 mem[rdptr];
+`endif
+ end
+
+`ifdef rd_req
+`else
+ assign q = mem[rdptr];
+`endif
+
+ // Fix these
+ always @(posedge wrclk)
+ wrusedw <= #1 wrptr - rdptr;
+
+ always @(posedge rdclk)
+ rdusedw <= #1 wrptr - rdptr;
+
+
+endmodule // fifo_1c_4k
diff --git a/models/fifo_1k.v b/models/fifo_1k.v
new file mode 100644
index 000000000..acfa4d176
--- /dev/null
+++ b/models/fifo_1k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_1k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [9:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [9:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/models/fifo_2k.v b/models/fifo_2k.v
new file mode 100644
index 000000000..50cd7811d
--- /dev/null
+++ b/models/fifo_2k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_2k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [10:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [10:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/models/fifo_4k.v b/models/fifo_4k.v
new file mode 100644
index 000000000..1fa4ba0a7
--- /dev/null
+++ b/models/fifo_4k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_4k
+ ( input [15:0] data,
+ input wrreq,
+ input rdreq,
+ input rdclk,
+ input wrclk,
+ input aclr,
+ output [15:0] q,
+ output rdfull,
+ output rdempty,
+ output [11:0] rdusedw,
+ output wrfull,
+ output wrempty,
+ output [11:0] wrusedw
+ );
+
+fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_1k
+
diff --git a/models/pll.v b/models/pll.v
new file mode 100644
index 000000000..d87964844
--- /dev/null
+++ b/models/pll.v
@@ -0,0 +1,33 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Very simple model for the PLL in the RX buffer
+
+module pll (inclk0,c0);
+
+ input inclk0;
+ output c0;
+
+ assign c0 = #9 inclk0;
+
+endmodule // pll
+
+
diff --git a/models/ssram.v b/models/ssram.v
new file mode 100644
index 000000000..fd7339970
--- /dev/null
+++ b/models/ssram.v
@@ -0,0 +1,38 @@
+
+// Model of Pipelined [ZBT] Synchronous SRAM
+
+module ssram(clock,addr,data,wen,ce);
+ parameter addrbits = 19;
+ parameter depth = 524288;
+
+ input clock;
+ input [addrbits-1:0] addr;
+ inout [35:0] data;
+ input wen;
+ input ce;
+
+ reg [35:0] ram [0:depth-1];
+
+ reg read_d1,read_d2;
+ reg write_d1,write_d2;
+ reg [addrbits-1:0] addr_d1,addr_d2;
+
+ always @(posedge clock)
+ begin
+ read_d1 <= #1 ce & ~wen;
+ write_d1 <= #1 ce & wen;
+ addr_d1 <= #1 addr;
+ read_d2 <= #1 read_d1;
+ write_d2 <= #1 write_d1;
+ addr_d2 <= #1 addr_d1;
+ if(write_d2)
+ ram[addr_d2] = data;
+ end // always @ (posedge clock)
+
+ data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
+
+ always @(posedge clock)
+ if(~ce & (write_d2 | write_d1 | wen))
+ $display("$time ERROR: RAM CE not asserted during write cycle");
+
+endmodule // ssram
diff --git a/rbf/Makefile.am b/rbf/Makefile.am
new file mode 100644
index 000000000..dbc2875fc
--- /dev/null
+++ b/rbf/Makefile.am
@@ -0,0 +1,49 @@
+#
+# Copyright 2005,2006 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+#
+
+include $(top_srcdir)/Makefile.common
+
+datadir = $(prefix)/share/usrp
+
+rbfs = \
+ rev2/std_2rxhb_2tx.rbf \
+ rev2/std_4rx_0tx.rbf \
+ rev4/std_2rxhb_2tx.rbf \
+ rev4/std_4rx_0tx.rbf \
+ rev2/multi_2rxhb_2tx.rbf \
+ rev4/multi_2rxhb_2tx.rbf
+
+
+EXTRA_DIST = \
+ $(rbfs)
+
+
+install-data-local:
+ @for file in $(rbfs); do \
+ echo "$(INSTALL_DATA) $(srcdir)/$$file $(DESTDIR)$(datadir)/$$file"; \
+ $(INSTALL_DATA) $(srcdir)/$$file $(DESTDIR)$(datadir)/$$file; \
+ done
+
+uninstall-local:
+ @for file in $(rbfs); do \
+ echo "$(RM) $(DESTDIR)$(datadir)/$$file"; \
+ $(RM) $(DESTDIR)$(datadir)/$$file; \
+ done
diff --git a/rbf/rev2/multi_2rxhb_2tx.rbf b/rbf/rev2/multi_2rxhb_2tx.rbf
new file mode 100755
index 000000000..2683d8641
--- /dev/null
+++ b/rbf/rev2/multi_2rxhb_2tx.rbf
Binary files differ
diff --git a/rbf/rev2/multi_4rx_0tx.rbf b/rbf/rev2/multi_4rx_0tx.rbf
new file mode 100755
index 000000000..b7e4eb393
--- /dev/null
+++ b/rbf/rev2/multi_4rx_0tx.rbf
Binary files differ
diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf
new file mode 100755
index 000000000..80f336c9d
--- /dev/null
+++ b/rbf/rev2/std_2rxhb_2tx.rbf
Binary files differ
diff --git a/rbf/rev2/std_4rx_0tx.rbf b/rbf/rev2/std_4rx_0tx.rbf
new file mode 100755
index 000000000..7dc16e24a
--- /dev/null
+++ b/rbf/rev2/std_4rx_0tx.rbf
Binary files differ
diff --git a/rbf/rev4/multi_2rxhb_2tx.rbf b/rbf/rev4/multi_2rxhb_2tx.rbf
new file mode 100755
index 000000000..2683d8641
--- /dev/null
+++ b/rbf/rev4/multi_2rxhb_2tx.rbf
Binary files differ
diff --git a/rbf/rev4/multi_4rx_0tx.rbf b/rbf/rev4/multi_4rx_0tx.rbf
new file mode 100755
index 000000000..b7e4eb393
--- /dev/null
+++ b/rbf/rev4/multi_4rx_0tx.rbf
Binary files differ
diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf
new file mode 100755
index 000000000..80f336c9d
--- /dev/null
+++ b/rbf/rev4/std_2rxhb_2tx.rbf
Binary files differ
diff --git a/rbf/rev4/std_4rx_0tx.rbf b/rbf/rev4/std_4rx_0tx.rbf
new file mode 100755
index 000000000..7dc16e24a
--- /dev/null
+++ b/rbf/rev4/std_4rx_0tx.rbf
Binary files differ
diff --git a/sdr_lib/adc_interface.v b/sdr_lib/adc_interface.v
new file mode 100644
index 000000000..f18ffc104
--- /dev/null
+++ b/sdr_lib/adc_interface.v
@@ -0,0 +1,71 @@
+
+
+`include "../../firmware/include/fpga_regs_common.v"
+`include "../../firmware/include/fpga_regs_standard.v"
+
+module adc_interface
+ (input clock, input reset, input enable,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
+ input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b,
+ output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3,
+ output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q,
+ output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q,
+ output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q,
+ output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q,
+ output wire [3:0] rx_numchan);
+
+ // Buffer at input to chip
+ reg [11:0] adc0,adc1,adc2,adc3;
+ always @(posedge clock)
+ begin
+ adc0 <= #1 rx_a_a;
+ adc1 <= #1 rx_b_a;
+ adc2 <= #1 rx_a_b;
+ adc3 <= #1 rx_b_b;
+ end
+
+ // then scale and subtract dc offset
+ wire [3:0] dco_en;
+ wire [15:0] adc0_corr,adc1_corr,adc2_corr,adc3_corr;
+
+ setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(dco_en));
+
+ rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+ rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3'b0}),.adc_out(adc1_corr),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+ rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3'b0}),.adc_out(adc2_corr),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+ rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3'b0}),.adc_out(adc3_corr),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+ // Level sensing for AGC
+ rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16]));
+ rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16]));
+ rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16]));
+ rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16]));
+
+ // And mux to the appropriate outputs
+ wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
+ wire rx_realsignals;
+
+ setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
+ .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
+ assign rx_numchan[0] = 1'b0;
+
+ always @(posedge clock)
+ begin
+ ddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr);
+ ddc0_in_q <= #1 rx_realsignals ? 16'd0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr);
+ ddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr);
+ ddc1_in_q <= #1 rx_realsignals ? 16'd0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr);
+ ddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr);
+ ddc2_in_q <= #1 rx_realsignals ? 16'd0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr);
+ ddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr);
+ ddc3_in_q <= #1 rx_realsignals ? 16'd0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr);
+ end
+
+endmodule // adc_interface
+
+
diff --git a/sdr_lib/bidir_reg.v b/sdr_lib/bidir_reg.v
new file mode 100644
index 000000000..b12441252
--- /dev/null
+++ b/sdr_lib/bidir_reg.v
@@ -0,0 +1,29 @@
+// Bidirectional registers
+
+module bidir_reg
+ ( inout wire [15:0] tristate,
+ input wire [15:0] oe,
+ input wire [15:0] reg_val );
+
+ // This would be much cleaner if all the tools
+ // supported "for generate"........
+
+ assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
+ assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
+ assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
+ assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
+ assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
+ assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
+ assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
+ assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
+ assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
+ assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
+ assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
+ assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
+ assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
+ assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
+ assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
+ assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
+
+endmodule // bidir_reg
+
diff --git a/sdr_lib/bus_interface.v b/sdr_lib/bus_interface.v
new file mode 100755
index 000000000..3f5f748d5
--- /dev/null
+++ b/sdr_lib/bus_interface.v
@@ -0,0 +1,213 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes. Each fifo line is 4 bytes
+// Fifo has 1024 or 2048 lines
+
+module bus_interface
+ ( input usbclk,
+ input reset,
+ inout [15:0] usbdata, // TRISTATE
+ input wire [5:0] usbctl,
+ output wire [5:0] usbrdy,
+ output [31:0] txdata,
+ input [31:0] rxdata,
+ input txclk,
+ input txstrobe,
+ input rxclk,
+ input rxstrobe,
+ output [11:0] debugbus,
+ input clear_status
+ );
+
+ parameter IN_CHANNELS = 1;
+ parameter OUT_CHANNELS = 1;
+ parameter bitmask = (IN_CHANNELS*2)-1;
+
+ wire have_space, have_pkt_rdy;
+ wire WR, RD, OE;
+ reg tx_underrun, rx_overrun;
+
+ assign WR = usbctl[0];
+ assign RD = usbctl[1];
+ assign OE = usbctl[2];
+
+ assign usbrdy[0] = have_space;
+ assign usbrdy[1] = have_pkt_rdy;
+ assign usbrdy[2] = tx_underrun;
+ assign usbrdy[3] = rx_overrun;
+
+ reg [IN_CHANNELS*2*16-1:0] fifo_in;
+ wire [OUT_CHANNELS*2*16-1:0] fifo_out;
+
+ wire [15:0] usbdata_in = usbdata;
+
+ reg select_out;
+ reg select_in;
+
+ reg commit;
+ reg rd_next;
+ reg [15:0] usbdata_out;
+ wire [10:0] txfifolevel,rxfifolevel;
+ reg [8:0] write_count;
+ wire tx_empty;
+ wire tx_full;
+ wire rx_empty;
+ wire rx_full;
+ wire [31:0] txd;
+ wire rdreq;
+
+ // Tri-state bus macro
+ bustri bustri(.data(usbdata_out),
+ .enabledt(OE),
+ .tridata(usbdata) );
+
+ //////////////////////////////////////////////
+ // TX Side (USB --> DAC)
+ always @(posedge usbclk, posedge reset)
+ begin
+ if(reset)
+ begin
+ fifo_in <= #1 0;
+ write_count <= #1 0;
+ end
+ else
+ if(WR & ~write_count[8])
+ begin
+ case(write_count[0])
+ 1'b0 : fifo_in[31:16] <= #1 usbdata_in; // I
+ 1'b1 : fifo_in[15:0] <= #1 usbdata_in; // Q
+ endcase
+ write_count <= #1 write_count + 9'd1;
+ end
+ else
+ write_count <= #1 WR ? write_count : 9'b0;
+ end
+
+ always @(posedge usbclk)
+ if(reset)
+ commit <= #1 1'b0;
+ else
+ if(write_count[0] && ~write_count[8] && WR)
+ commit <= #1 1'b1;
+ else
+ commit <= #1 1'b0;
+
+ assign rdreq = txstrobe & !tx_empty;
+ assign txdata = tx_empty ? 32'b0 : txd;
+
+ always @(posedge txclk)
+ if(reset)
+ tx_underrun <= 1'b0;
+ else if(txstrobe & tx_empty)
+ tx_underrun <= 1'b1;
+ else if(clear_status)
+ tx_underrun <= 1'b0;
+
+ fifo_1c_2k txfifo (.data ( fifo_in ),
+ .wrreq ( commit ),
+ .wrclk ( usbclk ),
+
+ .q ( txd ),
+ .rdreq ( rdreq),
+ .rdclk ( txclk ),
+
+ .aclr ( reset ),
+
+ .rdempty ( tx_empty ),
+ .rdusedw ( ),
+ .wrfull ( tx_full ),
+ .wrusedw ( txfifolevel )
+ );
+
+ assign have_space = (txfifolevel <= (2048-128));
+
+ //////////////////////////////
+ // Receive FIFO (ADC --> USB)
+
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rxstrobe & rx_full)
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ always @(select_out, fifo_out)
+ case(select_out)
+ 0 : usbdata_out = fifo_out[31:16]; // I
+ 1 : usbdata_out = fifo_out[15:0]; // Q
+ endcase
+
+/*
+ always @(posedge usbclk, posedge reset)
+ if(reset)
+ usbdata_out <= #1 16'b0;
+ else
+ if(select_out)
+ usbdata_out = fifo_out[31:16];
+ else
+ usbdata_out = fifo_out[15:0];
+ */
+
+ always @(negedge usbclk, posedge reset)
+ if(reset)
+ select_out <= #1 1'b0;
+ else if(~RD)
+ select_out <= #1 1'b0;
+ else
+ select_out <= #1 ~select_out;
+
+ fifo_1c_2k rxfifo (.data ( rxdata ), // counter ),
+ .wrreq (rxstrobe & ~rx_full ),
+ .wrclk ( rxclk ),
+
+ .q ( fifo_out ),
+ .rdreq ( select_out ),// & RD ), // FIXME
+ .rdclk ( usbclk ),
+
+ .aclr ( reset ),
+
+ .rdempty ( rx_empty ),
+ .rdusedw ( rxfifolevel ),
+ .wrfull ( rx_full ),
+ .wrusedw ( )
+ );
+
+ assign have_pkt_rdy = (rxfifolevel >= 128);
+
+ // Debugging Aids
+ assign debugbus[0] = tx_underrun;
+ assign debugbus[1] = rx_overrun;
+ assign debugbus[2] = tx_empty;
+ assign debugbus[3] = tx_full;
+ assign debugbus[4] = rx_empty;
+ assign debugbus[5] = rx_full;
+ assign debugbus[6] = txstrobe;
+ assign debugbus[7] = rxstrobe;
+ assign debugbus[8] = select_out;
+ assign debugbus[9] = rxstrobe & ~rx_full;
+ assign debugbus[10] = have_space;
+ assign debugbus[11] = have_pkt_rdy;
+
+endmodule // bus_interface
+
diff --git a/sdr_lib/cic_decim.v b/sdr_lib/cic_decim.v
new file mode 100755
index 000000000..45b863f16
--- /dev/null
+++ b/sdr_lib/cic_decim.v
@@ -0,0 +1,106 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module cic_decim
+ ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
+ parameter bw = 16;
+ parameter N = 4;
+ parameter log2_of_max_rate = 8;
+ parameter maxbitgain = N * log2_of_max_rate;
+
+ input clock;
+ input reset;
+ input enable;
+ input [7:0] rate;
+ input strobe_in,strobe_out;
+ input [bw-1:0] signal_in;
+ output [bw-1:0] signal_out;
+ reg [bw-1:0] signal_out;
+
+ wire [bw+maxbitgain-1:0] signal_in_ext;
+ reg [bw+maxbitgain-1:0] integrator [0:N-1];
+ reg [bw+maxbitgain-1:0] differentiator [0:N-1];
+ reg [bw+maxbitgain-1:0] pipeline [0:N-1];
+ reg [bw+maxbitgain-1:0] sampler;
+
+ integer i;
+
+ sign_extend #(bw,bw+maxbitgain)
+ ext_input (.in(signal_in),.out(signal_in_ext));
+
+ always @(posedge clock)
+ if(reset)
+ for(i=0;i<N;i=i+1)
+ integrator[i] <= #1 0;
+ else if (enable && strobe_in)
+ begin
+ integrator[0] <= #1 integrator[0] + signal_in_ext;
+ for(i=1;i<N;i=i+1)
+ integrator[i] <= #1 integrator[i] + integrator[i-1];
+ end
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ sampler <= #1 0;
+ for(i=0;i<N;i=i+1)
+ begin
+ pipeline[i] <= #1 0;
+ differentiator[i] <= #1 0;
+ end
+ end
+ else if (enable && strobe_out)
+ begin
+ sampler <= #1 integrator[N-1];
+ differentiator[0] <= #1 sampler;
+ pipeline[0] <= #1 sampler - differentiator[0];
+ for(i=1;i<N;i=i+1)
+ begin
+ differentiator[i] <= #1 pipeline[i-1];
+ pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+ end
+ end // if (enable && strobe_out)
+
+ wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
+
+ // Output Scaling to same width as input
+ function [2:0] log_ceil;
+ input [7:0] val;
+ log_ceil = val[6] ? 3'd7 : val[5] ? 3'd6 : val[4] ? 3'd5 :
+ val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
+ endfunction // log_ceil
+
+ wire [2:0] shift = log_ceil(rate);
+
+ always @*
+ case(shift)
+ 3'd2 : signal_out = signal_out_unnorm[2*N+bw-1:2*N]; // Decim by 4
+ 3'd3 : signal_out = signal_out_unnorm[3*N+bw-1:3*N];
+ 3'd4 : signal_out = signal_out_unnorm[4*N+bw-1:4*N];
+ 3'd5 : signal_out = signal_out_unnorm[5*N+bw-1:5*N];
+ 3'd6 : signal_out = signal_out_unnorm[6*N+bw-1:6*N];
+ 3'd7 : signal_out = signal_out_unnorm[7*N+bw-1:7*N];
+ default : signal_out = signal_out_unnorm[7*N+bw-1:7*N];
+ endcase // case(shift)
+
+endmodule // cic_decim
+
diff --git a/sdr_lib/cic_int_shifter.v b/sdr_lib/cic_int_shifter.v
new file mode 100644
index 000000000..112d8712b
--- /dev/null
+++ b/sdr_lib/cic_int_shifter.v
@@ -0,0 +1,98 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module cic_int_shifter(rate,signal_in,signal_out);
+ parameter bw = 16;
+ parameter N = 4;
+ parameter log2_of_max_rate = 7;
+ parameter maxbitgain = (N-1)*log2_of_max_rate;
+
+ input [7:0] rate;
+ input wire [bw+maxbitgain-1:0] signal_in;
+ output reg [bw-1:0] signal_out;
+
+ function [2:0] log_ceil;
+ input [7:0] val;
+ log_ceil = val[6] ? 3'd7 : val[5] ? 3'd6 : val[4] ? 3'd5 :
+ val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
+ endfunction // log_ceil
+
+ function [4:0] bitgain;
+ input [7:0] rate;
+ case(rate)
+ 8'd4 : bitgain = 2*(N-1);
+ 8'd8 : bitgain = 3*(N-1);
+ 8'd16 : bitgain = 4*(N-1);
+ 8'd32 : bitgain = 5*(N-1);
+ 8'd64 : bitgain = 6*(N-1);
+ 8'd128 : bitgain = 7*(N-1);
+
+ 8'd5 : bitgain = 7;
+ 8'd6 : bitgain = 8;
+ 8'd7 : bitgain = 9;
+ 8'd9,8'd10 : bitgain = 10;
+ 8'd12 : bitgain = 11;
+ 8'd13,8'd14,8'd15 : bitgain = 12;
+ 8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
+ 8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
+ 8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
+ 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
+ 8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
+ 8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
+ 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
+ 8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
+
+ default : bitgain = 21;
+ endcase // case(rate)
+ endfunction // bitgain
+
+ wire [4:0] shift = bitgain(rate+1);
+
+ // We should be able to do this, but can't ....
+ // assign signal_out = signal_in[shift+bw-1:shift];
+
+ always @*
+ case(shift)
+ 5'd6 : signal_out = signal_in[6+bw-1:6];
+ 5'd9 : signal_out = signal_in[9+bw-1:9];
+ 5'd12 : signal_out = signal_in[12+bw-1:12];
+ 5'd15 : signal_out = signal_in[15+bw-1:15];
+ 5'd18 : signal_out = signal_in[18+bw-1:18];
+ 5'd21 : signal_out = signal_in[21+bw-1:21];
+
+ 5'd7 : signal_out = signal_in[7+bw-1:7];
+ 5'd8 : signal_out = signal_in[8+bw-1:8];
+ 5'd10 : signal_out = signal_in[10+bw-1:10];
+ 5'd11 : signal_out = signal_in[11+bw-1:11];
+ 5'd13 : signal_out = signal_in[13+bw-1:13];
+ 5'd14 : signal_out = signal_in[14+bw-1:14];
+ 5'd16 : signal_out = signal_in[16+bw-1:16];
+ 5'd17 : signal_out = signal_in[17+bw-1:17];
+ 5'd19 : signal_out = signal_in[19+bw-1:19];
+ 5'd20 : signal_out = signal_in[20+bw-1:20];
+
+
+ default : signal_out = signal_in[21+bw-1:21];
+ endcase // case(shift)
+
+endmodule // cic_int_shifter
+
diff --git a/sdr_lib/cic_interp.v b/sdr_lib/cic_interp.v
new file mode 100755
index 000000000..43ab17d3b
--- /dev/null
+++ b/sdr_lib/cic_interp.v
@@ -0,0 +1,88 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
+ parameter bw = 16;
+ parameter N = 4;
+ parameter log2_of_max_rate = 7;
+ parameter maxbitgain = (N-1)*log2_of_max_rate;
+
+ input clock;
+ input reset;
+ input enable;
+ input [7:0] rate;
+ input strobe_in,strobe_out;
+ input [bw-1:0] signal_in;
+ wire [bw-1:0] signal_in;
+ output [bw-1:0] signal_out;
+ wire [bw-1:0] signal_out;
+
+ wire [bw+maxbitgain-1:0] signal_in_ext;
+ reg [bw+maxbitgain-1:0] integrator [0:N-1];
+ reg [bw+maxbitgain-1:0] differentiator [0:N-1];
+ reg [bw+maxbitgain-1:0] pipeline [0:N-1];
+
+ integer i;
+
+ sign_extend #(bw,bw+maxbitgain)
+ ext_input (.in(signal_in),.out(signal_in_ext));
+
+ //FIXME Note that this section has pipe and diff reversed
+ // It still works, but is confusing
+ always @(posedge clock)
+ if(reset)
+ for(i=0;i<N;i=i+1)
+ integrator[i] <= #1 0;
+ else if (enable & strobe_out)
+ begin
+ if(strobe_in)
+ integrator[0] <= #1 integrator[0] + pipeline[N-1];
+ for(i=1;i<N;i=i+1)
+ integrator[i] <= #1 integrator[i] + integrator[i-1];
+ end
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ for(i=0;i<N;i=i+1)
+ begin
+ differentiator[i] <= #1 0;
+ pipeline[i] <= #1 0;
+ end
+ end
+ else if (enable && strobe_in)
+ begin
+ differentiator[0] <= #1 signal_in_ext;
+ pipeline[0] <= #1 signal_in_ext - differentiator[0];
+ for(i=1;i<N;i=i+1)
+ begin
+ differentiator[i] <= #1 pipeline[i-1];
+ pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+ end
+ end
+
+ wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
+
+ cic_int_shifter cic_int_shifter(rate,signal_out_unnorm,signal_out);
+
+endmodule // cic_interp
+
diff --git a/sdr_lib/clk_divider.v b/sdr_lib/clk_divider.v
new file mode 100755
index 000000000..a687297b4
--- /dev/null
+++ b/sdr_lib/clk_divider.v
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
+ reg [7:0] counter;
+
+ // FIXME maybe should use PLL or switch to double edge version
+
+ always @(posedge in_clk or posedge reset)
+ if(reset)
+ counter <= #1 8'd0;
+ else if(counter == 0)
+ counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
+ else
+ counter <= #1 counter-8'd1;
+
+ always @(posedge in_clk or posedge reset)
+ if(reset)
+ out_clk <= #1 1'b0;
+ else if(counter == 0)
+ out_clk <= #1 ~out_clk;
+
+endmodule // clk_divider
+
diff --git a/sdr_lib/cordic.v b/sdr_lib/cordic.v
new file mode 100755
index 000000000..8c8c0ab0d
--- /dev/null
+++ b/sdr_lib/cordic.v
@@ -0,0 +1,109 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+ parameter bitwidth = 16;
+ parameter zwidth = 16;
+
+ input clock;
+ input reset;
+ input enable;
+ input [bitwidth-1:0] xi, yi;
+ output [bitwidth-1:0] xo, yo;
+ input [zwidth-1:0] zi;
+ output [zwidth-1:0] zo;
+
+ reg [bitwidth+1:0] x0,y0;
+ reg [zwidth-2:0] z0;
+ wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
+ wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
+ wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
+
+ wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+ wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+ // Compute consts. Would be easier if vlog had atan...
+ // see gen_cordic_consts.py
+
+`define c00 16'd8192
+`define c01 16'd4836
+`define c02 16'd2555
+`define c03 16'd1297
+`define c04 16'd651
+`define c05 16'd326
+`define c06 16'd163
+`define c07 16'd81
+`define c08 16'd41
+`define c09 16'd20
+`define c10 16'd10
+`define c11 16'd5
+`define c12 16'd3
+`define c13 16'd1
+`define c14 16'd1
+`define c15 16'd0
+`define c16 16'd0
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
+ end
+ else// if(enable)
+ begin
+ z0 <= #1 zi[zwidth-2:0];
+ case (zi[zwidth-1:zwidth-2])
+ 2'b00, 2'b11 :
+ begin
+ x0 <= #1 xi_ext;
+ y0 <= #1 yi_ext;
+ end
+ 2'b01, 2'b10 :
+ begin
+ x0 <= #1 -xi_ext;
+ y0 <= #1 -yi_ext;
+ end
+ endcase // case(zi[zwidth-1:zwidth-2])
+ end // else: !if(reset)
+
+ // FIXME need to handle variable number of stages
+ // FIXME should be able to narrow zwidth but quartus makes it bigger...
+ // This would be easier if arrays worked better in vlog...
+ cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
+ cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
+ cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
+ cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
+ cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
+ cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
+ cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
+ cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
+ cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
+ cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
+ cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
+ cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
+
+ assign xo = x12[bitwidth:1];
+ assign yo = y12[bitwidth:1];
+ //assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
+ //assign yo = y12[bitwidth+1:2];
+ assign zo = z12;
+
+endmodule // cordic
+
diff --git a/sdr_lib/cordic_stage.v b/sdr_lib/cordic_stage.v
new file mode 100755
index 000000000..c9c0ef9a3
--- /dev/null
+++ b/sdr_lib/cordic_stage.v
@@ -0,0 +1,60 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
+ parameter bitwidth = 16;
+ parameter zwidth = 16;
+ parameter shift = 1;
+
+ input clock;
+ input reset;
+ input enable;
+ input [bitwidth-1:0] xi,yi;
+ input [zwidth-1:0] zi;
+ input [zwidth-1:0] constant;
+ output [bitwidth-1:0] xo,yo;
+ output [zwidth-1:0] zo;
+
+ wire z_is_pos = ~zi[zwidth-1];
+
+ reg [bitwidth-1:0] xo,yo;
+ reg [zwidth-1:0] zo;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ xo <= #1 0;
+ yo <= #1 0;
+ zo <= #1 0;
+ end
+ else //if(enable)
+ begin
+ xo <= #1 z_is_pos ?
+ xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
+ xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
+ yo <= #1 z_is_pos ?
+ yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
+ yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
+ zo <= #1 z_is_pos ?
+ zi - constant :
+ zi + constant;
+ end
+endmodule
diff --git a/sdr_lib/ddc.v b/sdr_lib/ddc.v
new file mode 100755
index 000000000..48bca9a79
--- /dev/null
+++ b/sdr_lib/ddc.v
@@ -0,0 +1,97 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+// DDC block
+
+module ddc(input clock,
+ input reset,
+ input enable,
+ input [3:0] rate1,
+ input [3:0] rate2,
+ output strobe,
+ input [31:0] freq,
+ input [15:0] i_in,
+ input [15:0] q_in,
+ output [15:0] i_out,
+ output [15:0] q_out
+ );
+ parameter bw = 16;
+ parameter zw = 16;
+
+ wire [15:0] i_cordic_out, q_cordic_out;
+ wire [31:0] phase;
+
+ wire strobe1, strobe2;
+ reg [3:0] strobe_ctr1,strobe_ctr2;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ strobe_ctr2 <= #1 4'd0;
+ else if(strobe2)
+ strobe_ctr2 <= #1 4'd0;
+ else
+ strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ strobe_ctr1 <= #1 4'd0;
+ else if(strobe1)
+ strobe_ctr1 <= #1 4'd0;
+ else if(strobe2)
+ strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+
+
+ assign strobe2 = enable & ( strobe_ctr2 == rate2 );
+ assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+ assign strobe = strobe1;
+
+ function [2:0] log_ceil;
+ input [3:0] val;
+
+ log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
+ endfunction
+
+ wire [2:0] shift1 = log_ceil(rate1);
+ wire [2:0] shift2 = log_ceil(rate2);
+
+ cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+ cordic(.clock(clock), .reset(reset), .enable(enable),
+ .xi(i_in), .yi(q_in), .zi(phase[31:32-zw]),
+ .xo(i_cordic_out), .yo(q_cordic_out), .zo() );
+
+ cic_decim_2stage #(.bw(bw),.N(4))
+ decim_i(.clock(clock),.reset(reset),.enable(enable),
+ .strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+ .signal_in(i_cordic_out),.signal_out(i_out));
+
+ cic_decim_2stage #(.bw(bw),.N(4))
+ decim_q(.clock(clock),.reset(reset),.enable(enable),
+ .strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+ .signal_in(q_cordic_out),.signal_out(q_out));
+
+ phase_acc #(.resolution(32))
+ nco (.clk(clock),.reset(reset),.enable(enable),
+ .freq(freq),.phase(phase));
+
+endmodule
diff --git a/sdr_lib/dpram.v b/sdr_lib/dpram.v
new file mode 100644
index 000000000..5c38decce
--- /dev/null
+++ b/sdr_lib/dpram.v
@@ -0,0 +1,47 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
+ parameter depth = 4;
+ parameter width = 16;
+ parameter size = 16;
+
+ input wclk;
+ input [width-1:0] wdata;
+ input [depth-1:0] waddr;
+ input wen;
+
+ input rclk;
+ output reg [width-1:0] rdata;
+ input [depth-1:0] raddr;
+
+ reg [width-1:0] ram [0:size-1];
+
+ always @(posedge wclk)
+ if(wen)
+ ram[waddr] <= #1 wdata;
+
+ always @(posedge rclk)
+ rdata <= #1 ram[raddr];
+
+endmodule // dpram
diff --git a/sdr_lib/duc.v b/sdr_lib/duc.v
new file mode 100755
index 000000000..780fc9f23
--- /dev/null
+++ b/sdr_lib/duc.v
@@ -0,0 +1,95 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// DUC block
+
+module duc(input clock,
+ input reset,
+ input enable,
+ input [3:0] rate1,
+ input [3:0] rate2,
+ output strobe,
+ input [31:0] freq,
+ input [15:0] i_in,
+ input [15:0] q_in,
+ output [15:0] i_out,
+ output [15:0] q_out
+ );
+ parameter bw = 16;
+ parameter zw = 16;
+
+ wire [15:0] i_interp_out, q_interp_out;
+ wire [31:0] phase;
+
+ wire strobe1, strobe2;
+ reg [3:0] strobe_ctr1,strobe_ctr2;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ strobe_ctr2 <= #1 4'd0;
+ else if(strobe2)
+ strobe_ctr2 <= #1 4'd0;
+ else
+ strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ strobe_ctr1 <= #1 4'd0;
+ else if(strobe1)
+ strobe_ctr1 <= #1 4'd0;
+ else if(strobe2)
+ strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+
+
+ assign strobe2 = enable & ( strobe_ctr2 == rate2 );
+ assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+ assign strobe = strobe1;
+
+ function [2:0] log_ceil;
+ input [3:0] val;
+
+ log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
+ endfunction
+
+ wire [2:0] shift1 = log_ceil(rate1);
+ wire [2:0] shift2 = log_ceil(rate2);
+
+ cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+ cordic(.clock(clock), .reset(reset), .enable(enable),
+ .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
+ .xo(i_out), .yo(q_out), .zo() );
+
+ cic_interp_2stage #(.bw(bw),.N(4))
+ interp_i(.clock(clock),.reset(reset),.enable(enable),
+ .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+ .signal_in(i_in),.signal_out(i_interp_out));
+
+ cic_interp_2stage #(.bw(bw),.N(4))
+ interp_q(.clock(clock),.reset(reset),.enable(enable),
+ .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+ .signal_in(q_in),.signal_out(q_interp_out));
+
+ phase_acc #(.resolution(32))
+ nco (.clk(clock),.reset(reset),.enable(enable),
+ .freq(freq),.phase(phase));
+
+endmodule
diff --git a/sdr_lib/ext_fifo.v b/sdr_lib/ext_fifo.v
new file mode 100644
index 000000000..dfe1f2fe7
--- /dev/null
+++ b/sdr_lib/ext_fifo.v
@@ -0,0 +1,126 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// Vendor Independent FIFO module
+// Width and Depth should be parameterizable
+// Asynchronous clocks for each side
+// Read side is read-acknowledge, not read-request
+// FIFO does not enforce "don't write when full, don't read when empty"
+// That is up to the connecting modules
+// The FIFO only holds 2^N-1 entries, not 2^N
+
+module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
+ parameter width=32;
+ parameter depth=10;
+
+ input reset; // Asynchronous
+ input [width-1:0] data;
+ input write;
+ input wrclk;
+ output [depth-1:0] wr_used;
+ output [width-1:0] q;
+ input read_ack;
+ input rdclk;
+ output [depth-1:0] rd_used;
+
+ reg [depth-1:0] read_addr, write_addr,
+ read_addr_gray, read_addr_gray_sync,
+ write_addr_gray, write_addr_gray_sync;
+
+ // Pseudo-dual-port RAM
+ dpram #(.depth(10),.width(width),.size(1024))
+ fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
+ .rclk(rdclk), .rdata(q),.raddr(read_addr) );
+
+ wire [depth-1:0] wag,rag;
+
+ // Keep track of own side's pointer
+ always @(posedge wrclk or posedge reset)
+ if(reset) write_addr <= #1 0;
+ else if(write) write_addr <= #1 write_addr + 1;
+
+ always @(posedge rdclk or posedge reset)
+ if(reset) read_addr <= #1 0;
+ else if(read_ack) read_addr <= #1 read_addr + 1;
+
+ // Convert own side pointer to gray
+ bin2gray #(depth) write_b2g (write_addr,wag);
+ bin2gray #(depth) read_b2g (read_addr,rag);
+
+ // Latch it
+ always @(posedge wrclk or posedge reset)
+ if(reset) write_addr_gray <= #1 0;
+ else write_addr_gray <= #1 wag;
+
+ always @(posedge rdclk or posedge reset)
+ if(reset) read_addr_gray <= #1 0;
+ else read_addr_gray <= #1 rag;
+
+ // Send it to other side and latch
+ always @(posedge wrclk or posedge reset)
+ if(reset) read_addr_gray_sync <= #1 0;
+ else read_addr_gray_sync <= #1 read_addr_gray;
+
+ always @(posedge rdclk or posedge reset)
+ if(reset) write_addr_gray_sync <= #1 0;
+ else write_addr_gray_sync <= #1 write_addr_gray;
+
+ wire [depth-1:0] write_addr_sync, read_addr_sync;
+
+ // Convert back to binary
+ gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
+ gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
+
+ assign rd_used = write_addr_sync - read_addr;
+ assign wr_used = write_addr - read_addr_sync;
+
+endmodule // fifo
+
+module bin2gray(bin_val,gray_val);
+ parameter width = 8;
+ input [width-1:0] bin_val;
+ output reg [width-1:0] gray_val;
+
+ integer i;
+
+ always @*
+ begin
+ gray_val[width-1] = bin_val[width-1];
+ for(i=0;i<width-1;i=i+1)
+ gray_val[i] = bin_val[i] ^ bin_val[i+1];
+ end
+endmodule // bin2gray
+
+module gray2bin(gray_val,bin_val);
+ parameter width = 8;
+ input [width-1:0] gray_val;
+ output reg [width-1:0] bin_val;
+
+ integer i;
+
+ always @*
+ begin
+ bin_val[width-1] = gray_val[width-1];
+ for(i=width-2;i>=0;i=i-1)
+ bin_val[i] = bin_val[i+1] ^ gray_val[i];
+ end
+endmodule // gray2bin
diff --git a/sdr_lib/gen_cordic_consts.py b/sdr_lib/gen_cordic_consts.py
new file mode 100755
index 000000000..ab66cfe01
--- /dev/null
+++ b/sdr_lib/gen_cordic_consts.py
@@ -0,0 +1,10 @@
+#!/usr/bin/env python
+
+import math
+
+zwidth = 16
+
+for i in range(17):
+ c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth)
+ print "`define c%02d %d'd%d" % (i, zwidth, round (c))
+
diff --git a/sdr_lib/gen_sync.v b/sdr_lib/gen_sync.v
new file mode 100644
index 000000000..d72b39d56
--- /dev/null
+++ b/sdr_lib/gen_sync.v
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module gen_sync
+ ( input clock,
+ input reset,
+ input enable,
+ input [7:0] rate,
+ output wire sync );
+
+// parameter width = 8;
+
+ reg [7:0] counter;
+ assign sync = |(((rate+1)>>1)& counter);
+
+ always @(posedge clock)
+ if(reset || ~enable)
+ counter <= #1 0;
+ else if(counter == rate)
+ counter <= #1 0;
+ else
+ counter <= #1 counter + 8'd1;
+
+endmodule // gen_sync
+
diff --git a/sdr_lib/hb/acc.v b/sdr_lib/hb/acc.v
new file mode 100644
index 000000000..195d5ea94
--- /dev/null
+++ b/sdr_lib/hb/acc.v
@@ -0,0 +1,22 @@
+
+
+module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
+ input signed [30:0] addend, output reg signed [33:0] sum );
+
+ always @(posedge clock)
+ if(reset)
+ sum <= #1 34'd0;
+ //else if(clear & enable_in)
+ // sum <= #1 addend;
+ //else if(clear)
+ // sum <= #1 34'd0;
+ else if(clear)
+ sum <= #1 addend;
+ else if(enable_in)
+ sum <= #1 sum + addend;
+
+ always @(posedge clock)
+ enable_out <= #1 enable_in;
+
+endmodule // acc
+
diff --git a/sdr_lib/hb/coeff_ram.v b/sdr_lib/hb/coeff_ram.v
new file mode 100644
index 000000000..65460822f
--- /dev/null
+++ b/sdr_lib/hb/coeff_ram.v
@@ -0,0 +1,26 @@
+
+
+module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data);
+
+ always @(posedge clock)
+ case (rd_addr)
+ 4'd0 : rd_data <= #1 -16'd16;
+ 4'd1 : rd_data <= #1 16'd74;
+ 4'd2 : rd_data <= #1 -16'd254;
+ 4'd3 : rd_data <= #1 16'd669;
+ 4'd4 : rd_data <= #1 -16'd1468;
+ 4'd5 : rd_data <= #1 16'd2950;
+ 4'd6 : rd_data <= #1 -16'd6158;
+ 4'd7 : rd_data <= #1 16'd20585;
+ 4'd8 : rd_data <= #1 16'd20585;
+ 4'd9 : rd_data <= #1 -16'd6158;
+ 4'd10 : rd_data <= #1 16'd2950;
+ 4'd11 : rd_data <= #1 -16'd1468;
+ 4'd12 : rd_data <= #1 16'd669;
+ 4'd13 : rd_data <= #1 -16'd254;
+ 4'd14 : rd_data <= #1 16'd74;
+ 4'd15 : rd_data <= #1 -16'd16;
+ default : rd_data <= #1 16'd0;
+ endcase // case(rd_addr)
+
+endmodule // ram
diff --git a/sdr_lib/hb/coeff_rom.v b/sdr_lib/hb/coeff_rom.v
new file mode 100644
index 000000000..c287eaaad
--- /dev/null
+++ b/sdr_lib/hb/coeff_rom.v
@@ -0,0 +1,19 @@
+
+
+module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
+
+ always @(posedge clock)
+ case (addr)
+ 3'd0 : data <= #1 -16'd16;
+ 3'd1 : data <= #1 16'd74;
+ 3'd2 : data <= #1 -16'd254;
+ 3'd3 : data <= #1 16'd669;
+ 3'd4 : data <= #1 -16'd1468;
+ 3'd5 : data <= #1 16'd2950;
+ 3'd6 : data <= #1 -16'd6158;
+ 3'd7 : data <= #1 16'd20585;
+ endcase // case(addr)
+
+endmodule // coeff_rom
+
+
diff --git a/sdr_lib/hb/halfband_decim.v b/sdr_lib/hb/halfband_decim.v
new file mode 100644
index 000000000..2a05ce52c
--- /dev/null
+++ b/sdr_lib/hb/halfband_decim.v
@@ -0,0 +1,163 @@
+/* -*- verilog -*-
+ *
+ * USRP - Universal Software Radio Peripheral
+ *
+ * Copyright (C) 2005 Matt Ettus
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * This implements a 31-tap halfband filter that decimates by two.
+ * The coefficients are symmetric, and with the exception of the middle tap,
+ * every other coefficient is zero. The middle section of taps looks like this:
+ *
+ * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ...
+ * |
+ * middle tap -------+
+ *
+ * See coeff_rom.v for the full set. The taps are scaled relative to 32768,
+ * thus the middle tap equals 1.0. Not counting the middle tap, there are 8
+ * non-zero taps on each side, and they are symmetric. A naive implementation
+ * requires a mulitply for each non-zero tap. Because of symmetry, we can
+ * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output
+ * sample, we need to perform 8 multiplications. Since the middle tap is 1.0,
+ * we just add the corresponding delay line value.
+ *
+ * About timing: We implement this with a single multiplier, so it takes
+ * 8 cycles to compute a single output. However, since we're decimating by two
+ * we can accept a new input value every 4 cycles. strobe_in is asserted when
+ * there's a new input sample available. Depending on the overall decimation
+ * rate, strobe_in may be asserted less frequently than once every 4 clocks.
+ * On the output side, we assert strobe_out when output contains a new sample.
+ *
+ * Implementation: Every time strobe_in is asserted we store the new data into
+ * the delay line. We split the delay line into two components, one for the
+ * even samples, and one for the odd samples. ram16_odd is the delay line for
+ * the odd samples. This ram is written on each odd assertion of strobe_in, and
+ * is read on each clock when we're computing the dot product. ram16_even is
+ * similar, although because it holds the even samples we must be able to read
+ * two samples from different addresses at the same time, while writing the incoming
+ * even samples. Thus it's "triple-ported".
+ */
+
+module halfband_decim
+ (input clock, input reset, input enable, input strobe_in, output wire strobe_out,
+ input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);
+
+ reg [3:0] rd_addr1;
+ reg [3:0] rd_addr2;
+ reg [3:0] phase;
+ reg [3:0] base_addr;
+
+ wire signed [15:0] mac_out,middle_data, sum, coeff;
+ wire signed [30:0] product;
+ wire signed [33:0] sum_even;
+ wire clear;
+ reg store_odd;
+
+ always @(posedge clock)
+ if(reset)
+ store_odd <= #1 1'b0;
+ else
+ if(strobe_in)
+ store_odd <= #1 ~store_odd;
+
+ wire start = strobe_in & store_odd;
+ always @(posedge clock)
+ if(reset)
+ base_addr <= #1 4'd0;
+ else if(start)
+ base_addr <= #1 base_addr + 4'd1;
+
+ always @(posedge clock)
+ if(reset)
+ phase <= #1 4'd8;
+ else if (start)
+ phase <= #1 4'd0;
+ else if(phase != 4'd8)
+ phase <= #1 phase + 4'd1;
+
+ reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
+ always @(posedge clock)
+ begin
+ start_d1 <= #1 start;
+ start_d2 <= #1 start_d1;
+ start_d3 <= #1 start_d2;
+ start_d4 <= #1 start_d3;
+ start_d5 <= #1 start_d4;
+ start_d6 <= #1 start_d5;
+ start_d7 <= #1 start_d6;
+ start_d8 <= #1 start_d7;
+ start_d9 <= #1 start_d8;
+ start_dA <= #1 start_d9;
+ start_dB <= #1 start_dA;
+ start_dC <= #1 start_dB;
+ start_dD <= #1 start_dC;
+ end // always @ (posedge clock)
+
+ reg mult_en, mult_en_pre;
+ always @(posedge clock)
+ begin
+ mult_en_pre <= #1 phase!=8;
+ mult_en <= #1 mult_en_pre;
+ end
+
+ assign clear = start_d4; // was dC
+ wire latch_result = start_d4; // was dC
+ assign strobe_out = start_d5; // was dD
+ wire acc_en;
+
+ always @*
+ case(phase[2:0])
+ 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
+ 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end
+ 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end
+ 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end
+ 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end
+ 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end
+ 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end
+ 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end
+ default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
+ endcase // case(phase)
+
+ coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff));
+
+ ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
+ .wr_addr(base_addr),.wr_data(data_in),
+ .rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
+ .sum(sum));
+
+ ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items
+ .wr_addr(base_addr),.wr_data(data_in),
+ //.rd_addr(base_addr+4'd7),.rd_data(middle_data));
+ .rd_addr(base_addr+4'd6),.rd_data(middle_data));
+
+ mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));
+
+ acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
+ .clear(clear),.addend(product),.sum(sum_even));
+
+ wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!!
+
+ always @(posedge clock)
+ if(reset)
+ data_out <= #1 16'd0;
+ else if(latch_result)
+ data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);
+
+ assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
+
+endmodule // halfband_decim
diff --git a/sdr_lib/hb/halfband_interp.v b/sdr_lib/hb/halfband_interp.v
new file mode 100644
index 000000000..cdb11c1f6
--- /dev/null
+++ b/sdr_lib/hb/halfband_interp.v
@@ -0,0 +1,121 @@
+
+
+module halfband_interp
+ (input clock, input reset, input enable,
+ input strobe_in, input strobe_out,
+ input [15:0] signal_in_i, input [15:0] signal_in_q,
+ output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
+ output wire [12:0] debug);
+
+ wire [15:0] coeff_ram_out;
+ wire [15:0] data_ram_out_i;
+ wire [15:0] data_ram_out_q;
+
+ wire [3:0] data_rd_addr;
+ reg [3:0] data_wr_addr;
+ reg [2:0] coeff_rd_addr;
+
+ wire filt_done;
+
+ wire [15:0] mac_out_i;
+ wire [15:0] mac_out_q;
+ reg [15:0] delayed_middle_i, delayed_middle_q;
+ wire [7:0] shift = 8'd9;
+
+ reg stb_out_happened;
+
+ wire [15:0] data_ram_out_i_b;
+
+ always @(posedge clock)
+ if(strobe_in)
+ stb_out_happened <= #1 1'b0;
+ else if(strobe_out)
+ stb_out_happened <= #1 1'b1;
+
+assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
+
+ wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
+ wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
+
+/* always @(posedge clock)
+ if(reset)
+ begin
+ signal_out_i <= #1 16'd0;
+ signal_out_q <= #1 16'd0;
+ end
+ else if(strobe_in)
+ begin
+ signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
+ signal_out_q <= #1 delayed_middle_q;
+ end
+ //else if(filt_done&stb_out_happened)
+ else if(stb_out_happened)
+ begin
+ signal_out_i <= #1 mac_out_i;
+ signal_out_q <= #1 mac_out_q;
+ end
+*/
+
+ always @(posedge clock)
+ if(reset)
+ coeff_rd_addr <= #1 3'd0;
+ else if(coeff_rd_addr != 3'd0)
+ coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
+ else if(strobe_in)
+ coeff_rd_addr <= #1 3'd1;
+
+ reg filt_done_d1;
+ always@(posedge clock)
+ filt_done_d1 <= #1 filt_done;
+
+ always @(posedge clock)
+ if(reset)
+ data_wr_addr <= #1 4'd0;
+ //else if(strobe_in)
+ else if(filt_done & ~filt_done_d1)
+ data_wr_addr <= #1 data_wr_addr + 4'd1;
+
+ always @(posedge clock)
+ if(coeff_rd_addr == 3'd7)
+ begin
+ delayed_middle_i <= #1 data_ram_out_i_b;
+ // delayed_middle_q <= #1 data_ram_out_q_b;
+ end
+
+// always @(posedge clock)
+// if(reset)
+// data_rd_addr <= #1 4'd0;
+// else if(strobe_in)
+// data_rd_addr <= #1 data_wr_addr + 4'd1;
+// else if(!filt_done)
+// data_rd_addr <= #1 data_rd_addr + 4'd1;
+// else
+// data_rd_addr <= #1 data_wr_addr;
+
+ wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
+ wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
+// always @(posedge clock)
+// if(reset)
+// filt_done <= #1 1'b1;
+// else if(strobe_in)
+ // filt_done <= #1 1'b0;
+// else if(coeff_rd_addr == 4'd0)
+// filt_done <= #1 1'b1;
+
+ assign filt_done = (coeff_rd_addr == 3'd0);
+
+ coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
+
+ ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
+ .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
+
+ ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
+ .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
+
+ mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+ .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
+
+ mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+ .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
+
+endmodule // halfband_interp
diff --git a/sdr_lib/hb/hbd_tb/HBD b/sdr_lib/hb/hbd_tb/HBD
new file mode 100644
index 000000000..574fbba91
--- /dev/null
+++ b/sdr_lib/hb/hbd_tb/HBD
@@ -0,0 +1,80 @@
+*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+test_hbd.clock
+test_hbd.reset
+@420
+test_hbd.halfband_decim.middle_data[15:0]
+@22
+test_hbd.halfband_decim.sum_even[33:0]
+test_hbd.halfband_decim.base_addr[3:0]
+@420
+test_hbd.i_in[15:0]
+@24
+test_hbd.halfband_decim.phase[3:0]
+test_hbd.halfband_decim.ram16_even.rd_addr1[3:0]
+test_hbd.halfband_decim.ram16_even.rd_addr2[3:0]
+test_hbd.halfband_decim.ram16_even.wr_addr[3:0]
+test_hbd.halfband_decim.ram16_even.wr_data[15:0]
+@28
+test_hbd.halfband_decim.ram16_even.write
+@420
+test_hbd.halfband_decim.sum[15:0]
+test_hbd.halfband_decim.product[30:0]
+test_hbd.halfband_decim.dout[33:0]
+test_hbd.halfband_decim.sum_even[33:0]
+@22
+test_hbd.halfband_decim.acc.addend[30:0]
+@28
+test_hbd.halfband_decim.acc.reset
+@420
+test_hbd.halfband_decim.acc.sum[33:0]
+test_hbd.halfband_decim.mult.x[15:0]
+test_hbd.halfband_decim.mult.y[15:0]
+@28
+test_hbd.halfband_decim.acc.clear
+test_hbd.strobe_in
+test_hbd.strobe_out
+test_hbd.halfband_decim.acc_en
+@420
+test_hbd.i_out[15:0]
+@28
+test_hbd.halfband_decim.mult_en
+test_hbd.halfband_decim.latch_result
+@420
+test_hbd.halfband_decim.sum[15:0]
+test_hbd.halfband_decim.sum_even[33:0]
+test_hbd.halfband_decim.dout[33:0]
+test_hbd.halfband_decim.data_out[15:0]
+@22
+test_hbd.halfband_decim.data_out[15:0]
+@28
+test_hbd.halfband_decim.dout[33:0]
+@29
+test_hbd.halfband_decim.acc_en
+@22
+test_hbd.halfband_decim.base_addr[3:0]
+@28
+test_hbd.halfband_decim.clear
+test_hbd.halfband_decim.latch_result
+test_hbd.halfband_decim.mult_en
+test_hbd.halfband_decim.mult_en_pre
+@22
+test_hbd.halfband_decim.phase[3:0]
+@28
+test_hbd.halfband_decim.start
+test_hbd.halfband_decim.start_d1
+test_hbd.halfband_decim.start_d2
+test_hbd.halfband_decim.start_d3
+test_hbd.halfband_decim.start_d4
+test_hbd.halfband_decim.start_d5
+test_hbd.halfband_decim.start_d6
+test_hbd.halfband_decim.start_d7
+test_hbd.halfband_decim.start_d8
+test_hbd.halfband_decim.start_d9
+test_hbd.halfband_decim.start_dA
+test_hbd.halfband_decim.start_dB
+test_hbd.halfband_decim.start_dC
+test_hbd.halfband_decim.start_dD
+test_hbd.halfband_decim.store_odd
+test_hbd.halfband_decim.strobe_in
+test_hbd.halfband_decim.strobe_out
diff --git a/sdr_lib/hb/hbd_tb/really_golden b/sdr_lib/hb/hbd_tb/really_golden
new file mode 100644
index 000000000..2d24a9e14
--- /dev/null
+++ b/sdr_lib/hb/hbd_tb/really_golden
@@ -0,0 +1,142 @@
+VCD info: dumpfile test_hbd.vcd opened for output.
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ x
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8192
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+- 4
+ 18
+- 63
+ 167
+- 367
+ 737
+- 1539
+ 5146
+ 5146
+- 1539
+ 737
+- 367
+ 167
+- 63
+ 18
+- 4
+ 0
+ 0
+ 0
+ 0
+ 0
+- 4
+ 14
+- 49
+ 118
+- 249
+ 488
+ 7141
+12287
+17433
+15894
+16631
+16264
+16432
+16368
+16387
+16383
+16383
+16383
+16383
+16383
+16387
+16368
+16432
+16264
+16631
+15894
+ 9241
+ 4095
+- 1051
+ 488
+- 249
+ 118
+- 49
+ 14
+- 4
+ 0
+ 0
+ 0
+ 0
+ 0
+- 4
+ 14
+- 49
+ 118
+- 249
+ 488
+- 1051
+12287
+17433
+15894
+16631
+16264
+16432
+16368
+16387
+16383
+16383
+16383
+16383
+16383
+16387
+16368
+16432
+16264
+16631
+15894
+17433
+ 4095
+- 1051
+ 488
+- 249
+ 118
+- 49
+ 14
+- 4
+ 0
+ 0
+ 0
+ 0
diff --git a/sdr_lib/hb/hbd_tb/regression b/sdr_lib/hb/hbd_tb/regression
new file mode 100644
index 000000000..fc279c2f2
--- /dev/null
+++ b/sdr_lib/hb/hbd_tb/regression
@@ -0,0 +1,95 @@
+echo "Baseline 1000"
+iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden
+diff golden really_golden
+
+echo
+echo "Test 100"
+iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 50"
+iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 40"
+iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 30"
+iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 25"
+iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 20"
+iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 19"
+iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 18"
+iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 17"
+iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 16"
+iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 15"
+iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 14"
+iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 13"
+iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 12"
+iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 11"
+iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 10"
+iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 9"
+iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 8"
+iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 7"
+iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 6"
+iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 5"
+iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 4"
+iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 3"
+iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden
diff --git a/sdr_lib/hb/hbd_tb/run_hbd b/sdr_lib/hb/hbd_tb/run_hbd
new file mode 100755
index 000000000..b8aec7574
--- /dev/null
+++ b/sdr_lib/hb/hbd_tb/run_hbd
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y .. -o test_hbd test_hbd.v
+./test_hbd
diff --git a/sdr_lib/hb/hbd_tb/test_hbd.v b/sdr_lib/hb/hbd_tb/test_hbd.v
new file mode 100644
index 000000000..01ab5e7e0
--- /dev/null
+++ b/sdr_lib/hb/hbd_tb/test_hbd.v
@@ -0,0 +1,75 @@
+
+
+module test_hbd();
+
+ reg clock;
+ initial clock = 1'b0;
+ always #5 clock <= ~clock;
+
+ reg reset;
+ initial reset = 1'b1;
+ initial #1000 reset = 1'b0;
+
+ initial $dumpfile("test_hbd.vcd");
+ initial $dumpvars(0,test_hbd);
+
+ reg [15:0] i_in, q_in;
+ wire [15:0] i_out, q_out;
+
+ reg strobe_in;
+ wire strobe_out;
+ reg coeff_write;
+ reg [15:0] coeff_data;
+ reg [4:0] coeff_addr;
+
+ halfband_decim halfband_decim
+ ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
+ .data_in(i_in),.data_out(i_out) );
+
+ always @(posedge strobe_out)
+ if(i_out[15])
+ $display("-%d",65536-i_out);
+ else
+ $display("%d",i_out);
+
+ initial
+ begin
+ strobe_in = 1'b0;
+ @(negedge reset);
+ @(posedge clock);
+ while(1)
+ begin
+ strobe_in <= #1 1'b1;
+ @(posedge clock);
+ strobe_in <= #1 1'b0;
+ repeat (`RATE)
+ @(posedge clock);
+ end
+ end
+
+ initial #10000000 $finish; // Just in case...
+
+ initial
+ begin
+ i_in <= #1 16'd0;
+ repeat (40) @(posedge strobe_in);
+ i_in <= #1 16'd16384;
+ @(posedge strobe_in);
+ i_in <= #1 16'd0;
+ repeat (40) @(posedge strobe_in);
+ i_in <= #1 16'd16384;
+ @(posedge strobe_in);
+ i_in <= #1 16'd0;
+ repeat (40) @(posedge strobe_in);
+ i_in <= #1 16'd16384;
+ repeat (40) @(posedge strobe_in);
+ i_in <= #1 16'd0;
+ repeat (41) @(posedge strobe_in);
+ i_in <= #1 16'd16384;
+ repeat (40) @(posedge strobe_in);
+ i_in <= #1 16'd0;
+ repeat (40) @(posedge strobe_in);
+ repeat (7) @(posedge clock);
+ $finish;
+ end // initial begin
+endmodule // test_hb
diff --git a/sdr_lib/hb/mac.v b/sdr_lib/hb/mac.v
new file mode 100644
index 000000000..5a270bc73
--- /dev/null
+++ b/sdr_lib/hb/mac.v
@@ -0,0 +1,58 @@
+
+
+module mac (input clock, input reset, input enable, input clear,
+ input signed [15:0] x, input signed [15:0] y,
+ input [7:0] shift, output [15:0] z );
+
+ reg signed [30:0] product;
+ reg signed [39:0] z_int;
+ reg signed [15:0] z_shift;
+
+ reg enable_d1;
+ always @(posedge clock)
+ enable_d1 <= #1 enable;
+
+ always @(posedge clock)
+ if(reset | clear)
+ z_int <= #1 40'd0;
+ else if(enable_d1)
+ z_int <= #1 z_int + {{9{product[30]}},product};
+
+ always @(posedge clock)
+ product <= #1 x*y;
+
+ always @* // FIXME full case? parallel case?
+ case(shift)
+ //8'd0 : z_shift <= z_int[39:24];
+ //8'd1 : z_shift <= z_int[38:23];
+ //8'd2 : z_shift <= z_int[37:22];
+ //8'd3 : z_shift <= z_int[36:21];
+ //8'd4 : z_shift <= z_int[35:20];
+ //8'd5 : z_shift <= z_int[34:19];
+ 8'd6 : z_shift <= z_int[33:18];
+ 8'd7 : z_shift <= z_int[32:17];
+ 8'd8 : z_shift <= z_int[31:16];
+ 8'd9 : z_shift <= z_int[30:15];
+ 8'd10 : z_shift <= z_int[29:14];
+ 8'd11 : z_shift <= z_int[28:13];
+ //8'd12 : z_shift <= z_int[27:12];
+ //8'd13 : z_shift <= z_int[26:11];
+ //8'd14 : z_shift <= z_int[25:10];
+ //8'd15 : z_shift <= z_int[24:9];
+ //8'd16 : z_shift <= z_int[23:8];
+ //8'd17 : z_shift <= z_int[22:7];
+ //8'd18 : z_shift <= z_int[21:6];
+ //8'd19 : z_shift <= z_int[20:5];
+ //8'd20 : z_shift <= z_int[19:4];
+ //8'd21 : z_shift <= z_int[18:3];
+ //8'd22 : z_shift <= z_int[17:2];
+ //8'd23 : z_shift <= z_int[16:1];
+ //8'd24 : z_shift <= z_int[15:0];
+ default : z_shift <= z_int[15:0];
+ endcase // case(shift)
+
+ // FIXME do we need to saturate?
+ //assign z = z_shift;
+ assign z = z_int[15:0];
+
+endmodule // mac
diff --git a/sdr_lib/hb/mult.v b/sdr_lib/hb/mult.v
new file mode 100644
index 000000000..a8d4cb1b7
--- /dev/null
+++ b/sdr_lib/hb/mult.v
@@ -0,0 +1,16 @@
+
+
+module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
+ input enable_in, output reg enable_out );
+
+ always @(posedge clock)
+ if(enable_in)
+ product <= #1 x*y;
+ else
+ product <= #1 31'd0;
+
+ always @(posedge clock)
+ enable_out <= #1 enable_in;
+
+endmodule // mult
+
diff --git a/sdr_lib/hb/ram16_2port.v b/sdr_lib/hb/ram16_2port.v
new file mode 100644
index 000000000..e1761a926
--- /dev/null
+++ b/sdr_lib/hb/ram16_2port.v
@@ -0,0 +1,22 @@
+
+
+module ram16_2port (input clock, input write,
+ input [3:0] wr_addr, input [15:0] wr_data,
+ input [3:0] rd_addr1, output reg [15:0] rd_data1,
+ input [3:0] rd_addr2, output reg [15:0] rd_data2);
+
+ reg [15:0] ram_array [0:31];
+
+ always @(posedge clock)
+ rd_data1 <= #1 ram_array[rd_addr1];
+
+ always @(posedge clock)
+ rd_data2 <= #1 ram_array[rd_addr2];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram16_2port
+
+
diff --git a/sdr_lib/hb/ram16_2sum.v b/sdr_lib/hb/ram16_2sum.v
new file mode 100644
index 000000000..559b06fd5
--- /dev/null
+++ b/sdr_lib/hb/ram16_2sum.v
@@ -0,0 +1,27 @@
+
+
+module ram16_2sum (input clock, input write,
+ input [3:0] wr_addr, input [15:0] wr_data,
+ input [3:0] rd_addr1, input [3:0] rd_addr2,
+ output reg [15:0] sum);
+
+ reg signed [15:0] ram_array [0:15];
+ reg signed [15:0] a,b;
+ wire signed [16:0] sum_int;
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+ always @(posedge clock)
+ begin
+ a <= #1 ram_array[rd_addr1];
+ b <= #1 ram_array[rd_addr2];
+ end
+
+ assign sum_int = {a[15],a} + {b[15],b};
+
+ always @(posedge clock)
+ sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+endmodule // ram16_2sum
diff --git a/sdr_lib/hb/ram32_2sum.v b/sdr_lib/hb/ram32_2sum.v
new file mode 100644
index 000000000..d1f55b7d0
--- /dev/null
+++ b/sdr_lib/hb/ram32_2sum.v
@@ -0,0 +1,22 @@
+
+
+module ram32_2sum (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr1, input [4:0] rd_addr2,
+ output reg [15:0] sum);
+
+ reg [15:0] ram_array [0:31];
+ wire [16:0] sum_int;
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+ assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
+
+ always @(posedge clock)
+ sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+
+endmodule // ram32_2sum
+
diff --git a/sdr_lib/io_pins.v b/sdr_lib/io_pins.v
new file mode 100644
index 000000000..da20b3b03
--- /dev/null
+++ b/sdr_lib/io_pins.v
@@ -0,0 +1,52 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2005,2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+`include "../../firmware/include/fpga_regs_common.v"
+`include "../../firmware/include/fpga_regs_standard.v"
+
+module io_pins
+ ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
+ input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
+ input clock, input rx_reset, input tx_reset,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
+
+ reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
+
+ bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
+ bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
+ bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2));
+ bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3));
+
+ // Upper 16 bits are mask for lower 16
+ always @(posedge clock)
+ if(serial_strobe)
+ case(serial_addr)
+ `FR_OE_0 : io_0_oe
+ <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_OE_1 : io_1_oe
+ <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_OE_2 : io_2_oe
+ <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_OE_3 : io_3_oe
+ <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ endcase // case(serial_addr)
+
+endmodule // io_pins
diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v
new file mode 100644
index 000000000..d42817c72
--- /dev/null
+++ b/sdr_lib/master_control.v
@@ -0,0 +1,155 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003,2005 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Clock, enable, and reset controls for whole system
+
+module master_control
+ ( input master_clk, input usbclk,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
+ output tx_bus_reset, output rx_bus_reset,
+ output wire tx_dsp_reset, output wire rx_dsp_reset,
+ output wire enable_tx, output wire enable_rx,
+ output wire [7:0] interp_rate, output wire [7:0] decim_rate,
+ output tx_sample_strobe, output strobe_interp,
+ output rx_sample_strobe, output strobe_decim,
+ input tx_empty,
+ input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
+ output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
+ );
+
+ // FIXME need a separate reset for all control settings
+ // Master Controls assignments
+ wire [7:0] master_controls;
+ setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
+ assign enable_tx = master_controls[0];
+ assign enable_rx = master_controls[1];
+ assign tx_dsp_reset = master_controls[2];
+ assign rx_dsp_reset = master_controls[3];
+ // Unused - 4-7
+
+ // Strobe Generators
+ setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
+ setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
+
+ strobe_gen da_strobe_gen
+ ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
+ .rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
+
+ strobe_gen tx_strobe_gen
+ ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
+ .rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
+
+ assign rx_sample_strobe = 1'b1;
+
+ strobe_gen decim_strobe_gen
+ ( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
+ .rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
+
+ // Reset syncs for bus (usbclk) side
+ // The RX bus side reset isn't used, the TX bus side one may not be needed
+ reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
+
+ always @(posedge usbclk)
+ begin
+ tx_reset_bus_sync1 <= #1 tx_dsp_reset;
+ rx_reset_bus_sync1 <= #1 rx_dsp_reset;
+ tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
+ rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
+ end
+
+ assign tx_bus_reset = tx_reset_bus_sync2;
+ assign rx_bus_reset = rx_reset_bus_sync2;
+
+ wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
+ wire txaclk,txbclk,rxaclk,rxbclk;
+ wire [3:0] debug_en, txcvr_ctrl;
+
+ wire [31:0] txcvr_rxlines, txcvr_txlines;
+
+ setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
+ setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
+ setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
+ setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
+
+ setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
+
+ clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
+ clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
+ clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
+ clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
+
+ reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
+ // Upper 16 bits are mask for lower 16
+ always @(posedge master_clk)
+ if(serial_strobe)
+ case(serial_addr)
+ `FR_IO_0 : io_0_reg
+ <= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_IO_1 : io_1_reg
+ <= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_IO_2 : io_2_reg
+ <= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ `FR_IO_3 : io_3_reg
+ <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+ endcase // case(serial_addr)
+
+ wire transmit_now = !tx_empty & enable_tx;
+ wire atr_ctl;
+ wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
+
+ setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
+ setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
+ setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
+
+ setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
+ setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
+ setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
+
+ setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
+ setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
+ setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
+
+ setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
+ setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
+ setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
+
+ //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
+ assign atr_ctl = 1'b1;
+
+ wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
+ wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
+
+ wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
+ wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
+
+ wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
+ wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
+
+ wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
+ wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
+
+ assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
+ assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
+ assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
+ assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
+
+
+endmodule // master_control
diff --git a/sdr_lib/master_control_multi.v b/sdr_lib/master_control_multi.v
new file mode 100644
index 000000000..af1e0b1f1
--- /dev/null
+++ b/sdr_lib/master_control_multi.v
@@ -0,0 +1,73 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+`include "usrp_multi.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+// Clock, enable, and reset controls for whole system
+// Modified version to enable multi_usrp synchronisation
+
+module master_control_multi
+ ( input master_clk, input usbclk,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
+ input wire rx_slave_sync,
+ output tx_bus_reset, output rx_bus_reset,
+ output wire tx_dsp_reset, output wire rx_dsp_reset,
+ output wire enable_tx, output wire enable_rx,
+ output wire sync_rx,
+ output wire [7:0] interp_rate, output wire [7:0] decim_rate,
+ output tx_sample_strobe, output strobe_interp,
+ output rx_sample_strobe, output strobe_decim,
+ input tx_empty,
+ input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
+ output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
+ );
+
+ wire [15:0] reg_1_std;
+
+ master_control master_control_standard
+ ( .master_clk(master_clk),.usbclk(usbclk),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ .debug_0(debug_0),.debug_1(debug_1),
+ .debug_2(debug_2),.debug_3(debug_3),
+ .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
+
+ // FIXME need a separate reset for all control settings
+ // Master/slave Controls assignments
+ wire [7:0] rx_master_slave_controls;
+ setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
+
+ assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
+ //sync if we are told by master_control or if we get a hardware slave sync
+ //TODO There can be a one sample difference between master and slave sync.
+ // Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
+ // Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
+ //TODO make output pin not hardwired
+assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
+
+
+endmodule // master_control
diff --git a/sdr_lib/phase_acc.v b/sdr_lib/phase_acc.v
new file mode 100755
index 000000000..d00716fd0
--- /dev/null
+++ b/sdr_lib/phase_acc.v
@@ -0,0 +1,52 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+// Basic Phase accumulator for DDS
+
+
+module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
+ parameter FREQADDR = 0;
+ parameter PHASEADDR = 0;
+ parameter resolution = 32;
+
+ input clk, reset, enable, strobe;
+ input [6:0] serial_addr;
+ input [31:0] serial_data;
+ input serial_strobe;
+
+ output reg [resolution-1:0] phase;
+ wire [resolution-1:0] freq;
+
+ setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
+
+ always @(posedge clk)
+ if(reset)
+ phase <= #1 32'b0;
+ else if(serial_strobe & (serial_addr == PHASEADDR))
+ phase <= #1 serial_data;
+ else if(enable & strobe)
+ phase <= #1 phase + freq;
+
+endmodule // phase_acc
+
+
diff --git a/sdr_lib/ram.v b/sdr_lib/ram.v
new file mode 100644
index 000000000..fb64cdeae
--- /dev/null
+++ b/sdr_lib/ram.v
@@ -0,0 +1,16 @@
+
+
+module ram (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:31];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram
diff --git a/sdr_lib/ram16.v b/sdr_lib/ram16.v
new file mode 100644
index 000000000..0c93da2be
--- /dev/null
+++ b/sdr_lib/ram16.v
@@ -0,0 +1,17 @@
+
+
+module ram16 (input clock, input write,
+ input [3:0] wr_addr, input [15:0] wr_data,
+ input [3:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:15];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram16
+
diff --git a/sdr_lib/ram32.v b/sdr_lib/ram32.v
new file mode 100644
index 000000000..064e2735a
--- /dev/null
+++ b/sdr_lib/ram32.v
@@ -0,0 +1,17 @@
+
+
+module ram32 (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:31];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram32
+
diff --git a/sdr_lib/ram64.v b/sdr_lib/ram64.v
new file mode 100644
index 000000000..084545808
--- /dev/null
+++ b/sdr_lib/ram64.v
@@ -0,0 +1,16 @@
+
+
+module ram64 (input clock, input write,
+ input [5:0] wr_addr, input [15:0] wr_data,
+ input [5:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:63];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram64
diff --git a/sdr_lib/rssi.v b/sdr_lib/rssi.v
new file mode 100644
index 000000000..e45e2148c
--- /dev/null
+++ b/sdr_lib/rssi.v
@@ -0,0 +1,30 @@
+
+
+module rssi (input clock, input reset, input enable,
+ input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
+
+ wire over_hi = (adc == 12'h7FF);
+ wire over_lo = (adc == 12'h800);
+ wire over = over_hi | over_lo;
+
+ reg [25:0] over_count_int;
+ always @(posedge clock)
+ if(reset | ~enable)
+ over_count_int <= #1 26'd0;
+ else
+ over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
+
+ assign over_count = over_count_int[25:10];
+
+ wire [11:0] abs_adc = adc[11] ? ~adc : adc;
+
+ reg [25:0] rssi_int;
+ always @(posedge clock)
+ if(reset | ~enable)
+ rssi_int <= #1 26'd0;
+ else
+ rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
+
+ assign rssi = rssi_int[25:10];
+
+endmodule // rssi
diff --git a/sdr_lib/rx_buffer.v b/sdr_lib/rx_buffer.v
new file mode 100644
index 000000000..70c800e3d
--- /dev/null
+++ b/sdr_lib/rx_buffer.v
@@ -0,0 +1,182 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes. Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+`include "../../firmware/include/fpga_regs_common.v"
+`include "../../firmware/include/fpga_regs_standard.v"
+
+module rx_buffer
+ ( input usbclk,
+ input bus_reset, // Not used in RX
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+ output [15:0] debugbus
+ );
+
+ wire [15:0] fifodata, fifodata_8;
+ reg [15:0] fifodata_16;
+
+ wire [11:0] rxfifolevel;
+ wire rx_empty, rx_full;
+
+ wire bypass_hb, want_q;
+ wire [4:0] bitwidth;
+ wire [3:0] bitshift;
+
+ setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({bypass_hb,want_q,bitwidth,bitshift}));
+
+ // Receive FIFO (ADC --> USB)
+
+ // 257 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rxstrobe & (store_next != 0))
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [3:0] store_next;
+ always @(posedge rxclk)
+ if(reset)
+ store_next <= #1 4'd0;
+ else if(rxstrobe & (store_next == 0))
+ store_next <= #1 4'd1;
+ else if(~rx_full & (store_next == channels))
+ store_next <= #1 4'd0;
+ else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1)))
+ store_next <= #1 4'd0;
+ else if(~rx_full & (store_next != 0))
+ store_next <= #1 store_next + 4'd1;
+
+ assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
+
+ assign fifodata_8 = {round_8(top),round_8(bottom)};
+ reg [15:0] top,bottom;
+
+ function [7:0] round_8;
+ input [15:0] in_val;
+
+ round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
+ endfunction // round_8
+
+ always @*
+ case(store_next)
+ 4'd1 : begin
+ bottom = ch_0;
+ top = ch_1;
+ end
+ 4'd2 : begin
+ bottom = ch_2;
+ top = ch_3;
+ end
+ 4'd3 : begin
+ bottom = ch_4;
+ top = ch_5;
+ end
+ 4'd4 : begin
+ bottom = ch_6;
+ top = ch_7;
+ end
+ default : begin
+ top = 16'hFFFF;
+ bottom = 16'hFFFF;
+ end
+ endcase // case(store_next)
+
+ always @*
+ case(store_next)
+ 4'd1 : fifodata_16 = ch_0;
+ 4'd2 : fifodata_16 = ch_1;
+ 4'd3 : fifodata_16 = ch_2;
+ 4'd4 : fifodata_16 = ch_3;
+ 4'd5 : fifodata_16 = ch_4;
+ 4'd6 : fifodata_16 = ch_5;
+ 4'd7 : fifodata_16 = ch_6;
+ 4'd8 : fifodata_16 = ch_7;
+ default : fifodata_16 = 16'hFFFF;
+ endcase // case(store_next)
+
+ fifo_4k rxfifo
+ ( .data ( fifodata ),
+ .wrreq (~rx_full & (store_next != 0)),
+ .wrclk ( rxclk ),
+
+ .q ( usbdata ),
+ .rdreq ( RD & ~read_count[8] ),
+ .rdclk ( ~usbclk ),
+
+ .aclr ( reset ), // This one is asynchronous, so we can use either reset
+
+ .rdempty ( rx_empty ),
+ .rdusedw ( rxfifolevel ),
+ .wrfull ( rx_full ),
+ .wrusedw ( )
+ );
+
+ assign have_pkt_rdy = (rxfifolevel >= 256);
+
+ // Debugging Aids
+ assign debugbus[0] = RD;
+ assign debugbus[1] = rx_overrun;
+ assign debugbus[2] = read_count[8];
+ assign debugbus[3] = rx_full;
+ assign debugbus[4] = rxstrobe;
+ assign debugbus[5] = usbclk;
+ assign debugbus[6] = have_pkt_rdy;
+ assign debugbus[10:7] = store_next;
+ //assign debugbus[15:11] = rxfifolevel[4:0];
+ assign debugbus[15:11] = bitwidth;
+
+endmodule // rx_buffer
+
diff --git a/sdr_lib/rx_chain.v b/sdr_lib/rx_chain.v
new file mode 100644
index 000000000..4031e6bfb
--- /dev/null
+++ b/sdr_lib/rx_chain.v
@@ -0,0 +1,105 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Following defines conditionally include RX path circuitry
+
+`include "usrp_std.vh"
+module rx_chain
+ (input clock,
+ input reset,
+ input enable,
+ input wire [7:0] decim_rate,
+ input sample_strobe,
+ input decimator_strobe,
+ output wire hb_strobe,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+ input wire [15:0] i_in,
+ input wire [15:0] q_in,
+ output wire [15:0] i_out,
+ output wire [15:0] q_out,
+ output wire [15:0] debugdata,output wire [15:0] debugctrl
+ );
+
+ parameter FREQADDR = 0;
+ parameter PHASEADDR = 0;
+
+ wire [31:0] phase;
+ wire [15:0] bb_i, bb_q;
+ wire [15:0] hb_in_i, hb_in_q;
+
+ assign debugdata = hb_in_i;
+
+`ifdef RX_NCO_ON
+ phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
+ (.clk(clock),.reset(reset),.enable(enable),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .strobe(sample_strobe),.phase(phase) );
+
+ cordic rx_cordic
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .xi(i_in),.yi(q_in),.zi(phase[31:16]),
+ .xo(bb_i),.yo(bb_q),.zo() );
+`else
+ assign bb_i = i_in;
+ assign bb_q = q_in;
+ assign sample_strobe = 1;
+`endif // !`ifdef RX_NCO_ON
+
+`ifdef RX_CIC_ON
+ cic_decim cic_decim_i_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_i),.signal_out(hb_in_i) );
+`else
+ assign hb_in_i = bb_i;
+ assign decimator_strobe = sample_strobe;
+`endif
+
+`ifdef RX_HB_ON
+ halfband_decim hbd_i_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .strobe_in(decimator_strobe),.strobe_out(hb_strobe),
+ .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
+`else
+ assign i_out = hb_in_i;
+ assign hb_strobe = decimator_strobe;
+`endif
+
+`ifdef RX_CIC_ON
+ cic_decim cic_decim_q_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_q),.signal_out(hb_in_q) );
+`else
+ assign hb_in_q = bb_q;
+`endif
+
+`ifdef RX_HB_ON
+ halfband_decim hbd_q_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .strobe_in(decimator_strobe),.strobe_out(),
+ .data_in(hb_in_q),.data_out(q_out) );
+`else
+ assign q_out = hb_in_q;
+`endif
+
+
+endmodule // rx_chain
diff --git a/sdr_lib/rx_chain_dual.v b/sdr_lib/rx_chain_dual.v
new file mode 100644
index 000000000..698859468
--- /dev/null
+++ b/sdr_lib/rx_chain_dual.v
@@ -0,0 +1,103 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module rx_chain_dual
+ (input clock,
+ input clock_2x,
+ input reset,
+ input enable,
+ input wire [7:0] decim_rate,
+ input sample_strobe,
+ input decimator_strobe,
+ input wire [31:0] freq0,
+ input wire [15:0] i_in0,
+ input wire [15:0] q_in0,
+ output wire [15:0] i_out0,
+ output wire [15:0] q_out0,
+ input wire [31:0] freq1,
+ input wire [15:0] i_in1,
+ input wire [15:0] q_in1,
+ output wire [15:0] i_out1,
+ output wire [15:0] q_out1
+ );
+
+ wire [15:0] phase;
+ wire [15:0] bb_i, bb_q;
+ wire [15:0] i_in, q_in;
+
+ wire [31:0] phase0;
+ wire [31:0] phase1;
+ reg [15:0] bb_i0, bb_q0;
+ reg [15:0] bb_i1, bb_q1;
+
+ // We want to time-share the CORDIC by double-clocking it
+
+ phase_acc rx_phase_acc_0
+ (.clk(clock),.reset(reset),.enable(enable),
+ .strobe(sample_strobe),.freq(freq0),.phase(phase0) );
+
+ phase_acc rx_phase_acc_1
+ (.clk(clock),.reset(reset),.enable(enable),
+ .strobe(sample_strobe),.freq(freq1),.phase(phase1) );
+
+ assign phase = clock ? phase0[31:16] : phase1[31:16];
+ assign i_in = clock ? i_in0 : i_in1;
+ assign q_in = clock ? q_in0 : q_in1;
+
+// This appears reversed because of the number of CORDIC stages
+ always @(posedge clock_2x)
+ if(clock)
+ begin
+ bb_i1 <= #1 bb_i;
+ bb_q1 <= #1 bb_q;
+ end
+ else
+ begin
+ bb_i0 <= #1 bb_i;
+ bb_q0 <= #1 bb_q;
+ end
+
+ cordic rx_cordic
+ ( .clock(clock_2x),.reset(reset),.enable(enable),
+ .xi(i_in),.yi(q_in),.zi(phase),
+ .xo(bb_i),.yo(bb_q),.zo() );
+
+ cic_decim cic_decim_i_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_i0),.signal_out(i_out0) );
+
+ cic_decim cic_decim_q_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_q0),.signal_out(q_out0) );
+
+ cic_decim cic_decim_i_1
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_i1),.signal_out(i_out1) );
+
+ cic_decim cic_decim_q_1
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+ .signal_in(bb_q1),.signal_out(q_out1) );
+
+endmodule // rx_chain
diff --git a/sdr_lib/rx_dcoffset.v b/sdr_lib/rx_dcoffset.v
new file mode 100644
index 000000000..3be475ed6
--- /dev/null
+++ b/sdr_lib/rx_dcoffset.v
@@ -0,0 +1,22 @@
+
+
+module rx_dcoffset (input clock, input enable, input reset,
+ input signed [15:0] adc_in, output signed [15:0] adc_out,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
+ parameter MYADDR = 0;
+
+ reg signed [31:0] integrator;
+ wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
+ assign adc_out = adc_in - scaled_integrator;
+
+ // FIXME do we need signed?
+ //FIXME What do we do when clipping?
+ always @(posedge clock)
+ if(reset)
+ integrator <= #1 32'd0;
+ else if(serial_strobe & (MYADDR == serial_addr))
+ integrator <= #1 {serial_data[15:0],16'd0};
+ else if(enable)
+ integrator <= #1 integrator + adc_out;
+
+endmodule // rx_dcoffset
diff --git a/sdr_lib/serial_io.v b/sdr_lib/serial_io.v
new file mode 100644
index 000000000..1fe43c959
--- /dev/null
+++ b/sdr_lib/serial_io.v
@@ -0,0 +1,118 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003,2004 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+// Serial Control Bus from Cypress chip
+
+module serial_io
+ ( input master_clk,
+ input serial_clock,
+ input serial_data_in,
+ input enable,
+ input reset,
+ inout wire serial_data_out,
+ output reg [6:0] serial_addr,
+ output reg [31:0] serial_data,
+ output wire serial_strobe,
+ input wire [31:0] readback_0,
+ input wire [31:0] readback_1,
+ input wire [31:0] readback_2,
+ input wire [31:0] readback_3,
+ input wire [31:0] readback_4,
+ input wire [31:0] readback_5,
+ input wire [31:0] readback_6,
+ input wire [31:0] readback_7
+ );
+
+ reg is_read;
+ reg [7:0] ser_ctr;
+ reg write_done;
+
+ assign serial_data_out = is_read ? serial_data[31] : 1'bz;
+
+ always @(posedge serial_clock, posedge reset, negedge enable)
+ if(reset)
+ ser_ctr <= #1 8'd0;
+ else if(~enable)
+ ser_ctr <= #1 8'd0;
+ else if(ser_ctr == 39)
+ ser_ctr <= #1 8'd0;
+ else
+ ser_ctr <= #1 ser_ctr + 8'd1;
+
+ always @(posedge serial_clock, posedge reset, negedge enable)
+ if(reset)
+ is_read <= #1 1'b0;
+ else if(~enable)
+ is_read <= #1 1'b0;
+ else if((ser_ctr == 7)&&(serial_addr[6]==1))
+ is_read <= #1 1'b1;
+
+ always @(posedge serial_clock, posedge reset)
+ if(reset)
+ begin
+ serial_addr <= #1 7'b0;
+ serial_data <= #1 32'b0;
+ write_done <= #1 1'b0;
+ end
+ else if(~enable)
+ begin
+ //serial_addr <= #1 7'b0;
+ //serial_data <= #1 32'b0;
+ write_done <= #1 1'b0;
+ end
+ else
+ begin
+ if(~is_read && (ser_ctr == 39))
+ write_done <= #1 1'b1;
+ else
+ write_done <= #1 1'b0;
+ if(is_read & (ser_ctr==8))
+ case (serial_addr)
+ 7'd1: serial_data <= #1 readback_0;
+ 7'd2: serial_data <= #1 readback_1;
+ 7'd3: serial_data <= #1 readback_2;
+ 7'd4: serial_data <= #1 readback_3;
+ 7'd5: serial_data <= #1 readback_4;
+ 7'd6: serial_data <= #1 readback_5;
+ 7'd7: serial_data <= #1 readback_6;
+ 7'd8: serial_data <= #1 readback_7;
+ default: serial_data <= #1 32'd0;
+ endcase // case(serial_addr)
+ else if(ser_ctr >= 8)
+ serial_data <= #1 {serial_data[30:0],serial_data_in};
+ else if(ser_ctr < 8)
+ serial_addr <= #1 {serial_addr[5:0],serial_data_in};
+ end // else: !if(~enable)
+
+ reg enable_d1, enable_d2;
+ always @(posedge master_clk)
+ begin
+ enable_d1 <= #1 enable;
+ enable_d2 <= #1 enable_d1;
+ end
+
+ assign serial_strobe = enable_d2 & ~enable_d1;
+
+endmodule // serial_io
+
+
diff --git a/sdr_lib/setting_reg.v b/sdr_lib/setting_reg.v
new file mode 100644
index 000000000..3d31a9efb
--- /dev/null
+++ b/sdr_lib/setting_reg.v
@@ -0,0 +1,23 @@
+
+
+module setting_reg
+ ( input clock, input reset, input strobe, input wire [6:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+ parameter my_addr = 0;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 in;
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg
diff --git a/sdr_lib/setting_reg_masked.v b/sdr_lib/setting_reg_masked.v
new file mode 100644
index 000000000..72f7e21eb
--- /dev/null
+++ b/sdr_lib/setting_reg_masked.v
@@ -0,0 +1,26 @@
+
+
+module setting_reg_masked
+ ( input clock, input reset, input strobe, input wire [6:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+/* upper 16 bits are mask, lower 16 bits are value
+ * Note that you get a 16 bit register, not a 32 bit one */
+
+ parameter my_addr = 0;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg_masked
diff --git a/sdr_lib/sign_extend.v b/sdr_lib/sign_extend.v
new file mode 100644
index 000000000..2417909bd
--- /dev/null
+++ b/sdr_lib/sign_extend.v
@@ -0,0 +1,35 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+ parameter bits_in=0; // FIXME Quartus insists on a default
+ parameter bits_out=0;
+
+ input [bits_in-1:0] in;
+ output [bits_out-1:0] out;
+
+ assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+
+endmodule
diff --git a/sdr_lib/strobe_gen.v b/sdr_lib/strobe_gen.v
new file mode 100644
index 000000000..0511b6a1d
--- /dev/null
+++ b/sdr_lib/strobe_gen.v
@@ -0,0 +1,44 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module strobe_gen
+ ( input clock,
+ input reset,
+ input enable,
+ input [7:0] rate,
+ input strobe_in,
+ output wire strobe );
+
+// parameter width = 8;
+
+ reg [7:0] counter;
+ assign strobe = ~|counter && enable && strobe_in;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ counter <= #1 8'd0;
+ else if(strobe_in)
+ if(counter == 0)
+ counter <= #1 rate;
+ else
+ counter <= #1 counter - 8'd1;
+
+endmodule // strobe_gen
diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v
new file mode 100644
index 000000000..cae6607b3
--- /dev/null
+++ b/sdr_lib/tx_buffer.v
@@ -0,0 +1,138 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes. Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+module tx_buffer
+ ( input usbclk,
+ input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
+ input reset, // standard DSP-side reset
+ input [15:0] usbdata,
+ input wire WR,
+ output wire have_space,
+ output reg tx_underrun,
+ input wire [3:0] channels,
+ output reg [15:0] tx_i_0,
+ output reg [15:0] tx_q_0,
+ output reg [15:0] tx_i_1,
+ output reg [15:0] tx_q_1,
+ output reg [15:0] tx_i_2,
+ output reg [15:0] tx_q_2,
+ output reg [15:0] tx_i_3,
+ output reg [15:0] tx_q_3,
+ input txclk,
+ input txstrobe,
+ input clear_status,
+ output wire tx_empty,
+ output [11:0] debugbus
+ );
+
+ wire [11:0] txfifolevel;
+ reg [8:0] write_count;
+ wire tx_full;
+ wire [15:0] fifodata;
+ wire rdreq;
+
+ reg [3:0] load_next;
+
+ // DAC Side of FIFO
+ assign rdreq = ((load_next != channels) & !tx_empty);
+
+ always @(posedge txclk)
+ if(reset)
+ begin
+ {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
+ <= #1 128'h0;
+ load_next <= #1 4'd0;
+ end
+ else
+ if((load_next != channels) & !tx_empty)
+ begin
+ load_next <= #1 load_next + 4'd1;
+ case(load_next)
+ 4'd0 : tx_i_0 <= #1 fifodata;
+ 4'd1 : tx_q_0 <= #1 fifodata;
+ 4'd2 : tx_i_1 <= #1 fifodata;
+ 4'd3 : tx_q_1 <= #1 fifodata;
+ 4'd4 : tx_i_2 <= #1 fifodata;
+ 4'd5 : tx_q_2 <= #1 fifodata;
+ 4'd6 : tx_i_3 <= #1 fifodata;
+ 4'd7 : tx_q_3 <= #1 fifodata;
+ endcase // case(load_next)
+ end // if ((load_next != channels) & !tx_empty)
+ else if(txstrobe & (load_next == channels))
+ begin
+ load_next <= #1 4'd0;
+ end
+
+ // USB Side of FIFO
+ assign have_space = (txfifolevel <= (4095-256));
+
+ always @(posedge usbclk)
+ if(bus_reset) // Use bus reset because this is on usbclk
+ write_count <= #1 0;
+ else if(WR & ~write_count[8])
+ write_count <= #1 write_count + 9'd1;
+ else
+ write_count <= #1 WR ? write_count : 9'b0;
+
+ // Detect Underruns
+ always @(posedge txclk)
+ if(reset)
+ tx_underrun <= 1'b0;
+ else if(txstrobe & (load_next != channels))
+ tx_underrun <= 1'b1;
+ else if(clear_status)
+ tx_underrun <= 1'b0;
+
+ // FIFO
+ fifo_4k txfifo
+ ( .data ( usbdata ),
+ .wrreq ( WR & ~write_count[8] ),
+ .wrclk ( usbclk ),
+
+ .q ( fifodata ),
+ .rdreq ( rdreq ),
+ .rdclk ( txclk ),
+
+ .aclr ( reset ), // asynch, so we can use either
+
+ .rdempty ( tx_empty ),
+ .rdusedw ( ),
+ .wrfull ( tx_full ),
+ .wrusedw ( txfifolevel )
+ );
+
+ // Debugging Aids
+ assign debugbus[0] = WR;
+ assign debugbus[1] = have_space;
+ assign debugbus[2] = tx_empty;
+ assign debugbus[3] = tx_full;
+ assign debugbus[4] = tx_underrun;
+ assign debugbus[5] = write_count[8];
+ assign debugbus[6] = txstrobe;
+ assign debugbus[7] = rdreq;
+ assign debugbus[11:8] = load_next;
+
+endmodule // tx_buffer
+
diff --git a/sdr_lib/tx_chain.v b/sdr_lib/tx_chain.v
new file mode 100644
index 000000000..8f0a17a52
--- /dev/null
+++ b/sdr_lib/tx_chain.v
@@ -0,0 +1,65 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module tx_chain
+ (input clock,
+ input reset,
+ input enable,
+ input wire [7:0] interp_rate,
+ input sample_strobe,
+ input interpolator_strobe,
+ input wire [31:0] freq,
+ input wire [15:0] i_in,
+ input wire [15:0] q_in,
+ output wire [15:0] i_out,
+ output wire [15:0] q_out
+ );
+
+ wire [15:0] bb_i, bb_q;
+
+ cic_interp cic_interp_i
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
+ .signal_in(i_in),.signal_out(bb_i) );
+
+ cic_interp cic_interp_q
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
+ .signal_in(q_in),.signal_out(bb_q) );
+
+`define NOCORDIC_TX
+`ifdef NOCORDIC_TX
+ assign i_out = bb_i;
+ assign q_out = bb_q;
+`else
+ wire [31:0] phase;
+
+ phase_acc phase_acc_tx
+ (.clk(clock),.reset(reset),.enable(enable),
+ .strobe(sample_strobe),.freq(freq),.phase(phase) );
+
+ cordic tx_cordic_0
+ ( .clock(clock),.reset(reset),.enable(sample_strobe),
+ .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
+ .xo(i_out),.yo(q_out),.zo() );
+`endif
+
+endmodule // tx_chain
diff --git a/sdr_lib/tx_chain_hb.v b/sdr_lib/tx_chain_hb.v
new file mode 100644
index 000000000..6cbe29c00
--- /dev/null
+++ b/sdr_lib/tx_chain_hb.v
@@ -0,0 +1,76 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module tx_chain_hb
+ (input clock,
+ input reset,
+ input enable,
+ input wire [7:0] interp_rate,
+ input sample_strobe,
+ input interpolator_strobe,
+ input hb_strobe,
+ input wire [31:0] freq,
+ input wire [15:0] i_in,
+ input wire [15:0] q_in,
+ output wire [15:0] i_out,
+ output wire [15:0] q_out,
+output wire [15:0] debug, output [15:0] hb_i_out
+ );
+assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
+
+ wire [15:0] bb_i, bb_q;
+ wire [15:0] hb_i_out, hb_q_out;
+
+ halfband_interp hb
+ (.clock(clock),.reset(reset),.enable(enable),
+ .strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
+ .signal_in_i(i_in),.signal_in_q(q_in),
+ .signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
+ .debug(debug[12:0]));
+
+ cic_interp cic_interp_i
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
+ .signal_in(hb_i_out),.signal_out(bb_i) );
+
+ cic_interp cic_interp_q
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
+ .signal_in(hb_q_out),.signal_out(bb_q) );
+
+`define NOCORDIC_TX
+`ifdef NOCORDIC_TX
+ assign i_out = bb_i;
+ assign q_out = bb_q;
+`else
+ wire [31:0] phase;
+
+ phase_acc phase_acc_tx
+ (.clk(clock),.reset(reset),.enable(enable),
+ .strobe(sample_strobe),.freq(freq),.phase(phase) );
+
+ cordic tx_cordic_0
+ ( .clock(clock),.reset(reset),.enable(sample_strobe),
+ .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
+ .xo(i_out),.yo(q_out),.zo() );
+`endif
+
+endmodule // tx_chain
diff --git a/tb/cbus_tb.v b/tb/cbus_tb.v
new file mode 100644
index 000000000..53cc1272b
--- /dev/null
+++ b/tb/cbus_tb.v
@@ -0,0 +1,71 @@
+module cbus_tb;
+
+`define ch1in_freq 0
+`define ch2in_freq 1
+`define ch3in_freq 2
+`define ch4in_freq 3
+`define ch1out_freq 4
+`define ch2out_freq 5
+`define ch3out_freq 6
+`define ch4out_freq 7
+`define rates 8
+`define misc 9
+
+ task send_config_word;
+ input [7:0] addr;
+ input [31:0] data;
+ integer i;
+
+ begin
+ #10 serenable = 1;
+ for(i=7;i>=0;i=i-1)
+ begin
+ #10 serdata = addr[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ for(i=31;i>=0;i=i-1)
+ begin
+ #10 serdata = data[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ #10 serenable = 0;
+ // #10 serclk = 1;
+ // #10 serclk = 0;
+ end
+ endtask // send_config_word
+
+ initial $dumpfile("cbus_tb.vcd");
+ initial $dumpvars(0,cbus_tb);
+
+ initial reset = 1;
+ initial #500 reset = 0;
+
+ reg serclk, serdata, serenable, reset;
+ wire SDO;
+
+ control_bus control_bus
+ ( .serial_clock(serclk),
+ .serial_data_in(serdata),
+ .enable(serenable),
+ .reset(reset),
+ .serial_data_out(SDO) );
+
+
+ initial
+ begin
+ #1000 send_config_word(8'd1,32'hDEAD_BEEF);
+ #1000 send_config_word(8'd3,32'hDDEE_FF01);
+ #1000 send_config_word(8'd19,32'hFFFF_FFFF);
+ #1000 send_config_word(8'd23,32'h1234_FEDC);
+ #1000 send_config_word(8'h80,32'h0);
+ #1000 send_config_word(8'h81,32'h0);
+ #1000 send_config_word(8'h82,32'h0);
+ #1000 reset = 1;
+ #1 $finish;
+ end
+
+endmodule // cbus_tb
diff --git a/tb/cordic_tb.v b/tb/cordic_tb.v
new file mode 100644
index 000000000..ed85b37b1
--- /dev/null
+++ b/tb/cordic_tb.v
@@ -0,0 +1,61 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+
+module cordic_tb();
+
+ cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );
+
+ reg reset;
+ reg clk;
+ reg enable;
+ reg [15:0] xi, yi, zi;
+
+ initial reset = 1'b1;
+ initial #1000 reset = 1'b0;
+
+ initial clk = 1'b0;
+ always #50 clk <= ~clk;
+
+ initial enable = 1'b1;
+
+ initial zi = 16'b0;
+
+ always @(posedge clk)
+ zi <= #1 zi + 16'd0;
+
+ wire [15:0] xo,yo,zo;
+
+ initial $dumpfile("cordic.vcd");
+ initial $dumpvars(0,cordic_tb);
+ initial
+ begin
+`include "sine.txt"
+ end
+
+ wire [15:0] xiu = {~xi[15],xi[14:0]};
+ wire [15:0] yiu = {~yi[15],yi[14:0]};
+ wire [15:0] xou = {~xo[15],xo[14:0]};
+ wire [15:0] you = {~yo[15],yo[14:0]};
+ initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);
+
+endmodule // cordic_tb
diff --git a/tb/decim_tb.v b/tb/decim_tb.v
new file mode 100644
index 000000000..ecf20cf4a
--- /dev/null
+++ b/tb/decim_tb.v
@@ -0,0 +1,108 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+module decim_tb();
+
+`include "usrp_tasks.v"
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ reg tb_oe;
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("decim_tb.vcd");
+ $dumpvars(0, fc_tb);
+end
+
+initial #100000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+reg [7:0] counter_decim;
+wire [7:0] decim_rate;
+assign decim_rate = 32;
+initial $monitor(dac1_data);
+
+ always @(posedge clk_120mhz)
+ begin
+ if(reset | ~enable_tx)
+ counter_decim <= #1 0;
+ else if(counter_decim == 0)
+ counter_decim <= #1 decim_rate - 8'b1;
+ else
+ counter_decim <= #1 counter_decim - 8'b1;
+ end
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #48 clk_120mhz = ~clk_120mhz;
+always #120 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+
+initial enable_tx = 1'b1;
+
+ wire [31:0] decim_out, q_decim_out;
+ wire [31:0] decim_out;
+ wire [31:0] phase;
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+endmodule
diff --git a/tb/fullchip_tb.v b/tb/fullchip_tb.v
new file mode 100755
index 000000000..c446ff0e1
--- /dev/null
+++ b/tb/fullchip_tb.v
@@ -0,0 +1,174 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+`timescale 1ns/1ns
+
+module fullchip_tb();
+
+`include "usrp_tasks.v"
+
+fullchip fullchip
+ (
+ .clk_120mhz(clk_120mhz),
+ .reset(reset),
+ .enable_rx(enable_rx),
+ .enable_tx(enable_tx),
+ .SLD(serload),
+ .SEN(serenable),
+ .clear_status(),
+ .SDI(serdata),
+ .SCLK(serclk),
+
+ .adc1_data(adc1_data),
+ .adc2_data(adc2_data),
+ .adc3_data(adc1_data),
+ .adc4_data(adc2_data),
+
+ .dac1_data(dac1_data),
+ .dac2_data(dac2_data),
+ .dac3_data(),.dac4_data(),
+
+ .adclk0(adclk),.adclk1(),
+
+ .adc_oeb(),.adc_otr(4'b0),
+
+ .clk_out(clk_out),
+
+ .misc_pins(),
+
+ // USB interface
+ .usbclk(usbclk),.usbctl(usbctl),
+ .usbrdy(usbrdy),.usbdata(usbdata)
+ );
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ wire have_packet_rdy = usbrdy[1];
+
+ reg tb_oe;
+ initial tb_oe=1'b1;
+
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("fullchip_tb.vcd");
+ $dumpvars(0, fullchip_tb);
+end
+
+//initial #1000000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+//initial $monitor(dac1_data);
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #24 clk_120mhz = ~clk_120mhz;
+always #60 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+/////////////////////////////////////////////////
+// Run AD input
+
+always @(posedge adclk) adc1_data <= #1 12'd1234;
+always @(posedge adclk) adc2_data <= #1 12'd1234;
+
+/////////////////////////////////////////////////
+// USB interface
+
+ initial
+ begin
+ initialize_usb;
+ #30000 @(posedge usbclk);
+ burst_usb_write(257);
+
+ #30000 burst_usb_read(256);
+ #10000 $finish;
+
+// repeat(30)
+// begin
+// write_from_usb;
+// read_from_usb;
+// end
+end
+
+/////////////////////////////////////////////////
+// TX and RX enable
+
+initial enable_tx = 1'b0;
+initial #40000 enable_tx = 1'b1;
+initial enable_rx = 1'b0;
+initial #40000 enable_rx = 1'b1;
+
+//////////////////////////////////////////////////
+// Set up control bus
+
+initial
+begin
+ #1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock
+ send_config_word(`ch2in_freq,32'h0);
+ send_config_word(`ch3in_freq,32'h0);
+ send_config_word(`ch4in_freq,32'h0);
+ send_config_word(`ch1out_freq,32'h01234567);
+ send_config_word(`ch2out_freq,32'h0);
+ send_config_word(`ch3out_freq,32'h0);
+ send_config_word(`ch4out_freq,32'h0);
+ send_config_word(`misc,32'h0);
+ send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07});
+ // adc, ext, interp, decim
+end
+
+/////////////////////////////////////////////////////////
+
+endmodule
+
diff --git a/tb/interp_tb.v b/tb/interp_tb.v
new file mode 100755
index 000000000..8a8e89ff9
--- /dev/null
+++ b/tb/interp_tb.v
@@ -0,0 +1,108 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// testbench for fullchip
+
+module interp_tb();
+
+`include "usrp_tasks.v"
+
+ reg clk_120mhz;
+ reg usbclk;
+ reg reset;
+
+ reg [11:0] adc1_data, adc2_data;
+ wire [13:0] dac1_data, dac2_data;
+
+ wire [5:0] usbctl;
+ wire [5:0] usbrdy;
+
+ wire [15:0] usbdata;
+
+ reg WE, RD, OE;
+
+ assign usbctl[0] = WE;
+ assign usbctl[1] = RD;
+ assign usbctl[2] = OE;
+ assign usbctl[5:3] = 0;
+
+ reg tb_oe;
+ assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
+ reg serload, serenable, serclk, serdata;
+ reg enable_tx, enable_rx;
+ reg [15:0] usbdatareg;
+
+///////////////////////////////////////////////
+// Simulation Control
+initial
+begin
+ $dumpfile("interp_tb.vcd");
+ $dumpvars(0, fc_tb);
+end
+
+initial #100000 $finish;
+
+///////////////////////////////////////////////
+// Monitors
+
+reg [7:0] counter_interp;
+wire [7:0] interp_rate;
+assign interp_rate = 32;
+initial $monitor(dac1_data);
+
+ always @(posedge clk_120mhz)
+ begin
+ if(reset | ~enable_tx)
+ counter_interp <= #1 0;
+ else if(counter_interp == 0)
+ counter_interp <= #1 interp_rate - 8'b1;
+ else
+ counter_interp <= #1 counter_interp - 8'b1;
+ end
+
+///////////////////////////////////////////////
+// Clock and reset
+
+initial clk_120mhz = 0;
+initial usbclk = 0;
+always #48 clk_120mhz = ~clk_120mhz;
+always #120 usbclk = ~usbclk;
+
+initial reset = 1'b1;
+initial #500 reset = 1'b0;
+
+
+initial enable_tx = 1'b1;
+
+ wire [31:0] interp_out, q_interp_out;
+ wire [31:0] decim_out;
+ wire [31:0] phase;
+
+ cic_interp #(.bitwidth(32),.stages(4))
+ interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out));
+
+ cic_decim #(.bitwidth(32),.stages(4))
+ decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
+ .strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
+
+endmodule
diff --git a/tb/justinterp_tb.v b/tb/justinterp_tb.v
new file mode 100644
index 000000000..ffbd0f178
--- /dev/null
+++ b/tb/justinterp_tb.v
@@ -0,0 +1,73 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module cic_decim_tb;
+
+cic_decim #(.bitwidth(16),.stages(4))
+ decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
+
+ reg clock;
+ reg reset;
+ reg enable;
+ wire strobe;
+ reg [15:0] signal_in;
+ wire [15:0] signal_out;
+
+ assign strobe_in = 1'b1;
+ reg strobe_out;
+
+ always @(posedge clock)
+ while(1)
+ begin
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ strobe_out <= 1'b1;
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ strobe_out <= 1'b0;
+ end
+
+ initial clock = 0;
+ always #50 clock = ~clock;
+
+ initial reset = 1;
+ initial #1000 reset = 0;
+
+ initial enable = 0;
+ initial #2000 enable = 1;
+
+ initial signal_in = 16'h1;
+ initial #500000 signal_in = 16'h7fff;
+ initial #1000000 signal_in = 16'h8000;
+ initial #1500000 signal_in = 16'hffff;
+
+
+ initial $dumpfile("decim.vcd");
+ initial $dumpvars(0,cic_decim_tb);
+
+ initial #10000000 $finish;
+
+endmodule // cic_decim_tb
diff --git a/tb/makesine.pl b/tb/makesine.pl
new file mode 100755
index 000000000..9aebd6947
--- /dev/null
+++ b/tb/makesine.pl
@@ -0,0 +1,14 @@
+#!/usr/bin/perl
+
+$angle = 0;
+$angle_inc = 2*3.14159/87.2;
+$amp = 1;
+$amp_rate = 1.0035;
+for($i=0;$i<3500;$i++)
+ {
+ printf("@(posedge clk);xi<= #1 16'h%x;yi<= #1 16'h%x;\n",65535&int($amp*cos($angle)),65535&int($amp*sin($angle)));
+ $angle += $angle_inc;
+ $amp *= $amp_rate;
+ }
+
+printf("\$finish;\n");
diff --git a/tb/run_cordic b/tb/run_cordic
new file mode 100755
index 000000000..68144fc83
--- /dev/null
+++ b/tb/run_cordic
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y ../sdr_lib -o cordic_tb cordic_tb.v
+
diff --git a/tb/run_fullchip b/tb/run_fullchip
new file mode 100755
index 000000000..eb81d7ff7
--- /dev/null
+++ b/tb/run_fullchip
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y ../toplevel/fullchip -y ../sdr_lib -y ../models -y . -o fullchip_tb fullchip_tb.v
+
diff --git a/tb/usrp_tasks.v b/tb/usrp_tasks.v
new file mode 100755
index 000000000..00f82b9e1
--- /dev/null
+++ b/tb/usrp_tasks.v
@@ -0,0 +1,145 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Tasks
+
+/////////////////////////////////////////////////
+// USB interface
+
+task initialize_usb;
+begin
+ OE = 0;WE = 0;RD = 0;
+ usbdatareg <= 16'h0;
+end
+endtask
+
+task write_from_usb;
+begin
+ tb_oe <= 1'b1;
+ @(posedge usbclk);
+ usbdatareg <= #1 $random % 65536;
+ WE <= #1 1'b1;
+ @(posedge usbclk)
+ WE <= #1 1'b0;
+ tb_oe <= #1 1'b0;
+end
+endtask
+
+task burst_usb_write;
+ input [31:0] repeat_count;
+
+ begin
+ tb_oe <= 1'b1;
+ repeat(repeat_count)
+ begin
+ @(posedge usbclk)
+ usbdatareg <= #1 usbdatareg + 1; //$random % 65536;
+ WE <= #1 1'b1;
+ end
+ @(posedge usbclk)
+ WE <= #1 1'b0;
+ tb_oe <= 1'b0;
+ end
+endtask // burst_usb_write
+
+
+task read_from_usb;
+begin
+ @(posedge usbclk);
+ RD <= #1 1'b1;
+ @(posedge usbclk);
+ RD <= #1 1'b0;
+ OE <= #1 1'b1;
+ @(posedge usbclk);
+ OE <= #1 1'b0;
+end
+endtask
+
+task burst_usb_read;
+ input [31:0] repeat_count;
+ begin
+ while (~have_packet_rdy) begin
+ @(posedge usbclk);
+ end
+
+ @(posedge usbclk)
+ RD <= #1 1'b1;
+ repeat(repeat_count)
+ begin
+ @(posedge usbclk)
+ OE <= #1 1'b1;
+ end
+ RD <= #1 1'b0;
+ @(posedge usbclk);
+ OE <= #1 1'b0;
+ end
+endtask // burst_usb_read
+
+/////////////////////////////////////////////////
+// TX and RX enable
+
+//////////////////////////////////////////////////
+// Set up control bus
+
+`define ch1in_freq 0
+`define ch2in_freq 1
+`define ch3in_freq 2
+`define ch4in_freq 3
+`define ch1out_freq 4
+`define ch2out_freq 5
+`define ch3out_freq 6
+`define ch4out_freq 7
+`define rates 8
+`define misc 9
+
+ task send_config_word;
+ input [7:0] addr;
+ input [31:0] data;
+ integer i;
+
+ begin
+ #10 serenable = 1;
+ for(i=7;i>=0;i=i-1)
+ begin
+ #10 serdata = addr[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ for(i=31;i>=0;i=i-1)
+ begin
+ #10 serdata = data[i];
+ #10 serclk = 0;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ end
+ #10 serenable = 0;
+ // #10 serload = 0;
+ // #10 serload = 1;
+ #10 serclk = 1;
+ #10 serclk = 0;
+ //#10 serload = 0;
+ end
+ endtask // send_config_word
+
+
+/////////////////////////////////////////////////////////
+
diff --git a/toplevel/mrfm/biquad_2stage.v b/toplevel/mrfm/biquad_2stage.v
new file mode 100644
index 000000000..9b769014d
--- /dev/null
+++ b/toplevel/mrfm/biquad_2stage.v
@@ -0,0 +1,131 @@
+`include "mrfm.vh"
+
+module biquad_2stage (input clock, input reset, input strobe_in,
+ input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
+ input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus);
+
+ wire [3:0] coeff_addr, coeff_wr_addr;
+ wire [3:0] data_addr, data_wr_addr;
+ reg [3:0] cur_offset, data_addr_int, data_wr_addr_int;
+
+ wire [15:0] coeff, coeff_wr_data, data, data_wr_data;
+ wire coeff_wr;
+ reg data_wr;
+
+ wire [30:0] product;
+ wire [33:0] accum;
+ wire [15:0] scaled_accum;
+
+ wire [7:0] shift;
+ reg [3:0] phase;
+ wire enable_mult, enable_acc, latch_out, select_input;
+ reg done, clear_acc;
+
+ setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr));
+
+ setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(shift),.changed());
+
+ ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data),
+ .rd_addr(coeff_addr),.rd_data(coeff));
+
+ ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data),
+ .rd_addr(data_addr),.rd_data(data));
+
+ mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() );
+
+ acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
+ .addend(product),.sum(accum) );
+
+ shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
+
+ assign data_wr_data = select_input ? sample_in : scaled_accum;
+ assign enable_mult = 1'b1;
+
+ always @(posedge clock)
+ if(reset)
+ cur_offset <= #1 4'd0;
+ else if(latch_out)
+ cur_offset <= #1 cur_offset + 4'd1;
+
+ assign data_addr = data_addr_int + cur_offset;
+ assign data_wr_addr = data_wr_addr_int + cur_offset;
+
+ always @(posedge clock)
+ if(reset)
+ done <= #1 1'b0;
+ else if(latch_out)
+ done <= #1 1'b1;
+ else if(strobe_in)
+ done <= #1 1'b0;
+
+ always @(posedge clock)
+ if(reset)
+ phase <= #1 4'd0;
+ else if(strobe_in)
+ phase <= #1 4'd0;
+ else if(!done)
+ phase <= #1 phase + 4'd1;
+
+ assign coeff_addr = phase;
+
+ always @(phase)
+ case(phase)
+ 4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02;
+ 4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04;
+
+ 4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05;
+ 4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07;
+ default : data_addr_int = 4'd00;
+ endcase // case(phase)
+
+ always @(phase)
+ case(phase)
+ 4'd0 : data_wr_addr_int = 4'd2;
+ 4'd8 : data_wr_addr_int = 4'd5;
+ 4'd14 : data_wr_addr_int = 4'd8;
+ default : data_wr_addr_int = 4'd0;
+ endcase // case(phase)
+
+ always @(phase)
+ case(phase)
+ 4'd0, 4'd8, 4'd14 : data_wr = 1'b1;
+ default : data_wr = 1'b0;
+ endcase // case(phase)
+
+ assign select_input = (phase == 4'd0);
+
+ always @(phase)
+ case(phase)
+ 4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1;
+ default : clear_acc = 1'b0;
+ endcase // case(phase)
+
+ assign enable_acc = ~clear_acc;
+ assign latch_out = (phase == 4'd14);
+
+ always @(posedge clock)
+ if(reset)
+ sample_out <= #1 16'd0;
+ else if(latch_out)
+ sample_out <= #1 scaled_accum;
+
+ ////////////////////////////////////////////////////////
+ // Debug
+
+ wire [3:0] debugmux;
+
+ setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(debugmux),.changed());
+
+ assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset};
+ assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int};
+ assign debugbus[47:32] = debugmux[2] ? sample_out : coeff;
+ assign debugbus[63:48] = debugmux[3] ? sample_in : data;
+
+endmodule // biquad_2stage
+
diff --git a/toplevel/mrfm/biquad_6stage.v b/toplevel/mrfm/biquad_6stage.v
new file mode 100644
index 000000000..2b0c511ce
--- /dev/null
+++ b/toplevel/mrfm/biquad_6stage.v
@@ -0,0 +1,137 @@
+`include "mrfm.vh"
+
+module mrfm_iir (input clock, input reset, input strobe_in,
+ input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
+ input wire [15:0] sample_in, output reg [15:0] sample_out);
+
+ wire [5:0] coeff_addr, coeff_wr_addr;
+ wire [4:0] data_addr, data_wr_addr;
+ reg [4:0] cur_offset, data_addr_int, data_wr_addr_int;
+
+ wire [15:0] coeff, coeff_wr_data, data, data_wr_data;
+ wire coeff_wr;
+ reg data_wr;
+
+ wire [30:0] product;
+ wire [33:0] accum;
+ wire [15:0] scaled_accum;
+
+ wire [7:0] shift;
+ reg [5:0] phase;
+ wire enable_mult, enable_acc, latch_out, select_input;
+ reg done, clear_acc;
+
+ setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr));
+
+ setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(shift),.changed());
+
+ ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data),
+ .rd_addr(coeff_addr),.rd_data(coeff));
+
+ ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data),
+ .rd_addr(data_addr),.rd_data(data));
+
+ mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() );
+
+ acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
+ .addend(product),.sum(accum) );
+
+ shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
+
+ assign data_wr_data = select_input ? sample_in : scaled_accum;
+ assign enable_mult = 1'b1;
+
+ always @(posedge clock)
+ if(reset)
+ cur_offset <= #1 5'd0;
+ else if(latch_out)
+ cur_offset <= #1 cur_offset + 5'd1;
+
+ assign data_addr = data_addr_int + cur_offset;
+ assign data_wr_addr = data_wr_addr_int + cur_offset;
+
+ always @(posedge clock)
+ if(reset)
+ done <= #1 1'b0;
+ else if(latch_out)
+ done <= #1 1'b1;
+ else if(strobe_in)
+ done <= #1 1'b0;
+
+ always @(posedge clock)
+ if(reset)
+ phase <= #1 6'd0;
+ else if(strobe_in)
+ phase <= #1 6'd0;
+ else if(!done)
+ phase <= #1 phase + 6'd1;
+
+ always @(phase)
+ case(phase)
+ 6'd0 : data_addr_int = 5'd0;
+ default : data_addr_int = 5'd0;
+ endcase // case(phase)
+
+ assign coeff_addr = phase;
+
+ always @(phase)
+ case(phase)
+ 6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02;
+ 6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04;
+
+ 6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05;
+ 6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07;
+
+ 6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08;
+ 6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10;
+
+ 6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11;
+ 6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13;
+
+ 6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14;
+ 6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16;
+
+ 6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17;
+ 6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19;
+
+ default : data_addr_int = 5'd00;
+ endcase // case(phase)
+
+ always @(phase)
+ case(phase)
+ 6'd0 : data_wr_addr_int = 5'd2;
+ 6'd8 : data_wr_addr_int = 5'd5;
+ 6'd14 : data_wr_addr_int = 5'd8;
+ 6'd20 : data_wr_addr_int = 5'd11;
+ 6'd26 : data_wr_addr_int = 5'd14;
+ 6'd32 : data_wr_addr_int = 5'd17;
+ 6'd38 : data_wr_addr_int = 5'd20;
+ default : data_wr_addr_int = 5'd0;
+ endcase // case(phase)
+
+ always @(phase)
+ case(phase)
+ 6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1;
+ default : data_wr = 1'b0;
+ endcase // case(phase)
+
+ always @(phase)
+ case(phase)
+ 6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1;
+ default : clear_acc = 1'b0;
+ endcase // case(phase)
+
+ assign enable_acc = ~clear_acc;
+ assign latch_out = (phase == 6'd38);
+
+ always @(posedge clock)
+ if(reset)
+ sample_out <= #1 16'd0;
+ else if(latch_out)
+ sample_out <= #1 scaled_accum;
+
+endmodule // mrfm_iir
diff --git a/toplevel/mrfm/mrfm.csf b/toplevel/mrfm/mrfm.csf
new file mode 100644
index 000000000..2c30b996b
--- /dev/null
+++ b/toplevel/mrfm/mrfm.csf
@@ -0,0 +1,444 @@
+COMPILER_SETTINGS
+{
+ IO_PLACEMENT_OPTIMIZATION = OFF;
+ ENABLE_DRC_SETTINGS = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+ PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ TRUE_WYSIWYG_FLOW = OFF;
+ SEED = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = "NORMAL COMPILATION";
+ OPTIMIZE_HOLD_TIMING = OFF;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = OFF;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |mrfm;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
+ FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = SLD_HUB_INST;
+ HUB_ENTITY_NAME = SLD_HUB;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+ ENABLE_SIGNALTAP = Off;
+ AUTO_ENABLE_SMART_COMPILE = On;
+}
+CHIP(mrfm)
+{
+ DEVICE = EP1C12Q240C8;
+ DEVICE_FILTER_PACKAGE = "ANY QFP";
+ DEVICE_FILTER_PIN_COUNT = 240;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = OFF;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = ON;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
+ STRATIX_DEVICE_IO_STANDARD = LVTTL;
+ CLOCK_SOURCE = INTERNAL;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ SCLK : LOCATION = Pin_101;
+ SDI : LOCATION = Pin_100;
+ SEN : LOCATION = Pin_98;
+ SLD : LOCATION = Pin_95;
+ adc1_data[0] : LOCATION = Pin_5;
+ adc1_data[10] : LOCATION = Pin_235;
+ adc1_data[11] : LOCATION = Pin_234;
+ adc1_data[1] : LOCATION = Pin_4;
+ adc1_data[2] : LOCATION = Pin_3;
+ adc1_data[3] : LOCATION = Pin_2;
+ adc1_data[4] : LOCATION = Pin_1;
+ adc1_data[4] : IO_STANDARD = LVTTL;
+ adc1_data[5] : LOCATION = Pin_240;
+ adc1_data[6] : LOCATION = Pin_239;
+ adc1_data[7] : LOCATION = Pin_238;
+ adc1_data[8] : LOCATION = Pin_237;
+ adc1_data[9] : LOCATION = Pin_236;
+ adc2_data[0] : LOCATION = Pin_20;
+ adc2_data[10] : LOCATION = Pin_8;
+ adc2_data[11] : LOCATION = Pin_7;
+ adc2_data[1] : LOCATION = Pin_19;
+ adc2_data[2] : LOCATION = Pin_18;
+ adc2_data[3] : LOCATION = Pin_17;
+ adc2_data[4] : LOCATION = Pin_16;
+ adc2_data[5] : LOCATION = Pin_15;
+ adc2_data[6] : LOCATION = Pin_14;
+ adc2_data[7] : LOCATION = Pin_13;
+ adc2_data[8] : LOCATION = Pin_12;
+ adc2_data[9] : LOCATION = Pin_11;
+ adc3_data[0] : LOCATION = Pin_200;
+ adc3_data[10] : LOCATION = Pin_184;
+ adc3_data[11] : LOCATION = Pin_183;
+ adc3_data[1] : LOCATION = Pin_197;
+ adc3_data[2] : LOCATION = Pin_196;
+ adc3_data[3] : LOCATION = Pin_195;
+ adc3_data[4] : LOCATION = Pin_194;
+ adc3_data[5] : LOCATION = Pin_193;
+ adc3_data[6] : LOCATION = Pin_188;
+ adc3_data[7] : LOCATION = Pin_187;
+ adc3_data[8] : LOCATION = Pin_186;
+ adc3_data[9] : LOCATION = Pin_185;
+ adc4_data[0] : LOCATION = Pin_222;
+ adc4_data[10] : LOCATION = Pin_203;
+ adc4_data[11] : LOCATION = Pin_202;
+ adc4_data[1] : LOCATION = Pin_219;
+ adc4_data[2] : LOCATION = Pin_217;
+ adc4_data[3] : LOCATION = Pin_216;
+ adc4_data[4] : LOCATION = Pin_215;
+ adc4_data[5] : LOCATION = Pin_214;
+ adc4_data[6] : LOCATION = Pin_213;
+ adc4_data[7] : LOCATION = Pin_208;
+ adc4_data[8] : LOCATION = Pin_207;
+ adc4_data[9] : LOCATION = Pin_206;
+ adc_oeb[0] : LOCATION = Pin_228;
+ adc_oeb[1] : LOCATION = Pin_21;
+ adc_oeb[2] : LOCATION = Pin_181;
+ adc_oeb[3] : LOCATION = Pin_218;
+ adc_otr[0] : LOCATION = Pin_233;
+ adc_otr[1] : LOCATION = Pin_6;
+ adc_otr[2] : LOCATION = Pin_182;
+ adc_otr[3] : LOCATION = Pin_201;
+ adclk0 : LOCATION = Pin_224;
+ adclk1 : LOCATION = Pin_226;
+ clk0 : LOCATION = Pin_28;
+ clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk0 : IO_STANDARD = LVTTL;
+ clk1 : LOCATION = Pin_29;
+ clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk1 : IO_STANDARD = LVTTL;
+ clk3 : LOCATION = Pin_152;
+ clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk3 : IO_STANDARD = LVTTL;
+ clk_120mhz : LOCATION = Pin_153;
+ clk_120mhz : IO_STANDARD = LVTTL;
+ clk_out : LOCATION = Pin_63;
+ clk_out : IO_STANDARD = LVTTL;
+ dac1_data[0] : LOCATION = Pin_165;
+ dac1_data[10] : LOCATION = Pin_177;
+ dac1_data[11] : LOCATION = Pin_178;
+ dac1_data[12] : LOCATION = Pin_179;
+ dac1_data[13] : LOCATION = Pin_180;
+ dac1_data[1] : LOCATION = Pin_166;
+ dac1_data[2] : LOCATION = Pin_167;
+ dac1_data[3] : LOCATION = Pin_168;
+ dac1_data[4] : LOCATION = Pin_169;
+ dac1_data[5] : LOCATION = Pin_170;
+ dac1_data[6] : LOCATION = Pin_173;
+ dac1_data[7] : LOCATION = Pin_174;
+ dac1_data[8] : LOCATION = Pin_175;
+ dac1_data[9] : LOCATION = Pin_176;
+ dac2_data[0] : LOCATION = Pin_159;
+ dac2_data[10] : LOCATION = Pin_163;
+ dac2_data[11] : LOCATION = Pin_139;
+ dac2_data[12] : LOCATION = Pin_164;
+ dac2_data[13] : LOCATION = Pin_138;
+ dac2_data[1] : LOCATION = Pin_158;
+ dac2_data[2] : LOCATION = Pin_160;
+ dac2_data[3] : LOCATION = Pin_156;
+ dac2_data[4] : LOCATION = Pin_161;
+ dac2_data[5] : LOCATION = Pin_144;
+ dac2_data[6] : LOCATION = Pin_162;
+ dac2_data[7] : LOCATION = Pin_141;
+ dac2_data[8] : LOCATION = Pin_143;
+ dac2_data[9] : LOCATION = Pin_140;
+ dac3_data[0] : LOCATION = Pin_122;
+ dac3_data[10] : LOCATION = Pin_134;
+ dac3_data[11] : LOCATION = Pin_135;
+ dac3_data[12] : LOCATION = Pin_136;
+ dac3_data[13] : LOCATION = Pin_137;
+ dac3_data[1] : LOCATION = Pin_123;
+ dac3_data[2] : LOCATION = Pin_124;
+ dac3_data[3] : LOCATION = Pin_125;
+ dac3_data[4] : LOCATION = Pin_126;
+ dac3_data[5] : LOCATION = Pin_127;
+ dac3_data[6] : LOCATION = Pin_128;
+ dac3_data[7] : LOCATION = Pin_131;
+ dac3_data[8] : LOCATION = Pin_132;
+ dac3_data[9] : LOCATION = Pin_133;
+ dac4_data[0] : LOCATION = Pin_104;
+ dac4_data[10] : LOCATION = Pin_118;
+ dac4_data[11] : LOCATION = Pin_119;
+ dac4_data[12] : LOCATION = Pin_120;
+ dac4_data[13] : LOCATION = Pin_121;
+ dac4_data[1] : LOCATION = Pin_105;
+ dac4_data[2] : LOCATION = Pin_106;
+ dac4_data[3] : LOCATION = Pin_107;
+ dac4_data[4] : LOCATION = Pin_108;
+ dac4_data[5] : LOCATION = Pin_113;
+ dac4_data[6] : LOCATION = Pin_114;
+ dac4_data[7] : LOCATION = Pin_115;
+ dac4_data[8] : LOCATION = Pin_116;
+ dac4_data[9] : LOCATION = Pin_117;
+ enable_rx : LOCATION = Pin_88;
+ enable_tx : LOCATION = Pin_93;
+ gndbus[0] : LOCATION = Pin_223;
+ gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[0] : IO_STANDARD = LVTTL;
+ gndbus[1] : LOCATION = Pin_225;
+ gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[1] : IO_STANDARD = LVTTL;
+ gndbus[2] : LOCATION = Pin_227;
+ gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[2] : IO_STANDARD = LVTTL;
+ gndbus[3] : LOCATION = Pin_62;
+ gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[3] : IO_STANDARD = LVTTL;
+ gndbus[4] : LOCATION = Pin_64;
+ gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[4] : IO_STANDARD = LVTTL;
+ misc_pins[0] : LOCATION = Pin_87;
+ misc_pins[0] : IO_STANDARD = LVTTL;
+ misc_pins[10] : LOCATION = Pin_76;
+ misc_pins[10] : IO_STANDARD = LVTTL;
+ misc_pins[11] : LOCATION = Pin_74;
+ misc_pins[11] : IO_STANDARD = LVTTL;
+ misc_pins[1] : LOCATION = Pin_86;
+ misc_pins[1] : IO_STANDARD = LVTTL;
+ misc_pins[2] : LOCATION = Pin_85;
+ misc_pins[2] : IO_STANDARD = LVTTL;
+ misc_pins[3] : LOCATION = Pin_84;
+ misc_pins[3] : IO_STANDARD = LVTTL;
+ misc_pins[4] : LOCATION = Pin_83;
+ misc_pins[4] : IO_STANDARD = LVTTL;
+ misc_pins[5] : LOCATION = Pin_82;
+ misc_pins[5] : IO_STANDARD = LVTTL;
+ misc_pins[6] : LOCATION = Pin_79;
+ misc_pins[6] : IO_STANDARD = LVTTL;
+ misc_pins[7] : LOCATION = Pin_78;
+ misc_pins[7] : IO_STANDARD = LVTTL;
+ misc_pins[8] : LOCATION = Pin_77;
+ misc_pins[8] : IO_STANDARD = LVTTL;
+ misc_pins[9] : LOCATION = Pin_75;
+ misc_pins[9] : IO_STANDARD = LVTTL;
+ reset : LOCATION = Pin_94;
+ usbclk : LOCATION = Pin_55;
+ usbctl[0] : LOCATION = Pin_56;
+ usbctl[1] : LOCATION = Pin_54;
+ usbctl[2] : LOCATION = Pin_53;
+ usbctl[3] : LOCATION = Pin_58;
+ usbctl[4] : LOCATION = Pin_57;
+ usbctl[5] : LOCATION = Pin_44;
+ usbdata[0] : LOCATION = Pin_73;
+ usbdata[10] : LOCATION = Pin_41;
+ usbdata[11] : LOCATION = Pin_39;
+ usbdata[12] : LOCATION = Pin_38;
+ usbdata[12] : IO_STANDARD = LVTTL;
+ usbdata[13] : LOCATION = Pin_37;
+ usbdata[14] : LOCATION = Pin_24;
+ usbdata[15] : LOCATION = Pin_23;
+ usbdata[1] : LOCATION = Pin_68;
+ usbdata[2] : LOCATION = Pin_67;
+ usbdata[3] : LOCATION = Pin_66;
+ usbdata[4] : LOCATION = Pin_65;
+ usbdata[5] : LOCATION = Pin_61;
+ usbdata[6] : LOCATION = Pin_60;
+ usbdata[7] : LOCATION = Pin_59;
+ usbdata[8] : LOCATION = Pin_43;
+ usbdata[9] : LOCATION = Pin_42;
+ usbrdy[0] : LOCATION = Pin_45;
+ usbrdy[1] : LOCATION = Pin_46;
+ usbrdy[2] : LOCATION = Pin_47;
+ usbrdy[3] : LOCATION = Pin_48;
+ usbrdy[4] : LOCATION = Pin_49;
+ usbrdy[5] : LOCATION = Pin_50;
+ clear_status : LOCATION = Pin_99;
+}
diff --git a/toplevel/mrfm/mrfm.esf b/toplevel/mrfm/mrfm.esf
new file mode 100644
index 000000000..72b84e39e
--- /dev/null
+++ b/toplevel/mrfm/mrfm.esf
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+ ESTIMATE_POWER_CONSUMPTION = OFF;
+ GLITCH_INTERVAL = 1NS;
+ GLITCH_DETECTION = OFF;
+ SIMULATION_COVERAGE = ON;
+ CHECK_OUTPUTS = OFF;
+ SETUP_HOLD_DETECTION = OFF;
+ POWER_ESTIMATION_START_TIME = "0 NS";
+ ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+ SIMULATION_MODE = TIMING;
+ START_TIME = 0NS;
+ USE_COMPILER_SETTINGS = mrfm;
+}
diff --git a/toplevel/mrfm/mrfm.psf b/toplevel/mrfm/mrfm.psf
new file mode 100644
index 000000000..678a7faa2
--- /dev/null
+++ b/toplevel/mrfm/mrfm.psf
@@ -0,0 +1,312 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+ HCPY_ALOAD_SIGNALS = OFF;
+ HCPY_VREF_PINS = OFF;
+ HCPY_CAT = OFF;
+ HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+ ACLK_RULE_IMSZER_ADOMAIN = OFF;
+ ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+ ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+ ACLK_CAT = OFF;
+ SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+ SIGNALRACE_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+ NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+ NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+ NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+ NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+ NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+ NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+ NONSYNCHSTRUCT_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+ TIMING_RULE_COIN_CLKEDGE = OFF;
+ TIMING_RULE_SHIFT_REG = OFF;
+ TIMING_RULE_HIGH_FANOUTS = OFF;
+ TIMING_CAT = OFF;
+ RESET_RULE_ALL = OFF;
+ RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_REG_ASNYCH = OFF;
+ RESET_RULE_COMB_ASYNCH_RESET = OFF;
+ RESET_RULE_IMSYNCH_EXRESET = OFF;
+ RESET_RULE_UNSYNCH_EXRESET = OFF;
+ RESET_RULE_INPINS_RESETNET = OFF;
+ RESET_CAT = OFF;
+ CLK_RULE_ALL = OFF;
+ CLK_RULE_MIX_EDGES = OFF;
+ CLK_RULE_CLKNET_CLKSPINES = OFF;
+ CLK_RULE_INPINS_CLKNET = OFF;
+ CLK_RULE_GATING_SCHEME = OFF;
+ CLK_RULE_INV_CLOCK = OFF;
+ CLK_RULE_COMB_CLOCK = OFF;
+ CLK_CAT = OFF;
+ HCPY_EXCEED_USER_IO_USAGE = OFF;
+ HCPY_EXCEED_RAM_USAGE = OFF;
+ NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+ SIGNALRACE_RULE_TRISTATE = OFF;
+ ASSG_RULE_MISSING_TIMING = OFF;
+ ASSG_RULE_MISSING_FMAX = OFF;
+ ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+ AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+ AUTO_DSP_RECOGNITION = ON;
+ AUTO_RAM_RECOGNITION = ON;
+ REMOVE_DUPLICATE_LOGIC = ON;
+ AUTO_TURBO_BIT = ON;
+ AUTO_MERGE_PLLS = ON;
+ AUTO_OPEN_DRAIN_PINS = ON;
+ AUTO_PARALLEL_EXPANDERS = ON;
+ AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
+ AUTO_FAST_OUTPUT_REGISTERS = OFF;
+ AUTO_FAST_INPUT_REGISTERS = OFF;
+ AUTO_CASCADE_CHAINS = ON;
+ AUTO_CARRY_CHAINS = ON;
+ AUTO_DELAY_CHAINS = ON;
+ MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
+ PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
+ CASCADE_CHAIN_LENGTH = 2;
+ STRATIX_CARRY_CHAIN_LENGTH = 70;
+ MERCURY_CARRY_CHAIN_LENGTH = 48;
+ FLEX10K_CARRY_CHAIN_LENGTH = 32;
+ FLEX6K_CARRY_CHAIN_LENGTH = 32;
+ CARRY_CHAIN_LENGTH = 48;
+ CARRY_OUT_PINS_LCELL_INSERT = ON;
+ NORMAL_LCELL_INSERT = ON;
+ AUTO_LCELL_INSERTION = ON;
+ ALLOW_XOR_GATE_USAGE = ON;
+ AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
+ AUTO_PACKED_REGISTERS = OFF;
+ AUTO_PACKED_REG_CYCLONE = NORMAL;
+ FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
+ MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
+ APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
+ MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
+ STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
+ CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX10K_TECHNOLOGY_MAPPER = LUT;
+ FLEX6K_TECHNOLOGY_MAPPER = LUT;
+ MERCURY_TECHNOLOGY_MAPPER = LUT;
+ APEX20K_TECHNOLOGY_MAPPER = LUT;
+ MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
+ STRATIX_TECHNOLOGY_MAPPER = LUT;
+ AUTO_IMPLEMENT_IN_ROM = OFF;
+ AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+ AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+ AUTO_GLOBAL_OE = ON;
+ AUTO_GLOBAL_CLOCK = ON;
+ USE_LPM_FOR_AHDL_OPERATORS = ON;
+ LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+ ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+ WEAK_PULL_UP_RESISTOR = OFF;
+ TURBO_BIT = ON;
+ MAX7000_IGNORE_SOFT_BUFFERS = OFF;
+ IGNORE_SOFT_BUFFERS = ON;
+ MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
+ IGNORE_LCELL_BUFFERS = OFF;
+ IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+ IGNORE_GLOBAL_BUFFERS = OFF;
+ IGNORE_CASCADE_BUFFERS = OFF;
+ IGNORE_CARRY_BUFFERS = OFF;
+ REMOVE_DUPLICATE_REGISTERS = ON;
+ REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+ ALLOW_POWER_UP_DONT_CARE = ON;
+ PCI_IO = OFF;
+ NOT_GATE_PUSH_BACK = ON;
+ SLOW_SLEW_RATE = OFF;
+ DSP_BLOCK_BALANCING = AUTO;
+ STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+ HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ RUN_ALL_TIMING_ANALYSES = ON;
+ IGNORE_CLOCK_SETTINGS = OFF;
+ DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+ CUT_OFF_IO_PIN_FEEDBACK = ON;
+ CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+ CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+ CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+ DO_MIN_ANALYSIS = ON;
+ DO_MIN_TIMING = OFF;
+ NUMBER_OF_PATHS_TO_REPORT = 200;
+ NUMBER_OF_DESTINATION_TO_REPORT = 10;
+ NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+ MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+ VERILOG_INPUT_VERSION = VERILOG_2001;
+ ENABLE_IP_DEBUG = OFF;
+ VHDL_INPUT_VERSION = VHDL93;
+ VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(mrfm)
+{
+ ORIGINAL_QUARTUS_VERSION = 3.0;
+ PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003";
+ LAST_QUARTUS_VERSION = 3.0;
+ SHOW_REGISTRATION_MESSAGE = ON;
+ USER_LIBRARIES = "e:\usrp\fpga\megacells";
+}
+THIRD_PARTY_EDA_TOOLS(mrfm)
+{
+ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+ EDA_SIMULATION_TOOL = "<NONE>";
+ EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+ EDA_BOARD_DESIGN_TOOL = "<NONE>";
+ EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+ EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+ EDA_INPUT_GND_NAME = GND;
+ EDA_INPUT_VCC_NAME = VCC;
+ EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_INPUT_DATA_FORMAT = EDIF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ RESYNTHESIS_RETIMING = FULL;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
+CLOCK(clk_120mhz)
+{
+ FMAX_REQUIREMENT = "120.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(usbclk)
+{
+ FMAX_REQUIREMENT = "48.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(SCLK)
+{
+ FMAX_REQUIREMENT = "1.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk0)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk1)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
diff --git a/toplevel/mrfm/mrfm.py b/toplevel/mrfm/mrfm.py
new file mode 100644
index 000000000..0ce46012d
--- /dev/null
+++ b/toplevel/mrfm/mrfm.py
@@ -0,0 +1,129 @@
+#!/usr/bin/env python
+#
+# This is mrfm_fft_sos.py
+# Modification of Matt's mrfm_fft.py that reads filter coefs from file
+#
+# Copyright 2004,2005 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+#
+
+from gnuradio import gr, gru
+from gnuradio import usrp
+
+class source_c(usrp.source_c):
+ def __init__(self,fpga_filename):
+ usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0,
+ fpga_filename=fpga_filename)
+
+ self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain
+ self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain
+
+ self._write_9862(0,8,0) # TX PWR Down
+ self._write_9862(0,10,0) # DAC offset
+ self._write_9862(0,11,0) # DAC offset
+ self._write_9862(0,14,0x80) # gain
+ self._write_9862(0,16,0xff) # pga
+ self._write_9862(0,18,0x0c) # TX IF
+ self._write_9862(0,19,0x01) # TX Digital
+ self._write_9862(0,20,0x00) # TX Mod
+
+ # max/min values are +/-2, so scale is set to make 2 = 32767
+
+ self._write_fpga_reg(69,0x0e) # debug mux
+ self._write_fpga_reg(5,-1)
+ self._write_fpga_reg(7,-1)
+ self._write_oe(0,0xffff, 0xffff)
+ self._write_oe(1,0xffff, 0xffff)
+ self._write_fpga_reg(14,0xf)
+
+ self.decim = None
+
+ def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11):
+ def make_val(address,value):
+ return (address << 16) | (value & 0xffff)
+
+ # gain, scale already included in a's and b's from file
+
+ self._write_fpga_reg(67,make_val(1,b20))
+ self._write_fpga_reg(67,make_val(2,b10))
+ self._write_fpga_reg(67,make_val(3,b00))
+ self._write_fpga_reg(67,make_val(4,a20))
+ self._write_fpga_reg(67,make_val(5,a10))
+
+ self._write_fpga_reg(67,make_val(7,b21))
+ self._write_fpga_reg(67,make_val(8,b11))
+ self._write_fpga_reg(67,make_val(9,b01))
+ self._write_fpga_reg(67,make_val(10,a21))
+ self._write_fpga_reg(67,make_val(11,a11))
+
+ self._write_fpga_reg(68,frac_bits) # Shift
+
+ print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10)
+ print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11)
+
+ def set_decim_rate(self,rate=None):
+ i=2
+ turn=1
+ a=1
+ b=1
+ while (rate>1) and (i<257):
+ if (rate/i) * i == rate:
+ if turn == 1:
+ if a*i<257:
+ a = a * i
+ turn = 0
+ elif b*i<257:
+ b = b * i
+ turn = 0
+ else:
+ print "Failed to set DECIMATOR"
+ return self.decim
+ elif b*i<257:
+ b = b * i
+ turn = 1
+ elif a*i<257:
+ a = a * i
+ turn = 1
+ else:
+ print "Failed to set DECIMATOR"
+ return self.decim
+ rate=rate/i
+ continue
+ i = i + 1
+ if rate > 1:
+ print "Failed to set DECIMATOR"
+ return self.decim
+ else:
+ self.decim = a*b
+ print "a = %d b = %d" % (a,b)
+ self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation
+
+ def decim_rate(self):
+ return self.decim
+
+ def set_center_freq(self,freq):
+ self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq
+
+ def set_compensator(self,a11,a12,a21,a22,shift):
+ self._write_fpga_reg(70,a11)
+ self._write_fpga_reg(71,a12)
+ self._write_fpga_reg(72,a21)
+ self._write_fpga_reg(73,a22)
+ self._write_fpga_reg(74,shift) # comp shift
+
diff --git a/toplevel/mrfm/mrfm.qpf b/toplevel/mrfm/mrfm.qpf
new file mode 100644
index 000000000..959140875
--- /dev/null
+++ b/toplevel/mrfm/mrfm.qpf
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.0"
+DATE = "17:10:11 December 20, 2004"
+
+
+# Active Revisions
+
+PROJECT_REVISION = "mrfm"
diff --git a/toplevel/mrfm/mrfm.qsf b/toplevel/mrfm/mrfm.qsf
new file mode 100644
index 000000000..ba1ae0223
--- /dev/null
+++ b/toplevel/mrfm/mrfm.qsf
@@ -0,0 +1,411 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# mrfm_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
+
+# Pin & Location Assignments
+# ==========================
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
+set_location_assignment PIN_29 -to SCLK
+set_location_assignment PIN_117 -to SDI
+set_location_assignment PIN_28 -to usbclk
+set_location_assignment PIN_107 -to usbctl[0]
+set_location_assignment PIN_106 -to usbctl[1]
+set_location_assignment PIN_105 -to usbctl[2]
+set_location_assignment PIN_100 -to usbdata[0]
+set_location_assignment PIN_84 -to usbdata[10]
+set_location_assignment PIN_83 -to usbdata[11]
+set_location_assignment PIN_82 -to usbdata[12]
+set_location_assignment PIN_79 -to usbdata[13]
+set_location_assignment PIN_78 -to usbdata[14]
+set_location_assignment PIN_77 -to usbdata[15]
+set_location_assignment PIN_99 -to usbdata[1]
+set_location_assignment PIN_98 -to usbdata[2]
+set_location_assignment PIN_95 -to usbdata[3]
+set_location_assignment PIN_94 -to usbdata[4]
+set_location_assignment PIN_93 -to usbdata[5]
+set_location_assignment PIN_88 -to usbdata[6]
+set_location_assignment PIN_87 -to usbdata[7]
+set_location_assignment PIN_86 -to usbdata[8]
+set_location_assignment PIN_85 -to usbdata[9]
+set_location_assignment PIN_104 -to usbrdy[0]
+set_location_assignment PIN_101 -to usbrdy[1]
+set_location_assignment PIN_76 -to FX2_1
+set_location_assignment PIN_75 -to FX2_2
+set_location_assignment PIN_74 -to FX2_3
+set_location_assignment PIN_116 -to io_rx_a[0]
+set_location_assignment PIN_115 -to io_rx_a[1]
+set_location_assignment PIN_114 -to io_rx_a[2]
+set_location_assignment PIN_113 -to io_rx_a[3]
+set_location_assignment PIN_108 -to io_rx_a[4]
+set_location_assignment PIN_195 -to io_rx_a[5]
+set_location_assignment PIN_196 -to io_rx_a[6]
+set_location_assignment PIN_197 -to io_rx_a[7]
+set_location_assignment PIN_200 -to io_rx_a[8]
+set_location_assignment PIN_201 -to io_rx_a[9]
+set_location_assignment PIN_202 -to io_rx_a[10]
+set_location_assignment PIN_203 -to io_rx_a[11]
+set_location_assignment PIN_206 -to io_rx_a[12]
+set_location_assignment PIN_207 -to io_rx_a[13]
+set_location_assignment PIN_208 -to io_rx_a[14]
+set_location_assignment PIN_214 -to io_rx_b[0]
+set_location_assignment PIN_215 -to io_rx_b[1]
+set_location_assignment PIN_216 -to io_rx_b[2]
+set_location_assignment PIN_217 -to io_rx_b[3]
+set_location_assignment PIN_218 -to io_rx_b[4]
+set_location_assignment PIN_219 -to io_rx_b[5]
+set_location_assignment PIN_222 -to io_rx_b[6]
+set_location_assignment PIN_223 -to io_rx_b[7]
+set_location_assignment PIN_224 -to io_rx_b[8]
+set_location_assignment PIN_225 -to io_rx_b[9]
+set_location_assignment PIN_226 -to io_rx_b[10]
+set_location_assignment PIN_227 -to io_rx_b[11]
+set_location_assignment PIN_228 -to io_rx_b[12]
+set_location_assignment PIN_233 -to io_rx_b[13]
+set_location_assignment PIN_234 -to io_rx_b[14]
+set_location_assignment PIN_175 -to io_tx_a[0]
+set_location_assignment PIN_176 -to io_tx_a[1]
+set_location_assignment PIN_177 -to io_tx_a[2]
+set_location_assignment PIN_178 -to io_tx_a[3]
+set_location_assignment PIN_179 -to io_tx_a[4]
+set_location_assignment PIN_180 -to io_tx_a[5]
+set_location_assignment PIN_181 -to io_tx_a[6]
+set_location_assignment PIN_182 -to io_tx_a[7]
+set_location_assignment PIN_183 -to io_tx_a[8]
+set_location_assignment PIN_184 -to io_tx_a[9]
+set_location_assignment PIN_185 -to io_tx_a[10]
+set_location_assignment PIN_186 -to io_tx_a[11]
+set_location_assignment PIN_187 -to io_tx_a[12]
+set_location_assignment PIN_188 -to io_tx_a[13]
+set_location_assignment PIN_193 -to io_tx_a[14]
+set_location_assignment PIN_73 -to io_tx_b[0]
+set_location_assignment PIN_68 -to io_tx_b[1]
+set_location_assignment PIN_67 -to io_tx_b[2]
+set_location_assignment PIN_66 -to io_tx_b[3]
+set_location_assignment PIN_65 -to io_tx_b[4]
+set_location_assignment PIN_64 -to io_tx_b[5]
+set_location_assignment PIN_63 -to io_tx_b[6]
+set_location_assignment PIN_62 -to io_tx_b[7]
+set_location_assignment PIN_61 -to io_tx_b[8]
+set_location_assignment PIN_60 -to io_tx_b[9]
+set_location_assignment PIN_59 -to io_tx_b[10]
+set_location_assignment PIN_58 -to io_tx_b[11]
+set_location_assignment PIN_57 -to io_tx_b[12]
+set_location_assignment PIN_56 -to io_tx_b[13]
+set_location_assignment PIN_55 -to io_tx_b[14]
+set_location_assignment PIN_152 -to master_clk
+set_location_assignment PIN_144 -to rx_a_a[0]
+set_location_assignment PIN_143 -to rx_a_a[1]
+set_location_assignment PIN_141 -to rx_a_a[2]
+set_location_assignment PIN_140 -to rx_a_a[3]
+set_location_assignment PIN_139 -to rx_a_a[4]
+set_location_assignment PIN_138 -to rx_a_a[5]
+set_location_assignment PIN_137 -to rx_a_a[6]
+set_location_assignment PIN_136 -to rx_a_a[7]
+set_location_assignment PIN_135 -to rx_a_a[8]
+set_location_assignment PIN_134 -to rx_a_a[9]
+set_location_assignment PIN_133 -to rx_a_a[10]
+set_location_assignment PIN_132 -to rx_a_a[11]
+set_location_assignment PIN_23 -to rx_a_b[0]
+set_location_assignment PIN_21 -to rx_a_b[1]
+set_location_assignment PIN_20 -to rx_a_b[2]
+set_location_assignment PIN_19 -to rx_a_b[3]
+set_location_assignment PIN_18 -to rx_a_b[4]
+set_location_assignment PIN_17 -to rx_a_b[5]
+set_location_assignment PIN_16 -to rx_a_b[6]
+set_location_assignment PIN_15 -to rx_a_b[7]
+set_location_assignment PIN_14 -to rx_a_b[8]
+set_location_assignment PIN_13 -to rx_a_b[9]
+set_location_assignment PIN_12 -to rx_a_b[10]
+set_location_assignment PIN_11 -to rx_a_b[11]
+set_location_assignment PIN_131 -to rx_b_a[0]
+set_location_assignment PIN_128 -to rx_b_a[1]
+set_location_assignment PIN_127 -to rx_b_a[2]
+set_location_assignment PIN_126 -to rx_b_a[3]
+set_location_assignment PIN_125 -to rx_b_a[4]
+set_location_assignment PIN_124 -to rx_b_a[5]
+set_location_assignment PIN_123 -to rx_b_a[6]
+set_location_assignment PIN_122 -to rx_b_a[7]
+set_location_assignment PIN_121 -to rx_b_a[8]
+set_location_assignment PIN_120 -to rx_b_a[9]
+set_location_assignment PIN_119 -to rx_b_a[10]
+set_location_assignment PIN_118 -to rx_b_a[11]
+set_location_assignment PIN_8 -to rx_b_b[0]
+set_location_assignment PIN_7 -to rx_b_b[1]
+set_location_assignment PIN_6 -to rx_b_b[2]
+set_location_assignment PIN_5 -to rx_b_b[3]
+set_location_assignment PIN_4 -to rx_b_b[4]
+set_location_assignment PIN_3 -to rx_b_b[5]
+set_location_assignment PIN_2 -to rx_b_b[6]
+set_location_assignment PIN_240 -to rx_b_b[7]
+set_location_assignment PIN_239 -to rx_b_b[8]
+set_location_assignment PIN_238 -to rx_b_b[9]
+set_location_assignment PIN_237 -to rx_b_b[10]
+set_location_assignment PIN_236 -to rx_b_b[11]
+set_location_assignment PIN_156 -to SDO
+set_location_assignment PIN_153 -to SEN_FPGA
+set_location_assignment PIN_159 -to tx_a[0]
+set_location_assignment PIN_160 -to tx_a[1]
+set_location_assignment PIN_161 -to tx_a[2]
+set_location_assignment PIN_162 -to tx_a[3]
+set_location_assignment PIN_163 -to tx_a[4]
+set_location_assignment PIN_164 -to tx_a[5]
+set_location_assignment PIN_165 -to tx_a[6]
+set_location_assignment PIN_166 -to tx_a[7]
+set_location_assignment PIN_167 -to tx_a[8]
+set_location_assignment PIN_168 -to tx_a[9]
+set_location_assignment PIN_169 -to tx_a[10]
+set_location_assignment PIN_170 -to tx_a[11]
+set_location_assignment PIN_173 -to tx_a[12]
+set_location_assignment PIN_174 -to tx_a[13]
+set_location_assignment PIN_38 -to tx_b[0]
+set_location_assignment PIN_39 -to tx_b[1]
+set_location_assignment PIN_41 -to tx_b[2]
+set_location_assignment PIN_42 -to tx_b[3]
+set_location_assignment PIN_43 -to tx_b[4]
+set_location_assignment PIN_44 -to tx_b[5]
+set_location_assignment PIN_45 -to tx_b[6]
+set_location_assignment PIN_46 -to tx_b[7]
+set_location_assignment PIN_47 -to tx_b[8]
+set_location_assignment PIN_48 -to tx_b[9]
+set_location_assignment PIN_49 -to tx_b[10]
+set_location_assignment PIN_50 -to tx_b[11]
+set_location_assignment PIN_53 -to tx_b[12]
+set_location_assignment PIN_54 -to tx_b[13]
+set_location_assignment PIN_158 -to TXSYNC_A
+set_location_assignment PIN_37 -to TXSYNC_B
+set_location_assignment PIN_235 -to io_rx_b[15]
+set_location_assignment PIN_24 -to io_tx_b[15]
+set_location_assignment PIN_213 -to io_rx_a[15]
+set_location_assignment PIN_194 -to io_tx_a[15]
+set_location_assignment PIN_1 -to MYSTERY_SIGNAL
+
+# Timing Assignments
+# ==================
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name TOP_LEVEL_ENTITY mrfm
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name MAX_SCC_SIZE 50
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name START_TIME "0 ns"
+set_global_assignment -name GLITCH_INTERVAL "1 ns"
+
+# Design Assistant Assignments
+# ============================
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT OFF
+set_global_assignment -name HCPY_VREF_PINS OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# -----------------
+# start CLOCK(SCLK)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
+
+# end CLOCK(SCLK)
+# ---------------
+
+# -----------------------
+# start CLOCK(master_clk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
+
+# end CLOCK(master_clk)
+# ---------------------
+
+# -------------------
+# start CLOCK(usbclk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
+
+# end CLOCK(usbclk)
+# -----------------
+
+# ----------------------
+# start ENTITY(mrfm)
+
+ # Timing Assignments
+ # ==================
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+
+# end ENTITY(mrfm)
+# --------------------
+
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name VERILOG_FILE mrfm.vh
+set_global_assignment -name VERILOG_FILE biquad_2stage.v
+set_global_assignment -name VERILOG_FILE mrfm_compensator.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE mrfm_proc.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
+set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE mrfm.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT" \ No newline at end of file
diff --git a/toplevel/mrfm/mrfm.v b/toplevel/mrfm/mrfm.v
new file mode 100644
index 000000000..cf9d1119a
--- /dev/null
+++ b/toplevel/mrfm/mrfm.v
@@ -0,0 +1,199 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Top level module for a full setup with DUCs and DDCs
+
+// Uncomment the following to include optional circuitry
+
+`include "mrfm.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+
+module mrfm
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ input wire [11:0] rx_a_b,
+ input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ output wire TXSYNC_B,
+
+ // USB interface
+ input usbclk,
+ input wire [2:0] usbctl,
+ output wire [1:0] usbrdy,
+ inout [15:0] usbdata, // NB Careful, inout
+
+ // These are the general purpose i/o's that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ inout wire [15:0] io_rx_b
+ );
+ wire [15:0] debugdata,debugctrl;
+ assign MYSTERY_SIGNAL = 1'b0;
+
+ wire clk64;
+
+ wire WR = usbctl[0];
+ wire RD = usbctl[1];
+ wire OE = usbctl[2];
+
+ wire have_space, have_pkt_rdy;
+ assign usbrdy[0] = have_space;
+ assign usbrdy[1] = have_pkt_rdy;
+
+ wire tx_underrun, rx_overrun;
+ wire clear_status = FX2_1;
+ assign FX2_2 = rx_overrun;
+ assign FX2_3 = tx_underrun;
+
+ wire [15:0] usbdata_out;
+
+ wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
+
+ wire tx_realsignals;
+ wire [3:0] rx_numchan;
+
+ wire [15:0] tx_debugbus, rx_debugbus;
+
+ wire enable_tx, enable_rx;
+ wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+ wire [7:0] settings;
+
+ // Tri-state bus macro
+ bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+ assign clk64 = master_clk;
+
+ wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx;
+ wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+
+ wire serial_strobe;
+ wire [6:0] serial_addr;
+ wire [31:0] serial_data;
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ setting_reg #(`FR_TX_MUX)
+ sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Signal Processing Chain
+
+ reg [15:0] adc0;
+ wire [15:0] dac0;
+ wire [15:0] i,q,ip,qp;
+ wire strobe_out;
+ wire sync_out;
+
+ always @(posedge clk64)
+ adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0};
+
+ wire [15:0] adc0_corr;
+ rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr),
+ .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0));
+
+ //wire [63:0] filt_debug = 64'd0;
+
+ mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out),
+ .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out),
+ .debugbus( /* filt_debug */ ));
+
+ wire txsync = 1'b0;
+ assign TXSYNC_A = txsync;
+ assign TXSYNC_B = txsync;
+
+ assign tx_a = dac0[15:2];
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////
+ // Data Collection on RX Buffer
+
+ assign rx_numchan[0] = 1'b0;
+ setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),
+ .in(serial_data),.out(rx_numchan[3:1]));
+
+ rx_buffer rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(i),.ch_1(q),
+ .ch_2(ip),.ch_3(qp),
+ .ch_4(16'd0),.ch_5(16'd0),
+ .ch_6(16'd0),.ch_7(16'd0),
+ .rxclk(clk64),.rxstrobe(strobe_out),
+ .clear_status(clear_status),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .debugbus(rx_debugbus) );
+
+ //////////////////////////////////////////////////////////////////////////////
+ // Control Functions
+
+ wire [31:0] capabilities = 32'd2;
+
+ serial_io serial_io
+ ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+ .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) );
+
+ wire [15:0] reg_0,reg_1,reg_2,reg_3;
+ master_control master_control
+ ( .master_clk(clk64),.usbclk(usbclk),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ .debug_0({15'd0,sync_out}), //filt_debug[63:48]),
+ .debug_1({15'd0,sync_out}), //filt_debug[47:32]),
+ .debug_2({15'd0,sync_out}), //filt_debug[31:16]),
+ .debug_3({15'd0,sync_out}), //filt_debug[15:0]),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+ io_pins io_pins
+ (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+endmodule // mrfm
+
diff --git a/toplevel/mrfm/mrfm.vh b/toplevel/mrfm/mrfm.vh
new file mode 100644
index 000000000..808342d8d
--- /dev/null
+++ b/toplevel/mrfm/mrfm.vh
@@ -0,0 +1,21 @@
+
+
+// MRFM Register defines
+
+`define FR_MRFM_DECIM 7'd64
+`define FR_MRFM_FREQ 7'd65
+`define FR_MRFM_PHASE 7'd66
+`define FR_MRFM_IIR_COEFF 7'd67
+`define FR_MRFM_IIR_SHIFT 7'd68
+`define FR_MRFM_DEBUG 7'd69
+`define FR_MRFM_COMP_A11 7'd70
+`define FR_MRFM_COMP_A12 7'd71
+`define FR_MRFM_COMP_A21 7'd72
+`define FR_MRFM_COMP_A22 7'd73
+`define FR_MRFM_COMP_SHIFT 7'd74
+`define FR_USER_11 7'd75
+`define FR_USER_12 7'd76
+`define FR_USER_13 7'd77
+`define FR_USER_14 7'd78
+`define FR_USER_15 7'd79
+
diff --git a/toplevel/mrfm/mrfm_compensator.v b/toplevel/mrfm/mrfm_compensator.v
new file mode 100644
index 000000000..f44b73b2f
--- /dev/null
+++ b/toplevel/mrfm/mrfm_compensator.v
@@ -0,0 +1,80 @@
+
+
+module mrfm_compensator (input clock, input reset, input strobe_in,
+ input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
+ input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out);
+
+ wire [15:0] a11,a12,a21,a22;
+ reg [15:0] i_in_reg, q_in_reg;
+ wire [30:0] product;
+ reg [3:0] phase;
+ wire [15:0] data,coeff;
+ wire [7:0] shift;
+ wire [33:0] accum;
+ wire [15:0] scaled_accum;
+ wire enable_acc;
+
+ setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(a11),.changed());
+ setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(a12),.changed());
+ setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(a21),.changed());
+ setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(a22),.changed());
+ setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset),
+ .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out(shift),.changed());
+
+ mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() );
+ acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
+ .addend(product),.sum(accum) );
+ shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ i_in_reg <= #1 16'd0;
+ q_in_reg <= #1 16'd0;
+ end
+ else if(strobe_in)
+ begin
+ i_in_reg <= #1 i_in;
+ q_in_reg <= #1 q_in;
+ end
+
+ always @(posedge clock)
+ if(reset)
+ phase <= #1 4'd0;
+ else if(strobe_in)
+ phase <= #1 4'd1;
+ else if(strobe_in != 4'd8)
+ phase <= #1 phase + 4'd1;
+
+ assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg :
+ ((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0;
+
+ assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 :
+ (phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0;
+
+ assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8);
+ assign enable_acc = ~clear_acc;
+
+ always @(posedge clock)
+ if(reset)
+ i_out <= #1 16'd0;
+ else if(phase == 4'd4)
+ i_out <= #1 scaled_accum;
+
+ always @(posedge clock)
+ if(reset)
+ q_out <= #1 16'd0;
+ else if(phase == 4'd7)
+ q_out <= #1 scaled_accum;
+
+
+endmodule // mrfm_compensator
diff --git a/toplevel/mrfm/mrfm_fft.py b/toplevel/mrfm/mrfm_fft.py
new file mode 100755
index 000000000..343ab0197
--- /dev/null
+++ b/toplevel/mrfm/mrfm_fft.py
@@ -0,0 +1,319 @@
+#!/usr/bin/env python
+#
+# This is mrfm_fft_sos.py
+# Modification of Matt's mrfm_fft.py that reads filter coefs from file
+#
+# Copyright 2004,2005 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+#
+
+from gnuradio import gr, gru
+from gnuradio import usrp
+from gnuradio import eng_notation
+from gnuradio.eng_option import eng_option
+from gnuradio.wxgui import stdgui, fftsink, waterfallsink, scopesink, form, slider
+from optparse import OptionParser
+import wx
+import sys
+import mrfm
+
+
+def pick_subdevice(u):
+ """
+ The user didn't specify a subdevice on the command line.
+ If there's a daughterboard on A, select A.
+ If there's a daughterboard on B, select B.
+ Otherwise, select A.
+ """
+ if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem
+ return (0, 0)
+ if u.db[1][0].dbid() >= 0:
+ return (1, 0)
+ return (0, 0)
+
+def read_ints(filename):
+ try:
+ f = open(filename)
+ ints = [ int(i) for i in f.read().split() ]
+ f.close()
+ return ints
+ except:
+ return []
+
+class app_flow_graph(stdgui.gui_flow_graph):
+ def __init__(self, frame, panel, vbox, argv):
+ stdgui.gui_flow_graph.__init__(self)
+
+ self.frame = frame
+ self.panel = panel
+
+ parser = OptionParser(option_class=eng_option)
+ parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None,
+ help="select USRP Rx side A or B (default=first one with a daughterboard)")
+ parser.add_option("-d", "--decim", type="int", default=16,
+ help="set fgpa decimation rate to DECIM [default=%default]")
+ parser.add_option("-f", "--freq", type="eng_float", default=None,
+ help="set frequency to FREQ", metavar="FREQ")
+ parser.add_option("-g", "--gain", type="eng_float", default=None,
+ help="set gain in dB (default is midpoint)")
+ parser.add_option("-W", "--waterfall", action="store_true", default=False,
+ help="Enable waterfall display")
+ parser.add_option("-8", "--width-8", action="store_true", default=False,
+ help="Enable 8-bit samples across USB")
+ parser.add_option("-S", "--oscilloscope", action="store_true", default=False,
+ help="Enable oscilloscope display")
+ parser.add_option("-F", "--filename", default=None,
+ help="Name of file with filter coefficients")
+ parser.add_option("-C", "--cfilename", default=None,
+ help="Name of file with compensator coefficients")
+ parser.add_option("-B", "--bitstream", default="mrfm.rbf",
+ help="Name of FPGA Bitstream file (.rbf)")
+ parser.add_option("-n", "--frame-decim", type="int", default=20,
+ help="set oscope frame decimation factor to n [default=12]")
+ (options, args) = parser.parse_args()
+ if len(args) != 0:
+ parser.print_help()
+ sys.exit(1)
+
+ self.show_debug_info = True
+
+ # default filter coefs
+ b00 = b01 = 16384
+ b10 = b20 = a10 = a20 = b11 = b21 = a11 = a21 = 0
+
+ ba = read_ints(options.filename)
+ if len(ba) >= 6:
+ b00 = ba[0]; b10 = ba[1]; b20 = ba[2]; a10 = ba[4]; a20 = ba[5]
+ if len(ba) >= 12:
+ b01 = ba[6]; b11 = ba[7]; b21 = ba[8]; a11 = ba[10]; a21=ba[11]
+ print b00, b10, b20, a10, a20, b01, b11, b21, a11, a21
+
+ # default compensator coefficients
+ c11 = c22 = 1
+ c12 = c21 = cscale = 0
+
+ cs = read_ints(options.cfilename)
+ if len(cs) >= 5:
+ c11 = cs[0]; c12 = cs[1]; c21 = cs[2]; c22 = cs[3]; cscale = cs[4]
+ print c11, c12, c21, c22, cscale
+
+ # build the graph
+ self.u = mrfm.source_c(options.bitstream)
+
+ self.u.set_decim_rate(options.decim)
+ self.u.set_center_freq(options.freq)
+
+ frac_bits = 14
+ self.u.set_coeffs(frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11)
+
+ self.u.set_compensator(c11,c12,c21,c22,cscale)
+
+ if options.rx_subdev_spec is None:
+ options.rx_subdev_spec = pick_subdevice(self.u)
+ self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec))
+
+ if options.width_8:
+ width = 8
+ shift = 8
+ format = self.u.make_format(width, shift)
+ print "format =", hex(format)
+ r = self.u.set_format(format)
+ print "set_format =", r
+
+ # determine the daughterboard subdevice we're using
+ self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec)
+
+ #input_rate = self.u.adc_freq() / self.u.decim_rate()
+ input_rate = self.u.adc_freq() / options.decim
+
+ # fft_rate = 15
+ fft_rate = 5
+
+ self.deint = gr.deinterleave(gr.sizeof_gr_complex)
+ self.connect(self.u,self.deint)
+
+ if options.waterfall:
+ self.scope1=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate,
+ fft_rate=fft_rate)
+ self.scope2=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate,
+ fft_rate=fft_rate)
+
+ elif options.oscilloscope:
+ self.scope1 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) # added option JPJ 4/21/2006
+ self.scope2 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim)
+
+ else:
+ self.scope1 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate,
+ fft_rate=fft_rate)
+ self.scope2 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate,
+ fft_rate=fft_rate)
+
+ # Show I, I' on top scope panel, Q, Q' on bottom
+ #self.fin = gr.complex_to_float()
+ #self.fout = gr.complex_to_float()
+
+ #self.connect((self.deint,0), self.fin)
+ #self.connect((self.deint,1), self.fout)
+
+ #self.ii = gr.float_to_complex()
+ #self.qq = gr.float_to_complex()
+
+ #self.connect((self.fin,0), (self.ii,0))
+ #self.connect((self.fout,0), (self.ii,1))
+ #self.connect((self.fin,1), (self.qq,0))
+ #self.connect((self.fout,1), (self.qq,1))
+
+ #self.connect(self.ii, self.scope1)
+ #self.connect(self.qq, self.scope2)
+
+ self.connect ((self.deint,0),self.scope1)
+ self.connect ((self.deint,1),self.scope2)
+
+ self._build_gui(vbox)
+
+ # set initial values
+
+ if options.gain is None:
+ # if no gain was specified, use the mid-point in dB
+ g = self.subdev.gain_range()
+ options.gain = float(g[0]+g[1])/2
+
+ if options.freq is None:
+ # if no freq was specified, use the mid-point
+ r = self.subdev.freq_range()
+ options.freq = float(r[0]+r[1])/2
+
+ self.set_gain(options.gain)
+
+ if not(self.set_freq(options.freq)):
+ self._set_status_msg("Failed to set initial frequency")
+
+ if self.show_debug_info:
+ self.myform['decim'].set_value(self.u.decim_rate())
+ self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate())
+ self.myform['dbname'].set_value(self.subdev.name())
+
+
+ def _set_status_msg(self, msg):
+ self.frame.GetStatusBar().SetStatusText(msg, 0)
+
+ def _build_gui(self, vbox):
+
+ def _form_set_freq(kv):
+ return self.set_freq(kv['freq'])
+
+ vbox.Add(self.scope1.win, 10, wx.EXPAND)
+ vbox.Add(self.scope2.win, 10, wx.EXPAND)
+
+ # add control area at the bottom
+ self.myform = myform = form.form()
+ hbox = wx.BoxSizer(wx.HORIZONTAL)
+ hbox.Add((5,0), 0, 0)
+ myform['freq'] = form.float_field(
+ parent=self.panel, sizer=hbox, label="Center freq", weight=1,
+ callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg))
+
+ hbox.Add((5,0), 0, 0)
+ g = self.subdev.gain_range()
+ myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain",
+ weight=3,
+ min=int(g[0]), max=int(g[1]),
+ callback=self.set_gain)
+
+ hbox.Add((5,0), 0, 0)
+ vbox.Add(hbox, 0, wx.EXPAND)
+
+ self._build_subpanel(vbox)
+
+ def _build_subpanel(self, vbox_arg):
+ # build a secondary information panel (sometimes hidden)
+
+ # FIXME figure out how to have this be a subpanel that is always
+ # created, but has its visibility controlled by foo.Show(True/False)
+
+ if not(self.show_debug_info):
+ return
+
+ panel = self.panel
+ vbox = vbox_arg
+ myform = self.myform
+
+ #panel = wx.Panel(self.panel, -1)
+ #vbox = wx.BoxSizer(wx.VERTICAL)
+
+ hbox = wx.BoxSizer(wx.HORIZONTAL)
+ hbox.Add((5,0), 0)
+ myform['decim'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="Decim")
+
+ hbox.Add((5,0), 1)
+ myform['fs@usb'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="Fs@USB")
+
+ hbox.Add((5,0), 1)
+ myform['dbname'] = form.static_text_field(
+ parent=panel, sizer=hbox)
+
+ hbox.Add((5,0), 1)
+ myform['baseband'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="Analog BB")
+
+ hbox.Add((5,0), 1)
+ myform['ddc'] = form.static_float_field(
+ parent=panel, sizer=hbox, label="DDC")
+
+ hbox.Add((5,0), 0)
+ vbox.Add(hbox, 0, wx.EXPAND)
+
+
+
+ def set_freq(self, target_freq):
+ """
+ Set the center frequency we're interested in.
+
+ @param target_freq: frequency in Hz
+ @rypte: bool
+
+ Tuning is a two step process. First we ask the front-end to
+ tune as close to the desired frequency as it can. Then we use
+ the result of that operation and our target_frequency to
+ determine the value for the digital down converter.
+ """
+ r = self.u.tune(0, self.subdev, target_freq)
+
+ if r:
+ self.myform['freq'].set_value(target_freq) # update displayed value
+ if self.show_debug_info:
+ self.myform['baseband'].set_value(r.baseband_freq)
+ self.myform['ddc'].set_value(r.dxc_freq)
+ return True
+
+ return False
+
+ def set_gain(self, gain):
+ self.myform['gain'].set_value(gain) # update displayed value
+ self.subdev.set_gain(gain)
+
+
+def main ():
+ app = stdgui.stdapp(app_flow_graph, "USRP FFT", nstatus=1)
+ app.MainLoop()
+
+if __name__ == '__main__':
+ main ()
diff --git a/toplevel/mrfm/mrfm_proc.v b/toplevel/mrfm/mrfm_proc.v
new file mode 100644
index 000000000..80de9fc90
--- /dev/null
+++ b/toplevel/mrfm/mrfm_proc.v
@@ -0,0 +1,96 @@
+
+`include "mrfm.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+
+module mrfm_proc (input clock, input reset, input enable,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+ input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out,
+ output wire [15:0] i, output wire [15:0] q,
+ output wire [15:0] ip, output wire [15:0] qp,
+ output wire strobe_out, output wire [63:0] debugbus);
+
+ // Strobes
+ wire sample_strobe, strobe_0, strobe_1, strobe_2;
+ assign sample_strobe = 1'b1;
+ wire [7:0] rate_0, rate_1, rate_2;
+
+ setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0}));
+
+ strobe_gen strobe_gen_0
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) );
+ strobe_gen strobe_gen_1
+ ( .clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) );
+
+ wire [31:0] phase;
+
+ assign sync_out = phase[31];
+ wire [15:0] i_decim_0, i_decim_1, i_decim_2;
+ wire [15:0] q_decim_0, q_decim_1, q_decim_2;
+
+ wire [15:0] i_interp_0, i_interp_1, i_interp_2;
+ wire [15:0] q_interp_0, q_interp_1, q_interp_2;
+
+ wire [15:0] i_filt, q_filt, i_comp, q_comp;
+
+ assign ip=i_comp;
+ assign qp=q_comp;
+
+ phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc
+ (.clk(clock),.reset(reset),.enable(enable),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .strobe(sample_strobe),.phase(phase) );
+
+ cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable),
+ .xi(signal_in),.yi(16'd0),.zi(phase[31:16]),
+ .xo(i_decim_0),.yo(q_decim_0),.zo() );
+
+ cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0),
+ .signal_in(i_decim_0),.signal_out(i_decim_1));
+ cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1),
+ .signal_in(i_decim_1),.signal_out(i));
+
+ cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0),
+ .signal_in(q_decim_0),.signal_out(q_decim_1));
+ cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1),
+ .signal_in(q_decim_1),.signal_out(q));
+
+ assign strobe_out = strobe_1;
+
+ biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1),
+ .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
+ .sample_in(i),.sample_out(i_filt),.debugbus(debugbus));
+
+ biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1),
+ .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
+ .sample_in(q),.sample_out(q_filt),.debugbus());
+
+ mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1),
+ .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
+ .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp));
+
+ cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0),
+ .signal_in(i_comp),.signal_out(i_interp_0));
+ cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe),
+ .signal_in(i_interp_0),.signal_out(i_interp_1));
+
+ cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0),
+ .signal_in(q_comp),.signal_out(q_interp_0));
+ cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable),
+ .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe),
+ .signal_in(q_interp_0),.signal_out(q_interp_1));
+
+ cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable),
+ .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]),
+ .xo(signal_out),.yo(),.zo() );
+
+endmodule // mrfm_proc
diff --git a/toplevel/mrfm/shifter.v b/toplevel/mrfm/shifter.v
new file mode 100644
index 000000000..08d49db6e
--- /dev/null
+++ b/toplevel/mrfm/shifter.v
@@ -0,0 +1,106 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2005,2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift);
+ // Wish we could do assign out = in[15+shift:shift];
+
+ reg [15:0] quotient, remainder;
+ wire [15:0] out_unclipped;
+ reg [18:0] msbs;
+ wire in_range;
+
+ always @*
+ case(shift)
+ 0 : quotient = in[15:0];
+ 1 : quotient = in[16:1];
+ 2 : quotient = in[17:2];
+ 3 : quotient = in[18:3];
+ 4 : quotient = in[19:4];
+ 5 : quotient = in[20:5];
+ 6 : quotient = in[21:6];
+ 7 : quotient = in[22:7];
+ 8 : quotient = in[23:8];
+ 9 : quotient = in[24:9];
+ 10 : quotient = in[25:10];
+ 11 : quotient = in[26:11];
+ 12 : quotient = in[27:12];
+ 13 : quotient = in[28:13];
+ 14 : quotient = in[29:14];
+ 15 : quotient = in[30:15];
+ 16 : quotient = in[31:16];
+ 17 : quotient = in[32:17];
+ 18 : quotient = in[33:18];
+ default : quotient = in[15:0];
+ endcase // case(shift)
+
+ always @*
+ case(shift)
+ 0 : remainder = 16'b0;
+ 1 : remainder = {in[0],15'b0};
+ 2 : remainder = {in[1:0],14'b0};
+ 3 : remainder = {in[2:0],13'b0};
+ 4 : remainder = {in[3:0],12'b0};
+ 5 : remainder = {in[4:0],11'b0};
+ 6 : remainder = {in[5:0],10'b0};
+ 7 : remainder = {in[6:0],9'b0};
+ 8 : remainder = {in[7:0],8'b0};
+ 9 : remainder = {in[8:0],7'b0};
+ 10 : remainder = {in[9:0],6'b0};
+ 11 : remainder = {in[10:0],5'b0};
+ 12 : remainder = {in[11:0],4'b0};
+ 13 : remainder = {in[12:0],3'b0};
+ 14 : remainder = {in[13:0],2'b0};
+ 15 : remainder = {in[14:0],1'b0};
+ 16 : remainder = in[15:0];
+ 17 : remainder = in[16:1];
+ 18 : remainder = in[17:2];
+ default : remainder = 16'b0;
+ endcase // case(shift)
+
+ always @*
+ case(shift)
+ 0 : msbs = in[33:15];
+ 1 : msbs = {in[33],in[33:16]};
+ 2 : msbs = {{2{in[33]}},in[33:17]};
+ 3 : msbs = {{3{in[33]}},in[33:18]};
+ 4 : msbs = {{4{in[33]}},in[33:19]};
+ 5 : msbs = {{5{in[33]}},in[33:20]};
+ 6 : msbs = {{6{in[33]}},in[33:21]};
+ 7 : msbs = {{7{in[33]}},in[33:22]};
+ 8 : msbs = {{8{in[33]}},in[33:23]};
+ 9 : msbs = {{9{in[33]}},in[33:24]};
+ 10 : msbs = {{10{in[33]}},in[33:25]};
+ 11 : msbs = {{11{in[33]}},in[33:26]};
+ 12 : msbs = {{12{in[33]}},in[33:27]};
+ 13 : msbs = {{13{in[33]}},in[33:28]};
+ 14 : msbs = {{14{in[33]}},in[33:29]};
+ 15 : msbs = {{15{in[33]}},in[33:30]};
+ 16 : msbs = {{16{in[33]}},in[33:31]};
+ 17 : msbs = {{17{in[33]}},in[33:32]};
+ 18 : msbs = {{18{in[33]}},in[33]};
+ default : msbs = in[33:15];
+ endcase // case(shift)
+
+ assign in_range = &msbs | ~(|msbs);
+ assign out_unclipped = quotient + (in[33] & |remainder);
+ assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}};
+
+endmodule // shifter
diff --git a/toplevel/sizetest/sizetest.csf b/toplevel/sizetest/sizetest.csf
new file mode 100644
index 000000000..4b724e7f5
--- /dev/null
+++ b/toplevel/sizetest/sizetest.csf
@@ -0,0 +1,160 @@
+COMPILER_SETTINGS
+{
+ IO_PLACEMENT_OPTIMIZATION = OFF;
+ ENABLE_DRC_SETTINGS = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+ PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ TRUE_WYSIWYG_FLOW = OFF;
+ SEED = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = OFF;
+ OPTIMIZE_TIMING = OFF;
+ OPTIMIZE_HOLD_TIMING = OFF;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = ON;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |sizetest;
+ FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = SLD_HUB_INST;
+ HUB_ENTITY_NAME = SLD_HUB;
+}
+CHIP(sizetest)
+{
+ DEVICE = EP1C12Q240C8;
+ DEVICE_FILTER_PACKAGE = "ANY QFP";
+ DEVICE_FILTER_PIN_COUNT = 240;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+ ENABLE_SIGNALTAP = Off;
+ AUTO_ENABLE_SMART_COMPILE = On;
+}
diff --git a/toplevel/sizetest/sizetest.psf b/toplevel/sizetest/sizetest.psf
new file mode 100644
index 000000000..e4fc6aa27
--- /dev/null
+++ b/toplevel/sizetest/sizetest.psf
@@ -0,0 +1,228 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+ HCPY_ALOAD_SIGNALS = OFF;
+ HCPY_VREF_PINS = OFF;
+ HCPY_CAT = OFF;
+ HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+ ACLK_RULE_IMSZER_ADOMAIN = OFF;
+ ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+ ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+ ACLK_CAT = OFF;
+ SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+ SIGNALRACE_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+ NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+ NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+ NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+ NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+ NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+ NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+ NONSYNCHSTRUCT_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+ TIMING_RULE_COIN_CLKEDGE = OFF;
+ TIMING_RULE_SHIFT_REG = OFF;
+ TIMING_RULE_HIGH_FANOUTS = OFF;
+ TIMING_CAT = OFF;
+ RESET_RULE_ALL = OFF;
+ RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_REG_ASNYCH = OFF;
+ RESET_RULE_COMB_ASYNCH_RESET = OFF;
+ RESET_RULE_IMSYNCH_EXRESET = OFF;
+ RESET_RULE_UNSYNCH_EXRESET = OFF;
+ RESET_RULE_INPINS_RESETNET = OFF;
+ RESET_CAT = OFF;
+ CLK_RULE_ALL = OFF;
+ CLK_RULE_MIX_EDGES = OFF;
+ CLK_RULE_CLKNET_CLKSPINES = OFF;
+ CLK_RULE_INPINS_CLKNET = OFF;
+ CLK_RULE_GATING_SCHEME = OFF;
+ CLK_RULE_INV_CLOCK = OFF;
+ CLK_RULE_COMB_CLOCK = OFF;
+ CLK_CAT = OFF;
+ HCPY_EXCEED_USER_IO_USAGE = OFF;
+ HCPY_EXCEED_RAM_USAGE = OFF;
+ NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+ SIGNALRACE_RULE_TRISTATE = OFF;
+ ASSG_RULE_MISSING_TIMING = OFF;
+ ASSG_RULE_MISSING_FMAX = OFF;
+ ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+ AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+ AUTO_RAM_RECOGNITION = ON;
+ REMOVE_DUPLICATE_LOGIC = ON;
+ AUTO_MERGE_PLLS = ON;
+ AUTO_OPEN_DRAIN_PINS = ON;
+ AUTO_CARRY_CHAINS = ON;
+ AUTO_DELAY_CHAINS = ON;
+ STRATIX_CARRY_CHAIN_LENGTH = 70;
+ AUTO_PACKED_REG_CYCLONE = "MINIMIZE AREA WITH CHAINS";
+ CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED;
+ AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+ AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+ AUTO_GLOBAL_CLOCK = ON;
+ LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+ ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+ WEAK_PULL_UP_RESISTOR = OFF;
+ IGNORE_SOFT_BUFFERS = ON;
+ IGNORE_LCELL_BUFFERS = OFF;
+ IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+ IGNORE_GLOBAL_BUFFERS = OFF;
+ IGNORE_CASCADE_BUFFERS = OFF;
+ IGNORE_CARRY_BUFFERS = OFF;
+ REMOVE_DUPLICATE_REGISTERS = ON;
+ REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+ ALLOW_POWER_UP_DONT_CARE = ON;
+ PCI_IO = OFF;
+ NOT_GATE_PUSH_BACK = ON;
+ SLOW_SLEW_RATE = OFF;
+ STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+ HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ RUN_ALL_TIMING_ANALYSES = ON;
+ IGNORE_CLOCK_SETTINGS = OFF;
+ DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+ CUT_OFF_IO_PIN_FEEDBACK = ON;
+ CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+ CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+ CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+ DO_MIN_ANALYSIS = ON;
+ DO_MIN_TIMING = OFF;
+ NUMBER_OF_PATHS_TO_REPORT = 200;
+ NUMBER_OF_DESTINATION_TO_REPORT = 10;
+ NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+ MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+ VERILOG_INPUT_VERSION = VERILOG_2001;
+ ENABLE_IP_DEBUG = OFF;
+ VHDL_INPUT_VERSION = VHDL93;
+ VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(sizetest)
+{
+ USER_LIBRARIES = "e:\fpga\megacells\";
+ ORIGINAL_QUARTUS_VERSION = 3.0;
+ PROJECT_CREATION_TIME_DATE = "22:00:25 SEPTEMBER 28, 2003";
+ LAST_QUARTUS_VERSION = 3.0;
+ SHOW_REGISTRATION_MESSAGE = ON;
+}
+THIRD_PARTY_EDA_TOOLS(sizetest)
+{
+ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+ EDA_SIMULATION_TOOL = "<NONE>";
+ EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+ EDA_BOARD_DESIGN_TOOL = "<NONE>";
+ EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+ EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+ EDA_INPUT_GND_NAME = GND;
+ EDA_INPUT_VCC_NAME = VCC;
+ EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_INPUT_DATA_FORMAT = EDIF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ RESYNTHESIS_RETIMING = FULL;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
diff --git a/toplevel/sizetest/sizetest.quartus b/toplevel/sizetest/sizetest.quartus
new file mode 100644
index 000000000..d1eaf227a
--- /dev/null
+++ b/toplevel/sizetest/sizetest.quartus
@@ -0,0 +1,19 @@
+COMPILER_SETTINGS_LIST
+{
+ COMPILER_SETTINGS = sizetest;
+}
+SIMULATOR_SETTINGS_LIST
+{
+ SIMULATOR_SETTINGS = sizetest;
+}
+SOFTWARE_SETTINGS_LIST
+{
+ SOFTWARE_SETTINGS = Debug;
+ SOFTWARE_SETTINGS = Release;
+}
+FILES
+{
+ VERILOG_FILE = ..\..\sdr_lib\cordic_stage.v;
+ VERILOG_FILE = ..\..\sdr_lib\cordic.v;
+ VERILOG_FILE = sizetest.v;
+}
diff --git a/toplevel/sizetest/sizetest.ssf b/toplevel/sizetest/sizetest.ssf
new file mode 100644
index 000000000..1aceab1f1
--- /dev/null
+++ b/toplevel/sizetest/sizetest.ssf
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+ ESTIMATE_POWER_CONSUMPTION = OFF;
+ GLITCH_INTERVAL = 1NS;
+ GLITCH_DETECTION = OFF;
+ SIMULATION_COVERAGE = ON;
+ CHECK_OUTPUTS = OFF;
+ SETUP_HOLD_DETECTION = OFF;
+ POWER_ESTIMATION_START_TIME = "0 NS";
+ ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+ SIMULATION_MODE = TIMING;
+ START_TIME = 0NS;
+ USE_COMPILER_SETTINGS = sizetest;
+}
diff --git a/toplevel/sizetest/sizetest.v b/toplevel/sizetest/sizetest.v
new file mode 100644
index 000000000..cdbd0861a
--- /dev/null
+++ b/toplevel/sizetest/sizetest.v
@@ -0,0 +1,39 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+module sizetest(input clock,
+ input reset,
+ input enable,
+ input [15:0]xi,
+ input [15:0] yi,
+ input [15:0] zi,
+ output [15:0] xo,
+ output [15:0] yo,
+ output [15:0] zo
+// input [15:0] constant
+ );
+
+wire [16:0] zo;
+
+cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo );
+
+endmodule
diff --git a/toplevel/usrp_multi/usrp_multi.csf b/toplevel/usrp_multi/usrp_multi.csf
new file mode 100644
index 000000000..2f5df2bca
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.csf
@@ -0,0 +1,444 @@
+COMPILER_SETTINGS
+{
+ IO_PLACEMENT_OPTIMIZATION = OFF;
+ ENABLE_DRC_SETTINGS = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+ PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ TRUE_WYSIWYG_FLOW = OFF;
+ SEED = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = "NORMAL COMPILATION";
+ OPTIMIZE_HOLD_TIMING = OFF;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = OFF;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |usrp_multi;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
+ FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = SLD_HUB_INST;
+ HUB_ENTITY_NAME = SLD_HUB;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+ ENABLE_SIGNALTAP = Off;
+ AUTO_ENABLE_SMART_COMPILE = On;
+}
+CHIP(usrp_multi)
+{
+ DEVICE = EP1C12Q240C8;
+ DEVICE_FILTER_PACKAGE = "ANY QFP";
+ DEVICE_FILTER_PIN_COUNT = 240;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = OFF;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = ON;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
+ STRATIX_DEVICE_IO_STANDARD = LVTTL;
+ CLOCK_SOURCE = INTERNAL;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ SCLK : LOCATION = Pin_101;
+ SDI : LOCATION = Pin_100;
+ SEN : LOCATION = Pin_98;
+ SLD : LOCATION = Pin_95;
+ adc1_data[0] : LOCATION = Pin_5;
+ adc1_data[10] : LOCATION = Pin_235;
+ adc1_data[11] : LOCATION = Pin_234;
+ adc1_data[1] : LOCATION = Pin_4;
+ adc1_data[2] : LOCATION = Pin_3;
+ adc1_data[3] : LOCATION = Pin_2;
+ adc1_data[4] : LOCATION = Pin_1;
+ adc1_data[4] : IO_STANDARD = LVTTL;
+ adc1_data[5] : LOCATION = Pin_240;
+ adc1_data[6] : LOCATION = Pin_239;
+ adc1_data[7] : LOCATION = Pin_238;
+ adc1_data[8] : LOCATION = Pin_237;
+ adc1_data[9] : LOCATION = Pin_236;
+ adc2_data[0] : LOCATION = Pin_20;
+ adc2_data[10] : LOCATION = Pin_8;
+ adc2_data[11] : LOCATION = Pin_7;
+ adc2_data[1] : LOCATION = Pin_19;
+ adc2_data[2] : LOCATION = Pin_18;
+ adc2_data[3] : LOCATION = Pin_17;
+ adc2_data[4] : LOCATION = Pin_16;
+ adc2_data[5] : LOCATION = Pin_15;
+ adc2_data[6] : LOCATION = Pin_14;
+ adc2_data[7] : LOCATION = Pin_13;
+ adc2_data[8] : LOCATION = Pin_12;
+ adc2_data[9] : LOCATION = Pin_11;
+ adc3_data[0] : LOCATION = Pin_200;
+ adc3_data[10] : LOCATION = Pin_184;
+ adc3_data[11] : LOCATION = Pin_183;
+ adc3_data[1] : LOCATION = Pin_197;
+ adc3_data[2] : LOCATION = Pin_196;
+ adc3_data[3] : LOCATION = Pin_195;
+ adc3_data[4] : LOCATION = Pin_194;
+ adc3_data[5] : LOCATION = Pin_193;
+ adc3_data[6] : LOCATION = Pin_188;
+ adc3_data[7] : LOCATION = Pin_187;
+ adc3_data[8] : LOCATION = Pin_186;
+ adc3_data[9] : LOCATION = Pin_185;
+ adc4_data[0] : LOCATION = Pin_222;
+ adc4_data[10] : LOCATION = Pin_203;
+ adc4_data[11] : LOCATION = Pin_202;
+ adc4_data[1] : LOCATION = Pin_219;
+ adc4_data[2] : LOCATION = Pin_217;
+ adc4_data[3] : LOCATION = Pin_216;
+ adc4_data[4] : LOCATION = Pin_215;
+ adc4_data[5] : LOCATION = Pin_214;
+ adc4_data[6] : LOCATION = Pin_213;
+ adc4_data[7] : LOCATION = Pin_208;
+ adc4_data[8] : LOCATION = Pin_207;
+ adc4_data[9] : LOCATION = Pin_206;
+ adc_oeb[0] : LOCATION = Pin_228;
+ adc_oeb[1] : LOCATION = Pin_21;
+ adc_oeb[2] : LOCATION = Pin_181;
+ adc_oeb[3] : LOCATION = Pin_218;
+ adc_otr[0] : LOCATION = Pin_233;
+ adc_otr[1] : LOCATION = Pin_6;
+ adc_otr[2] : LOCATION = Pin_182;
+ adc_otr[3] : LOCATION = Pin_201;
+ adclk0 : LOCATION = Pin_224;
+ adclk1 : LOCATION = Pin_226;
+ clk0 : LOCATION = Pin_28;
+ clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk0 : IO_STANDARD = LVTTL;
+ clk1 : LOCATION = Pin_29;
+ clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk1 : IO_STANDARD = LVTTL;
+ clk3 : LOCATION = Pin_152;
+ clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk3 : IO_STANDARD = LVTTL;
+ clk_120mhz : LOCATION = Pin_153;
+ clk_120mhz : IO_STANDARD = LVTTL;
+ clk_out : LOCATION = Pin_63;
+ clk_out : IO_STANDARD = LVTTL;
+ dac1_data[0] : LOCATION = Pin_165;
+ dac1_data[10] : LOCATION = Pin_177;
+ dac1_data[11] : LOCATION = Pin_178;
+ dac1_data[12] : LOCATION = Pin_179;
+ dac1_data[13] : LOCATION = Pin_180;
+ dac1_data[1] : LOCATION = Pin_166;
+ dac1_data[2] : LOCATION = Pin_167;
+ dac1_data[3] : LOCATION = Pin_168;
+ dac1_data[4] : LOCATION = Pin_169;
+ dac1_data[5] : LOCATION = Pin_170;
+ dac1_data[6] : LOCATION = Pin_173;
+ dac1_data[7] : LOCATION = Pin_174;
+ dac1_data[8] : LOCATION = Pin_175;
+ dac1_data[9] : LOCATION = Pin_176;
+ dac2_data[0] : LOCATION = Pin_159;
+ dac2_data[10] : LOCATION = Pin_163;
+ dac2_data[11] : LOCATION = Pin_139;
+ dac2_data[12] : LOCATION = Pin_164;
+ dac2_data[13] : LOCATION = Pin_138;
+ dac2_data[1] : LOCATION = Pin_158;
+ dac2_data[2] : LOCATION = Pin_160;
+ dac2_data[3] : LOCATION = Pin_156;
+ dac2_data[4] : LOCATION = Pin_161;
+ dac2_data[5] : LOCATION = Pin_144;
+ dac2_data[6] : LOCATION = Pin_162;
+ dac2_data[7] : LOCATION = Pin_141;
+ dac2_data[8] : LOCATION = Pin_143;
+ dac2_data[9] : LOCATION = Pin_140;
+ dac3_data[0] : LOCATION = Pin_122;
+ dac3_data[10] : LOCATION = Pin_134;
+ dac3_data[11] : LOCATION = Pin_135;
+ dac3_data[12] : LOCATION = Pin_136;
+ dac3_data[13] : LOCATION = Pin_137;
+ dac3_data[1] : LOCATION = Pin_123;
+ dac3_data[2] : LOCATION = Pin_124;
+ dac3_data[3] : LOCATION = Pin_125;
+ dac3_data[4] : LOCATION = Pin_126;
+ dac3_data[5] : LOCATION = Pin_127;
+ dac3_data[6] : LOCATION = Pin_128;
+ dac3_data[7] : LOCATION = Pin_131;
+ dac3_data[8] : LOCATION = Pin_132;
+ dac3_data[9] : LOCATION = Pin_133;
+ dac4_data[0] : LOCATION = Pin_104;
+ dac4_data[10] : LOCATION = Pin_118;
+ dac4_data[11] : LOCATION = Pin_119;
+ dac4_data[12] : LOCATION = Pin_120;
+ dac4_data[13] : LOCATION = Pin_121;
+ dac4_data[1] : LOCATION = Pin_105;
+ dac4_data[2] : LOCATION = Pin_106;
+ dac4_data[3] : LOCATION = Pin_107;
+ dac4_data[4] : LOCATION = Pin_108;
+ dac4_data[5] : LOCATION = Pin_113;
+ dac4_data[6] : LOCATION = Pin_114;
+ dac4_data[7] : LOCATION = Pin_115;
+ dac4_data[8] : LOCATION = Pin_116;
+ dac4_data[9] : LOCATION = Pin_117;
+ enable_rx : LOCATION = Pin_88;
+ enable_tx : LOCATION = Pin_93;
+ gndbus[0] : LOCATION = Pin_223;
+ gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[0] : IO_STANDARD = LVTTL;
+ gndbus[1] : LOCATION = Pin_225;
+ gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[1] : IO_STANDARD = LVTTL;
+ gndbus[2] : LOCATION = Pin_227;
+ gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[2] : IO_STANDARD = LVTTL;
+ gndbus[3] : LOCATION = Pin_62;
+ gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[3] : IO_STANDARD = LVTTL;
+ gndbus[4] : LOCATION = Pin_64;
+ gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[4] : IO_STANDARD = LVTTL;
+ misc_pins[0] : LOCATION = Pin_87;
+ misc_pins[0] : IO_STANDARD = LVTTL;
+ misc_pins[10] : LOCATION = Pin_76;
+ misc_pins[10] : IO_STANDARD = LVTTL;
+ misc_pins[11] : LOCATION = Pin_74;
+ misc_pins[11] : IO_STANDARD = LVTTL;
+ misc_pins[1] : LOCATION = Pin_86;
+ misc_pins[1] : IO_STANDARD = LVTTL;
+ misc_pins[2] : LOCATION = Pin_85;
+ misc_pins[2] : IO_STANDARD = LVTTL;
+ misc_pins[3] : LOCATION = Pin_84;
+ misc_pins[3] : IO_STANDARD = LVTTL;
+ misc_pins[4] : LOCATION = Pin_83;
+ misc_pins[4] : IO_STANDARD = LVTTL;
+ misc_pins[5] : LOCATION = Pin_82;
+ misc_pins[5] : IO_STANDARD = LVTTL;
+ misc_pins[6] : LOCATION = Pin_79;
+ misc_pins[6] : IO_STANDARD = LVTTL;
+ misc_pins[7] : LOCATION = Pin_78;
+ misc_pins[7] : IO_STANDARD = LVTTL;
+ misc_pins[8] : LOCATION = Pin_77;
+ misc_pins[8] : IO_STANDARD = LVTTL;
+ misc_pins[9] : LOCATION = Pin_75;
+ misc_pins[9] : IO_STANDARD = LVTTL;
+ reset : LOCATION = Pin_94;
+ usbclk : LOCATION = Pin_55;
+ usbctl[0] : LOCATION = Pin_56;
+ usbctl[1] : LOCATION = Pin_54;
+ usbctl[2] : LOCATION = Pin_53;
+ usbctl[3] : LOCATION = Pin_58;
+ usbctl[4] : LOCATION = Pin_57;
+ usbctl[5] : LOCATION = Pin_44;
+ usbdata[0] : LOCATION = Pin_73;
+ usbdata[10] : LOCATION = Pin_41;
+ usbdata[11] : LOCATION = Pin_39;
+ usbdata[12] : LOCATION = Pin_38;
+ usbdata[12] : IO_STANDARD = LVTTL;
+ usbdata[13] : LOCATION = Pin_37;
+ usbdata[14] : LOCATION = Pin_24;
+ usbdata[15] : LOCATION = Pin_23;
+ usbdata[1] : LOCATION = Pin_68;
+ usbdata[2] : LOCATION = Pin_67;
+ usbdata[3] : LOCATION = Pin_66;
+ usbdata[4] : LOCATION = Pin_65;
+ usbdata[5] : LOCATION = Pin_61;
+ usbdata[6] : LOCATION = Pin_60;
+ usbdata[7] : LOCATION = Pin_59;
+ usbdata[8] : LOCATION = Pin_43;
+ usbdata[9] : LOCATION = Pin_42;
+ usbrdy[0] : LOCATION = Pin_45;
+ usbrdy[1] : LOCATION = Pin_46;
+ usbrdy[2] : LOCATION = Pin_47;
+ usbrdy[3] : LOCATION = Pin_48;
+ usbrdy[4] : LOCATION = Pin_49;
+ usbrdy[5] : LOCATION = Pin_50;
+ clear_status : LOCATION = Pin_99;
+}
diff --git a/toplevel/usrp_multi/usrp_multi.esf b/toplevel/usrp_multi/usrp_multi.esf
new file mode 100644
index 000000000..df45f676b
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.esf
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+ ESTIMATE_POWER_CONSUMPTION = OFF;
+ GLITCH_INTERVAL = 1NS;
+ GLITCH_DETECTION = OFF;
+ SIMULATION_COVERAGE = ON;
+ CHECK_OUTPUTS = OFF;
+ SETUP_HOLD_DETECTION = OFF;
+ POWER_ESTIMATION_START_TIME = "0 NS";
+ ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+ SIMULATION_MODE = TIMING;
+ START_TIME = 0NS;
+ USE_COMPILER_SETTINGS = usrp_multi;
+}
diff --git a/toplevel/usrp_multi/usrp_multi.psf b/toplevel/usrp_multi/usrp_multi.psf
new file mode 100644
index 000000000..68c2d12f9
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.psf
@@ -0,0 +1,312 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+ HCPY_ALOAD_SIGNALS = OFF;
+ HCPY_VREF_PINS = OFF;
+ HCPY_CAT = OFF;
+ HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+ ACLK_RULE_IMSZER_ADOMAIN = OFF;
+ ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+ ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+ ACLK_CAT = OFF;
+ SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+ SIGNALRACE_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+ NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+ NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+ NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+ NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+ NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+ NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+ NONSYNCHSTRUCT_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+ TIMING_RULE_COIN_CLKEDGE = OFF;
+ TIMING_RULE_SHIFT_REG = OFF;
+ TIMING_RULE_HIGH_FANOUTS = OFF;
+ TIMING_CAT = OFF;
+ RESET_RULE_ALL = OFF;
+ RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_REG_ASNYCH = OFF;
+ RESET_RULE_COMB_ASYNCH_RESET = OFF;
+ RESET_RULE_IMSYNCH_EXRESET = OFF;
+ RESET_RULE_UNSYNCH_EXRESET = OFF;
+ RESET_RULE_INPINS_RESETNET = OFF;
+ RESET_CAT = OFF;
+ CLK_RULE_ALL = OFF;
+ CLK_RULE_MIX_EDGES = OFF;
+ CLK_RULE_CLKNET_CLKSPINES = OFF;
+ CLK_RULE_INPINS_CLKNET = OFF;
+ CLK_RULE_GATING_SCHEME = OFF;
+ CLK_RULE_INV_CLOCK = OFF;
+ CLK_RULE_COMB_CLOCK = OFF;
+ CLK_CAT = OFF;
+ HCPY_EXCEED_USER_IO_USAGE = OFF;
+ HCPY_EXCEED_RAM_USAGE = OFF;
+ NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+ SIGNALRACE_RULE_TRISTATE = OFF;
+ ASSG_RULE_MISSING_TIMING = OFF;
+ ASSG_RULE_MISSING_FMAX = OFF;
+ ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+ AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+ AUTO_DSP_RECOGNITION = ON;
+ AUTO_RAM_RECOGNITION = ON;
+ REMOVE_DUPLICATE_LOGIC = ON;
+ AUTO_TURBO_BIT = ON;
+ AUTO_MERGE_PLLS = ON;
+ AUTO_OPEN_DRAIN_PINS = ON;
+ AUTO_PARALLEL_EXPANDERS = ON;
+ AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
+ AUTO_FAST_OUTPUT_REGISTERS = OFF;
+ AUTO_FAST_INPUT_REGISTERS = OFF;
+ AUTO_CASCADE_CHAINS = ON;
+ AUTO_CARRY_CHAINS = ON;
+ AUTO_DELAY_CHAINS = ON;
+ MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
+ PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
+ CASCADE_CHAIN_LENGTH = 2;
+ STRATIX_CARRY_CHAIN_LENGTH = 70;
+ MERCURY_CARRY_CHAIN_LENGTH = 48;
+ FLEX10K_CARRY_CHAIN_LENGTH = 32;
+ FLEX6K_CARRY_CHAIN_LENGTH = 32;
+ CARRY_CHAIN_LENGTH = 48;
+ CARRY_OUT_PINS_LCELL_INSERT = ON;
+ NORMAL_LCELL_INSERT = ON;
+ AUTO_LCELL_INSERTION = ON;
+ ALLOW_XOR_GATE_USAGE = ON;
+ AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
+ AUTO_PACKED_REGISTERS = OFF;
+ AUTO_PACKED_REG_CYCLONE = NORMAL;
+ FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
+ MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
+ APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
+ MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
+ STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
+ CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX10K_TECHNOLOGY_MAPPER = LUT;
+ FLEX6K_TECHNOLOGY_MAPPER = LUT;
+ MERCURY_TECHNOLOGY_MAPPER = LUT;
+ APEX20K_TECHNOLOGY_MAPPER = LUT;
+ MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
+ STRATIX_TECHNOLOGY_MAPPER = LUT;
+ AUTO_IMPLEMENT_IN_ROM = OFF;
+ AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+ AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+ AUTO_GLOBAL_OE = ON;
+ AUTO_GLOBAL_CLOCK = ON;
+ USE_LPM_FOR_AHDL_OPERATORS = ON;
+ LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+ ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+ WEAK_PULL_UP_RESISTOR = OFF;
+ TURBO_BIT = ON;
+ MAX7000_IGNORE_SOFT_BUFFERS = OFF;
+ IGNORE_SOFT_BUFFERS = ON;
+ MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
+ IGNORE_LCELL_BUFFERS = OFF;
+ IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+ IGNORE_GLOBAL_BUFFERS = OFF;
+ IGNORE_CASCADE_BUFFERS = OFF;
+ IGNORE_CARRY_BUFFERS = OFF;
+ REMOVE_DUPLICATE_REGISTERS = ON;
+ REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+ ALLOW_POWER_UP_DONT_CARE = ON;
+ PCI_IO = OFF;
+ NOT_GATE_PUSH_BACK = ON;
+ SLOW_SLEW_RATE = OFF;
+ DSP_BLOCK_BALANCING = AUTO;
+ STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+ HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ RUN_ALL_TIMING_ANALYSES = ON;
+ IGNORE_CLOCK_SETTINGS = OFF;
+ DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+ CUT_OFF_IO_PIN_FEEDBACK = ON;
+ CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+ CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+ CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+ DO_MIN_ANALYSIS = ON;
+ DO_MIN_TIMING = OFF;
+ NUMBER_OF_PATHS_TO_REPORT = 200;
+ NUMBER_OF_DESTINATION_TO_REPORT = 10;
+ NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+ MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+ VERILOG_INPUT_VERSION = VERILOG_2001;
+ ENABLE_IP_DEBUG = OFF;
+ VHDL_INPUT_VERSION = VHDL93;
+ VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(usrp_multi)
+{
+ ORIGINAL_QUARTUS_VERSION = 3.0;
+ PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003";
+ LAST_QUARTUS_VERSION = 3.0;
+ SHOW_REGISTRATION_MESSAGE = ON;
+ USER_LIBRARIES = "e:\usrp\fpga\megacells";
+}
+THIRD_PARTY_EDA_TOOLS(usrp_multi)
+{
+ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+ EDA_SIMULATION_TOOL = "<NONE>";
+ EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+ EDA_BOARD_DESIGN_TOOL = "<NONE>";
+ EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+ EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+ EDA_INPUT_GND_NAME = GND;
+ EDA_INPUT_VCC_NAME = VCC;
+ EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_INPUT_DATA_FORMAT = EDIF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ RESYNTHESIS_RETIMING = FULL;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
+CLOCK(clk_120mhz)
+{
+ FMAX_REQUIREMENT = "120.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(usbclk)
+{
+ FMAX_REQUIREMENT = "48.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(SCLK)
+{
+ FMAX_REQUIREMENT = "1.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk0)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk1)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
diff --git a/toplevel/usrp_multi/usrp_multi.qpf b/toplevel/usrp_multi/usrp_multi.qpf
new file mode 100644
index 000000000..1524de1bb
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.qpf
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.0"
+DATE = "17:10:11 December 20, 2004"
+
+
+# Active Revisions
+
+PROJECT_REVISION = "usrp_multi"
diff --git a/toplevel/usrp_multi/usrp_multi.qsf b/toplevel/usrp_multi/usrp_multi.qsf
new file mode 100644
index 000000000..e45c683af
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.qsf
@@ -0,0 +1,408 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# usrp_multi_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
+
+# Pin & Location Assignments
+# ==========================
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
+set_location_assignment PIN_29 -to SCLK
+set_location_assignment PIN_117 -to SDI
+set_location_assignment PIN_28 -to usbclk
+set_location_assignment PIN_107 -to usbctl[0]
+set_location_assignment PIN_106 -to usbctl[1]
+set_location_assignment PIN_105 -to usbctl[2]
+set_location_assignment PIN_100 -to usbdata[0]
+set_location_assignment PIN_84 -to usbdata[10]
+set_location_assignment PIN_83 -to usbdata[11]
+set_location_assignment PIN_82 -to usbdata[12]
+set_location_assignment PIN_79 -to usbdata[13]
+set_location_assignment PIN_78 -to usbdata[14]
+set_location_assignment PIN_77 -to usbdata[15]
+set_location_assignment PIN_99 -to usbdata[1]
+set_location_assignment PIN_98 -to usbdata[2]
+set_location_assignment PIN_95 -to usbdata[3]
+set_location_assignment PIN_94 -to usbdata[4]
+set_location_assignment PIN_93 -to usbdata[5]
+set_location_assignment PIN_88 -to usbdata[6]
+set_location_assignment PIN_87 -to usbdata[7]
+set_location_assignment PIN_86 -to usbdata[8]
+set_location_assignment PIN_85 -to usbdata[9]
+set_location_assignment PIN_104 -to usbrdy[0]
+set_location_assignment PIN_101 -to usbrdy[1]
+set_location_assignment PIN_76 -to FX2_1
+set_location_assignment PIN_75 -to FX2_2
+set_location_assignment PIN_74 -to FX2_3
+set_location_assignment PIN_116 -to io_rx_a[0]
+set_location_assignment PIN_115 -to io_rx_a[1]
+set_location_assignment PIN_114 -to io_rx_a[2]
+set_location_assignment PIN_113 -to io_rx_a[3]
+set_location_assignment PIN_108 -to io_rx_a[4]
+set_location_assignment PIN_195 -to io_rx_a[5]
+set_location_assignment PIN_196 -to io_rx_a[6]
+set_location_assignment PIN_197 -to io_rx_a[7]
+set_location_assignment PIN_200 -to io_rx_a[8]
+set_location_assignment PIN_201 -to io_rx_a[9]
+set_location_assignment PIN_202 -to io_rx_a[10]
+set_location_assignment PIN_203 -to io_rx_a[11]
+set_location_assignment PIN_206 -to io_rx_a[12]
+set_location_assignment PIN_207 -to io_rx_a[13]
+set_location_assignment PIN_208 -to io_rx_a[14]
+set_location_assignment PIN_214 -to io_rx_b[0]
+set_location_assignment PIN_215 -to io_rx_b[1]
+set_location_assignment PIN_216 -to io_rx_b[2]
+set_location_assignment PIN_217 -to io_rx_b[3]
+set_location_assignment PIN_218 -to io_rx_b[4]
+set_location_assignment PIN_219 -to io_rx_b[5]
+set_location_assignment PIN_222 -to io_rx_b[6]
+set_location_assignment PIN_223 -to io_rx_b[7]
+set_location_assignment PIN_224 -to io_rx_b[8]
+set_location_assignment PIN_225 -to io_rx_b[9]
+set_location_assignment PIN_226 -to io_rx_b[10]
+set_location_assignment PIN_227 -to io_rx_b[11]
+set_location_assignment PIN_228 -to io_rx_b[12]
+set_location_assignment PIN_233 -to io_rx_b[13]
+set_location_assignment PIN_234 -to io_rx_b[14]
+set_location_assignment PIN_175 -to io_tx_a[0]
+set_location_assignment PIN_176 -to io_tx_a[1]
+set_location_assignment PIN_177 -to io_tx_a[2]
+set_location_assignment PIN_178 -to io_tx_a[3]
+set_location_assignment PIN_179 -to io_tx_a[4]
+set_location_assignment PIN_180 -to io_tx_a[5]
+set_location_assignment PIN_181 -to io_tx_a[6]
+set_location_assignment PIN_182 -to io_tx_a[7]
+set_location_assignment PIN_183 -to io_tx_a[8]
+set_location_assignment PIN_184 -to io_tx_a[9]
+set_location_assignment PIN_185 -to io_tx_a[10]
+set_location_assignment PIN_186 -to io_tx_a[11]
+set_location_assignment PIN_187 -to io_tx_a[12]
+set_location_assignment PIN_188 -to io_tx_a[13]
+set_location_assignment PIN_193 -to io_tx_a[14]
+set_location_assignment PIN_73 -to io_tx_b[0]
+set_location_assignment PIN_68 -to io_tx_b[1]
+set_location_assignment PIN_67 -to io_tx_b[2]
+set_location_assignment PIN_66 -to io_tx_b[3]
+set_location_assignment PIN_65 -to io_tx_b[4]
+set_location_assignment PIN_64 -to io_tx_b[5]
+set_location_assignment PIN_63 -to io_tx_b[6]
+set_location_assignment PIN_62 -to io_tx_b[7]
+set_location_assignment PIN_61 -to io_tx_b[8]
+set_location_assignment PIN_60 -to io_tx_b[9]
+set_location_assignment PIN_59 -to io_tx_b[10]
+set_location_assignment PIN_58 -to io_tx_b[11]
+set_location_assignment PIN_57 -to io_tx_b[12]
+set_location_assignment PIN_56 -to io_tx_b[13]
+set_location_assignment PIN_55 -to io_tx_b[14]
+set_location_assignment PIN_152 -to master_clk
+set_location_assignment PIN_144 -to rx_a_a[0]
+set_location_assignment PIN_143 -to rx_a_a[1]
+set_location_assignment PIN_141 -to rx_a_a[2]
+set_location_assignment PIN_140 -to rx_a_a[3]
+set_location_assignment PIN_139 -to rx_a_a[4]
+set_location_assignment PIN_138 -to rx_a_a[5]
+set_location_assignment PIN_137 -to rx_a_a[6]
+set_location_assignment PIN_136 -to rx_a_a[7]
+set_location_assignment PIN_135 -to rx_a_a[8]
+set_location_assignment PIN_134 -to rx_a_a[9]
+set_location_assignment PIN_133 -to rx_a_a[10]
+set_location_assignment PIN_132 -to rx_a_a[11]
+set_location_assignment PIN_23 -to rx_a_b[0]
+set_location_assignment PIN_21 -to rx_a_b[1]
+set_location_assignment PIN_20 -to rx_a_b[2]
+set_location_assignment PIN_19 -to rx_a_b[3]
+set_location_assignment PIN_18 -to rx_a_b[4]
+set_location_assignment PIN_17 -to rx_a_b[5]
+set_location_assignment PIN_16 -to rx_a_b[6]
+set_location_assignment PIN_15 -to rx_a_b[7]
+set_location_assignment PIN_14 -to rx_a_b[8]
+set_location_assignment PIN_13 -to rx_a_b[9]
+set_location_assignment PIN_12 -to rx_a_b[10]
+set_location_assignment PIN_11 -to rx_a_b[11]
+set_location_assignment PIN_131 -to rx_b_a[0]
+set_location_assignment PIN_128 -to rx_b_a[1]
+set_location_assignment PIN_127 -to rx_b_a[2]
+set_location_assignment PIN_126 -to rx_b_a[3]
+set_location_assignment PIN_125 -to rx_b_a[4]
+set_location_assignment PIN_124 -to rx_b_a[5]
+set_location_assignment PIN_123 -to rx_b_a[6]
+set_location_assignment PIN_122 -to rx_b_a[7]
+set_location_assignment PIN_121 -to rx_b_a[8]
+set_location_assignment PIN_120 -to rx_b_a[9]
+set_location_assignment PIN_119 -to rx_b_a[10]
+set_location_assignment PIN_118 -to rx_b_a[11]
+set_location_assignment PIN_8 -to rx_b_b[0]
+set_location_assignment PIN_7 -to rx_b_b[1]
+set_location_assignment PIN_6 -to rx_b_b[2]
+set_location_assignment PIN_5 -to rx_b_b[3]
+set_location_assignment PIN_4 -to rx_b_b[4]
+set_location_assignment PIN_3 -to rx_b_b[5]
+set_location_assignment PIN_2 -to rx_b_b[6]
+set_location_assignment PIN_240 -to rx_b_b[7]
+set_location_assignment PIN_239 -to rx_b_b[8]
+set_location_assignment PIN_238 -to rx_b_b[9]
+set_location_assignment PIN_237 -to rx_b_b[10]
+set_location_assignment PIN_236 -to rx_b_b[11]
+set_location_assignment PIN_156 -to SDO
+set_location_assignment PIN_153 -to SEN_FPGA
+set_location_assignment PIN_159 -to tx_a[0]
+set_location_assignment PIN_160 -to tx_a[1]
+set_location_assignment PIN_161 -to tx_a[2]
+set_location_assignment PIN_162 -to tx_a[3]
+set_location_assignment PIN_163 -to tx_a[4]
+set_location_assignment PIN_164 -to tx_a[5]
+set_location_assignment PIN_165 -to tx_a[6]
+set_location_assignment PIN_166 -to tx_a[7]
+set_location_assignment PIN_167 -to tx_a[8]
+set_location_assignment PIN_168 -to tx_a[9]
+set_location_assignment PIN_169 -to tx_a[10]
+set_location_assignment PIN_170 -to tx_a[11]
+set_location_assignment PIN_173 -to tx_a[12]
+set_location_assignment PIN_174 -to tx_a[13]
+set_location_assignment PIN_38 -to tx_b[0]
+set_location_assignment PIN_39 -to tx_b[1]
+set_location_assignment PIN_41 -to tx_b[2]
+set_location_assignment PIN_42 -to tx_b[3]
+set_location_assignment PIN_43 -to tx_b[4]
+set_location_assignment PIN_44 -to tx_b[5]
+set_location_assignment PIN_45 -to tx_b[6]
+set_location_assignment PIN_46 -to tx_b[7]
+set_location_assignment PIN_47 -to tx_b[8]
+set_location_assignment PIN_48 -to tx_b[9]
+set_location_assignment PIN_49 -to tx_b[10]
+set_location_assignment PIN_50 -to tx_b[11]
+set_location_assignment PIN_53 -to tx_b[12]
+set_location_assignment PIN_54 -to tx_b[13]
+set_location_assignment PIN_158 -to TXSYNC_A
+set_location_assignment PIN_37 -to TXSYNC_B
+set_location_assignment PIN_235 -to io_rx_b[15]
+set_location_assignment PIN_24 -to io_tx_b[15]
+set_location_assignment PIN_213 -to io_rx_a[15]
+set_location_assignment PIN_194 -to io_tx_a[15]
+set_location_assignment PIN_1 -to MYSTERY_SIGNAL
+
+# Timing Assignments
+# ==================
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells"
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name MAX_SCC_SIZE 50
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name START_TIME "0 ns"
+set_global_assignment -name GLITCH_INTERVAL "1 ns"
+
+# Design Assistant Assignments
+# ============================
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT OFF
+set_global_assignment -name HCPY_VREF_PINS OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
+set_global_assignment -name ENABLE_SIGNALTAP Off
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# -----------------
+# start CLOCK(SCLK)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+ set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
+
+# end CLOCK(SCLK)
+# ---------------
+
+# -----------------------
+# start CLOCK(master_clk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+ set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
+
+# end CLOCK(master_clk)
+# ---------------------
+
+# -------------------
+# start CLOCK(usbclk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+ set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
+
+# end CLOCK(usbclk)
+# -----------------
+
+# ----------------------
+# start ENTITY(usrp_multi)
+
+ # Timing Assignments
+ # ==================
+ set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+ set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+
+# end ENTITY(usrp_multi)
+# --------------------
+
+
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE usrp_multi.vh
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
+set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE usrp_multi.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file
diff --git a/toplevel/usrp_multi/usrp_multi.v b/toplevel/usrp_multi/usrp_multi.v
new file mode 100644
index 000000000..b27d3d3a6
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.v
@@ -0,0 +1,379 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003,2004,2005,2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Top level module for a full setup with DUCs and DDCs
+
+// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
+// for debugging info. NB, This can kill the m'board and/or d'board if you
+// have anything except basic d'boards installed.
+
+// Uncomment the following to include optional circuitry
+
+`include "usrp_multi.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+
+module usrp_multi
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ input wire [11:0] rx_a_b,
+ input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ output wire TXSYNC_B,
+
+ // USB interface
+ input usbclk,
+ input wire [2:0] usbctl,
+ output wire [1:0] usbrdy,
+ inout [15:0] usbdata, // NB Careful, inout
+
+ // These are the general purpose i/o's that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ inout wire [15:0] io_rx_b
+ );
+ wire [15:0] debugdata,debugctrl;
+ assign MYSTERY_SIGNAL = 1'b0;
+
+ wire clk64,clk128;
+
+ wire WR = usbctl[0];
+ wire RD = usbctl[1];
+ wire OE = usbctl[2];
+
+ wire have_space, have_pkt_rdy;
+ assign usbrdy[0] = have_space;
+ assign usbrdy[1] = have_pkt_rdy;
+
+ wire tx_underrun, rx_overrun;
+ wire clear_status = FX2_1;
+ assign FX2_2 = rx_overrun;
+ assign FX2_3 = tx_underrun;
+
+ wire [15:0] usbdata_out;
+
+ wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
+
+ wire tx_realsignals;
+ wire [3:0] rx_numchan;
+ wire [2:0] tx_numchan;
+
+ wire [7:0] interp_rate, decim_rate;
+ wire [15:0] tx_debugbus, rx_debugbus;
+
+ wire enable_tx, enable_rx;
+ wire reset_data;
+`ifdef MULTI_ON
+ wire sync_rx;
+ assign reset_data = sync_rx;
+`else
+ assign reset_data = 1'b0;
+`endif // `ifdef MULTI_ON
+
+ wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+ wire [7:0] settings;
+
+ // Tri-state bus macro
+ bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+ assign clk64 = master_clk;
+
+ wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
+ wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+
+ // TX
+ wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
+ wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
+
+ wire strobe_interp, tx_sample_strobe;
+ wire tx_empty;
+
+ wire serial_strobe;
+ wire [6:0] serial_addr;
+ wire [31:0] serial_data;
+
+ reg [15:0] debug_counter;
+`ifdef COUNTER_32BIT_ON
+ reg [31:0] sample_counter_32bit;
+`endif // `ifdef COUNTER_32BIT_ON
+ reg [15:0] loopback_i_0,loopback_q_0;
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Transmit Side
+`ifdef TX_ON
+ assign bb_tx_i0 = ch0tx;
+ assign bb_tx_q0 = ch1tx;
+ assign bb_tx_i1 = ch2tx;
+ assign bb_tx_q1 = ch3tx;
+
+ tx_buffer tx_buffer
+ ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+ .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+ .channels({tx_numchan,1'b0}),
+ .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+ .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+ .tx_i_2(),.tx_q_2(),
+ .tx_i_3(),.tx_q_3(),
+ .txclk(clk64),.txstrobe(strobe_interp),
+ .clear_status(clear_status),
+ .tx_empty(tx_empty),
+ .debugbus(tx_debugbus) );
+
+ tx_chain tx_chain_0
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+
+ tx_chain tx_chain_1
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+
+ setting_reg #(`FR_TX_MUX)
+ sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+
+ wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+
+ wire txsync = tx_sample_strobe;
+ assign TXSYNC_A = txsync;
+ assign TXSYNC_B = txsync;
+
+ assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
+ assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
+`endif // `ifdef TX_ON
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Receive Side
+`ifdef RX_ON
+ wire rx_sample_strobe,strobe_decim,hb_strobe;
+ wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
+ bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
+
+ wire loopback = settings[0];
+ wire counter = settings[1];
+`ifdef COUNTER_32BIT_ON
+ wire counter_32bit = settings[2];
+
+ always @(posedge clk64)
+ if(rx_dsp_reset)
+ sample_counter_32bit <= #1 32'd0;
+ else if(~enable_rx | reset_data)
+ sample_counter_32bit <=#1 32'd0;
+ else if(hb_strobe)
+ sample_counter_32bit <=#1 sample_counter_32bit + 32'd1;
+`endif // `ifdef COUNTER_32BIT_ON
+
+ always @(posedge clk64)
+ if(rx_dsp_reset)
+ debug_counter <= #1 16'd0;
+ else if(~enable_rx)
+ debug_counter <= #1 16'd0;
+ else if(hb_strobe)
+ debug_counter <=#1 debug_counter + 16'd2;
+
+ always @(posedge clk64)
+ if(strobe_interp)
+ begin
+ loopback_i_0 <= #1 ch0tx;
+ loopback_q_0 <= #1 ch1tx;
+ end
+
+`ifdef COUNTER_32BIT_ON
+ assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+ assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
+ assign ch2rx = bb_rx_i1;
+ assign ch3rx = bb_rx_q1;
+ assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2;
+ assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter
+ //This means if you use 4 channels that channel 3 will be replaced by channel 0
+ // and channel 0 will output the 32 bit counter.
+ assign ch6rx = bb_rx_i3;
+ assign ch7rx = bb_rx_q3;
+`else
+ assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+ assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
+ assign ch2rx = bb_rx_i1;
+ assign ch3rx = bb_rx_q1;
+ assign ch4rx = bb_rx_i2;
+ assign ch5rx = bb_rx_q2;
+ assign ch6rx = bb_rx_i3;
+ assign ch7rx = bb_rx_q3;
+`endif // `ifdef COUNTER_32BIT_ON
+
+
+ wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
+ adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
+ .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
+ .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
+ .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
+ .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
+
+ rx_buffer rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data),
+ .reset_regs(rx_dsp_reset),
+ .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(ch0rx),.ch_1(ch1rx),
+ .ch_2(ch2rx),.ch_3(ch3rx),
+ .ch_4(ch4rx),.ch_5(ch5rx),
+ .ch_6(ch6rx),.ch_7(ch7rx),
+ .rxclk(clk64),.rxstrobe(hb_strobe),
+ .clear_status(clear_status),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .debugbus(rx_debugbus) );
+
+ `ifdef RX_EN_0
+ rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
+ ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
+ `else
+ assign bb_rx_i0=16'd0;
+ assign bb_rx_q0=16'd0;
+ `endif
+
+ `ifdef RX_EN_1
+ rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
+ ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
+ `else
+ assign bb_rx_i1=16'd0;
+ assign bb_rx_q1=16'd0;
+ `endif
+
+ `ifdef RX_EN_2
+ rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
+ ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
+ `else
+ assign bb_rx_i2=16'd0;
+ assign bb_rx_q2=16'd0;
+ `endif
+
+ `ifdef RX_EN_3
+ rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
+ ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
+ assign bb_rx_i3=16'd0;
+ assign bb_rx_q3=16'd0;
+ `endif
+
+`endif // `ifdef RX_ON
+
+ ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Control Functions
+
+ wire [31:0] capabilities;
+ assign capabilities[7] = `TX_CAP_HB;
+ assign capabilities[6:4] = `TX_CAP_NCHAN;
+ assign capabilities[3] = `RX_CAP_HB;
+ assign capabilities[2:0] = `RX_CAP_NCHAN;
+
+
+ serial_io serial_io
+ ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+ .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) );
+
+ wire [15:0] reg_0,reg_1,reg_2,reg_3;
+
+`ifdef MULTI_ON
+
+ master_control_multi master_control
+ ( .master_clk(clk64),.usbclk(usbclk),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .sync_rx(sync_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+ .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+`else //`ifdef MULTI_ON
+
+ master_control master_control
+ ( .master_clk(clk64),.usbclk(usbclk),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+ .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+`endif //`ifdef MULTI_ON
+
+ io_pins io_pins
+ (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Misc Settings
+ setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
+
+endmodule // usrp_multi
diff --git a/toplevel/usrp_multi/usrp_multi.vh b/toplevel/usrp_multi/usrp_multi.vh
new file mode 100644
index 000000000..2904a9352
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi.vh
@@ -0,0 +1,141 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// ====================================================================
+// User control over what parts get included
+//
+// >>>> EDIT ONLY THIS SECTION <<<<
+// Uncomment only ONE configuration
+// ====================================================================
+
+// ==== Multi usrp configurations ====
+// Uncomment this for multi with 2 rx channels (w/ halfband) & 2 transmit channels
+`include "usrp_multi_config_2rxhb_2tx.vh"
+
+// Uncomment this for multi with 4 rx channels (w/o halfband) & 0 transmit channels
+//`include "usrp_multi_config_4rx_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/ halfband) & 0 transmit channels
+//`include "usrp_multi_config_2rxhb_0tx.vh"
+
+// Uncomment this for multi with 2 rx channels (w/o halfband) & 0 transmit channels
+//`include "usrp_multi_config_2rx_0tx.vh"
+
+// ==== Standard configurations (no multi support) ====
+// Uncomment this for standard with 2 rx channels (w/ halfband) & 2 transmit channels
+// `include "../usrp_std/usrp_std_config_2rxhb_2tx.vh"
+
+// Uncomment this for standard with 4 rx channels (w/o halfband) & 0 transmit channels
+//`include "../usrp_std/usrp_std_config_4rx_0tx.vh"
+
+// Add other "known to fit" configurations here...
+
+// ====================================================================
+//
+// >>>> DO NOT EDIT BELOW HERE <<<<
+//
+// [The stuff from here down is derived from the stuff included above]
+//
+// N.B., *all* the remainder of the code should be conditionalized
+// only in terms of:
+//
+// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB,
+// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB,
+// RX_NCO_ON, RX_CIC_ON
+// ====================================================================
+`ifdef MULTI_ON
+ `define COUNTER_32BIT_ON
+`endif
+
+`ifdef TX_ON
+
+ `ifdef TX_SINGLE
+ `define TX_EN_0
+ `define TX_CAP_NCHAN 3'd1
+ `endif
+
+ `ifdef TX_DUAL
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_CAP_NCHAN 3'd2
+ `endif
+
+ `ifdef TX_QUAD
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_EN_2
+ `define TX_EN_3
+ `define TX_CAP_NCHAN 3'd4
+ `endif
+
+ `ifdef TX_HB_ON
+ `define TX_CAP_HB 1
+ `else
+ `define TX_CAP_HB 0
+ `endif
+
+`else // !ifdef TX_ON
+
+ `define TX_CAP_NCHAN 3'd0
+ `define TX_CAP_HB 0
+
+`endif // !ifdef TX_ON
+
+// --------------------------------------------------------------------
+
+`ifdef RX_ON
+
+ `ifdef RX_SINGLE
+ `define RX_EN_0
+ `define RX_CAP_NCHAN 3'd1
+ `endif
+
+ `ifdef RX_DUAL
+ `define RX_EN_0
+ `define RX_EN_1
+ `ifdef MULTI_ON
+ `define RX_CAP_NCHAN 3'd4
+ `else
+ `define RX_CAP_NCHAN 3'd2
+ `endif
+ `endif
+
+ `ifdef RX_QUAD
+ `define RX_EN_0
+ `define RX_EN_1
+ `define RX_EN_2
+ `define RX_EN_3
+ `define RX_CAP_NCHAN 3'd4
+ `endif
+
+ `ifdef RX_HB_ON
+ `define RX_CAP_HB 1
+ `else
+ `define RX_CAP_HB 0
+ `endif
+
+`else // !ifdef RX_ON
+
+ `define RX_CAP_NCHAN 3'd0
+ `define RX_CAP_HB 0
+
+`endif // !ifdef RX_ON
diff --git a/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh
new file mode 100644
index 000000000..26a41e4d0
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh
@@ -0,0 +1,62 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+`define MULTI_ON
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+// `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+//`define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+`define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+//`define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh
new file mode 100644
index 000000000..0673d9600
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh
@@ -0,0 +1,62 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+`define MULTI_ON
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+// `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+//`define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+ `define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+ `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
diff --git a/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh
new file mode 100644
index 000000000..80c7fbdcb
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh
@@ -0,0 +1,62 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+`define MULTI_ON
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+ `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+ `define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+ `define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+ `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
diff --git a/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh
new file mode 100644
index 000000000..36176be4a
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh
@@ -0,0 +1,62 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+`define MULTI_ON
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+// `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+//`define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+//`define RX_DUAL
+ `define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+//`define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
diff --git a/toplevel/usrp_multi/usrp_std.vh b/toplevel/usrp_multi/usrp_std.vh
new file mode 100644
index 000000000..189cf14b8
--- /dev/null
+++ b/toplevel/usrp_multi/usrp_std.vh
@@ -0,0 +1,29 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Martin Dudok van Heel
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// ====================================================================
+// Do not remove or edit this file.
+// This is a redirect to usrp_multi.vh
+// This is needed because some common source files have a
+// hardcoded `include "usrp_std.vh"
+// ====================================================================
+
+`include "usrp_multi.vh"
diff --git a/toplevel/usrp_std/usrp_std.csf b/toplevel/usrp_std/usrp_std.csf
new file mode 100644
index 000000000..627197caf
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.csf
@@ -0,0 +1,444 @@
+COMPILER_SETTINGS
+{
+ IO_PLACEMENT_OPTIMIZATION = OFF;
+ ENABLE_DRC_SETTINGS = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
+ PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
+ PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ TRUE_WYSIWYG_FLOW = OFF;
+ SEED = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = "NORMAL COMPILATION";
+ OPTIMIZE_HOLD_TIMING = OFF;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = OFF;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |usrp_std;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
+ FIT_ONLY_ONE_ATTEMPT = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = SLD_HUB_INST;
+ HUB_ENTITY_NAME = SLD_HUB;
+}
+SIGNALTAP_LOGIC_ANALYZER_SETTINGS
+{
+ ENABLE_SIGNALTAP = Off;
+ AUTO_ENABLE_SMART_COMPILE = On;
+}
+CHIP(usrp_std)
+{
+ DEVICE = EP1C12Q240C8;
+ DEVICE_FILTER_PACKAGE = "ANY QFP";
+ DEVICE_FILTER_PIN_COUNT = 240;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ MAX7000S_JTAG_USER_CODE = FFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = OFF;
+ APEX20K_CONFIGURATION_DEVICE = AUTO;
+ MERCURY_CONFIGURATION_DEVICE = AUTO;
+ FLEX6K_CONFIGURATION_DEVICE = AUTO;
+ FLEX10K_CONFIGURATION_DEVICE = AUTO;
+ EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_CONFIGURATION_DEVICE = AUTO;
+ CYCLONE_CONFIGURATION_DEVICE = AUTO;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = ON;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED";
+ STRATIX_DEVICE_IO_STANDARD = LVTTL;
+ CLOCK_SOURCE = INTERNAL;
+ CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
+ CONFIGURATION_CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
+ SCLK : LOCATION = Pin_101;
+ SDI : LOCATION = Pin_100;
+ SEN : LOCATION = Pin_98;
+ SLD : LOCATION = Pin_95;
+ adc1_data[0] : LOCATION = Pin_5;
+ adc1_data[10] : LOCATION = Pin_235;
+ adc1_data[11] : LOCATION = Pin_234;
+ adc1_data[1] : LOCATION = Pin_4;
+ adc1_data[2] : LOCATION = Pin_3;
+ adc1_data[3] : LOCATION = Pin_2;
+ adc1_data[4] : LOCATION = Pin_1;
+ adc1_data[4] : IO_STANDARD = LVTTL;
+ adc1_data[5] : LOCATION = Pin_240;
+ adc1_data[6] : LOCATION = Pin_239;
+ adc1_data[7] : LOCATION = Pin_238;
+ adc1_data[8] : LOCATION = Pin_237;
+ adc1_data[9] : LOCATION = Pin_236;
+ adc2_data[0] : LOCATION = Pin_20;
+ adc2_data[10] : LOCATION = Pin_8;
+ adc2_data[11] : LOCATION = Pin_7;
+ adc2_data[1] : LOCATION = Pin_19;
+ adc2_data[2] : LOCATION = Pin_18;
+ adc2_data[3] : LOCATION = Pin_17;
+ adc2_data[4] : LOCATION = Pin_16;
+ adc2_data[5] : LOCATION = Pin_15;
+ adc2_data[6] : LOCATION = Pin_14;
+ adc2_data[7] : LOCATION = Pin_13;
+ adc2_data[8] : LOCATION = Pin_12;
+ adc2_data[9] : LOCATION = Pin_11;
+ adc3_data[0] : LOCATION = Pin_200;
+ adc3_data[10] : LOCATION = Pin_184;
+ adc3_data[11] : LOCATION = Pin_183;
+ adc3_data[1] : LOCATION = Pin_197;
+ adc3_data[2] : LOCATION = Pin_196;
+ adc3_data[3] : LOCATION = Pin_195;
+ adc3_data[4] : LOCATION = Pin_194;
+ adc3_data[5] : LOCATION = Pin_193;
+ adc3_data[6] : LOCATION = Pin_188;
+ adc3_data[7] : LOCATION = Pin_187;
+ adc3_data[8] : LOCATION = Pin_186;
+ adc3_data[9] : LOCATION = Pin_185;
+ adc4_data[0] : LOCATION = Pin_222;
+ adc4_data[10] : LOCATION = Pin_203;
+ adc4_data[11] : LOCATION = Pin_202;
+ adc4_data[1] : LOCATION = Pin_219;
+ adc4_data[2] : LOCATION = Pin_217;
+ adc4_data[3] : LOCATION = Pin_216;
+ adc4_data[4] : LOCATION = Pin_215;
+ adc4_data[5] : LOCATION = Pin_214;
+ adc4_data[6] : LOCATION = Pin_213;
+ adc4_data[7] : LOCATION = Pin_208;
+ adc4_data[8] : LOCATION = Pin_207;
+ adc4_data[9] : LOCATION = Pin_206;
+ adc_oeb[0] : LOCATION = Pin_228;
+ adc_oeb[1] : LOCATION = Pin_21;
+ adc_oeb[2] : LOCATION = Pin_181;
+ adc_oeb[3] : LOCATION = Pin_218;
+ adc_otr[0] : LOCATION = Pin_233;
+ adc_otr[1] : LOCATION = Pin_6;
+ adc_otr[2] : LOCATION = Pin_182;
+ adc_otr[3] : LOCATION = Pin_201;
+ adclk0 : LOCATION = Pin_224;
+ adclk1 : LOCATION = Pin_226;
+ clk0 : LOCATION = Pin_28;
+ clk0 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk0 : IO_STANDARD = LVTTL;
+ clk1 : LOCATION = Pin_29;
+ clk1 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk1 : IO_STANDARD = LVTTL;
+ clk3 : LOCATION = Pin_152;
+ clk3 : RESERVE_PIN = "AS INPUT TRI-STATED";
+ clk3 : IO_STANDARD = LVTTL;
+ clk_120mhz : LOCATION = Pin_153;
+ clk_120mhz : IO_STANDARD = LVTTL;
+ clk_out : LOCATION = Pin_63;
+ clk_out : IO_STANDARD = LVTTL;
+ dac1_data[0] : LOCATION = Pin_165;
+ dac1_data[10] : LOCATION = Pin_177;
+ dac1_data[11] : LOCATION = Pin_178;
+ dac1_data[12] : LOCATION = Pin_179;
+ dac1_data[13] : LOCATION = Pin_180;
+ dac1_data[1] : LOCATION = Pin_166;
+ dac1_data[2] : LOCATION = Pin_167;
+ dac1_data[3] : LOCATION = Pin_168;
+ dac1_data[4] : LOCATION = Pin_169;
+ dac1_data[5] : LOCATION = Pin_170;
+ dac1_data[6] : LOCATION = Pin_173;
+ dac1_data[7] : LOCATION = Pin_174;
+ dac1_data[8] : LOCATION = Pin_175;
+ dac1_data[9] : LOCATION = Pin_176;
+ dac2_data[0] : LOCATION = Pin_159;
+ dac2_data[10] : LOCATION = Pin_163;
+ dac2_data[11] : LOCATION = Pin_139;
+ dac2_data[12] : LOCATION = Pin_164;
+ dac2_data[13] : LOCATION = Pin_138;
+ dac2_data[1] : LOCATION = Pin_158;
+ dac2_data[2] : LOCATION = Pin_160;
+ dac2_data[3] : LOCATION = Pin_156;
+ dac2_data[4] : LOCATION = Pin_161;
+ dac2_data[5] : LOCATION = Pin_144;
+ dac2_data[6] : LOCATION = Pin_162;
+ dac2_data[7] : LOCATION = Pin_141;
+ dac2_data[8] : LOCATION = Pin_143;
+ dac2_data[9] : LOCATION = Pin_140;
+ dac3_data[0] : LOCATION = Pin_122;
+ dac3_data[10] : LOCATION = Pin_134;
+ dac3_data[11] : LOCATION = Pin_135;
+ dac3_data[12] : LOCATION = Pin_136;
+ dac3_data[13] : LOCATION = Pin_137;
+ dac3_data[1] : LOCATION = Pin_123;
+ dac3_data[2] : LOCATION = Pin_124;
+ dac3_data[3] : LOCATION = Pin_125;
+ dac3_data[4] : LOCATION = Pin_126;
+ dac3_data[5] : LOCATION = Pin_127;
+ dac3_data[6] : LOCATION = Pin_128;
+ dac3_data[7] : LOCATION = Pin_131;
+ dac3_data[8] : LOCATION = Pin_132;
+ dac3_data[9] : LOCATION = Pin_133;
+ dac4_data[0] : LOCATION = Pin_104;
+ dac4_data[10] : LOCATION = Pin_118;
+ dac4_data[11] : LOCATION = Pin_119;
+ dac4_data[12] : LOCATION = Pin_120;
+ dac4_data[13] : LOCATION = Pin_121;
+ dac4_data[1] : LOCATION = Pin_105;
+ dac4_data[2] : LOCATION = Pin_106;
+ dac4_data[3] : LOCATION = Pin_107;
+ dac4_data[4] : LOCATION = Pin_108;
+ dac4_data[5] : LOCATION = Pin_113;
+ dac4_data[6] : LOCATION = Pin_114;
+ dac4_data[7] : LOCATION = Pin_115;
+ dac4_data[8] : LOCATION = Pin_116;
+ dac4_data[9] : LOCATION = Pin_117;
+ enable_rx : LOCATION = Pin_88;
+ enable_tx : LOCATION = Pin_93;
+ gndbus[0] : LOCATION = Pin_223;
+ gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[0] : IO_STANDARD = LVTTL;
+ gndbus[1] : LOCATION = Pin_225;
+ gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[1] : IO_STANDARD = LVTTL;
+ gndbus[2] : LOCATION = Pin_227;
+ gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[2] : IO_STANDARD = LVTTL;
+ gndbus[3] : LOCATION = Pin_62;
+ gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[3] : IO_STANDARD = LVTTL;
+ gndbus[4] : LOCATION = Pin_64;
+ gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED";
+ gndbus[4] : IO_STANDARD = LVTTL;
+ misc_pins[0] : LOCATION = Pin_87;
+ misc_pins[0] : IO_STANDARD = LVTTL;
+ misc_pins[10] : LOCATION = Pin_76;
+ misc_pins[10] : IO_STANDARD = LVTTL;
+ misc_pins[11] : LOCATION = Pin_74;
+ misc_pins[11] : IO_STANDARD = LVTTL;
+ misc_pins[1] : LOCATION = Pin_86;
+ misc_pins[1] : IO_STANDARD = LVTTL;
+ misc_pins[2] : LOCATION = Pin_85;
+ misc_pins[2] : IO_STANDARD = LVTTL;
+ misc_pins[3] : LOCATION = Pin_84;
+ misc_pins[3] : IO_STANDARD = LVTTL;
+ misc_pins[4] : LOCATION = Pin_83;
+ misc_pins[4] : IO_STANDARD = LVTTL;
+ misc_pins[5] : LOCATION = Pin_82;
+ misc_pins[5] : IO_STANDARD = LVTTL;
+ misc_pins[6] : LOCATION = Pin_79;
+ misc_pins[6] : IO_STANDARD = LVTTL;
+ misc_pins[7] : LOCATION = Pin_78;
+ misc_pins[7] : IO_STANDARD = LVTTL;
+ misc_pins[8] : LOCATION = Pin_77;
+ misc_pins[8] : IO_STANDARD = LVTTL;
+ misc_pins[9] : LOCATION = Pin_75;
+ misc_pins[9] : IO_STANDARD = LVTTL;
+ reset : LOCATION = Pin_94;
+ usbclk : LOCATION = Pin_55;
+ usbctl[0] : LOCATION = Pin_56;
+ usbctl[1] : LOCATION = Pin_54;
+ usbctl[2] : LOCATION = Pin_53;
+ usbctl[3] : LOCATION = Pin_58;
+ usbctl[4] : LOCATION = Pin_57;
+ usbctl[5] : LOCATION = Pin_44;
+ usbdata[0] : LOCATION = Pin_73;
+ usbdata[10] : LOCATION = Pin_41;
+ usbdata[11] : LOCATION = Pin_39;
+ usbdata[12] : LOCATION = Pin_38;
+ usbdata[12] : IO_STANDARD = LVTTL;
+ usbdata[13] : LOCATION = Pin_37;
+ usbdata[14] : LOCATION = Pin_24;
+ usbdata[15] : LOCATION = Pin_23;
+ usbdata[1] : LOCATION = Pin_68;
+ usbdata[2] : LOCATION = Pin_67;
+ usbdata[3] : LOCATION = Pin_66;
+ usbdata[4] : LOCATION = Pin_65;
+ usbdata[5] : LOCATION = Pin_61;
+ usbdata[6] : LOCATION = Pin_60;
+ usbdata[7] : LOCATION = Pin_59;
+ usbdata[8] : LOCATION = Pin_43;
+ usbdata[9] : LOCATION = Pin_42;
+ usbrdy[0] : LOCATION = Pin_45;
+ usbrdy[1] : LOCATION = Pin_46;
+ usbrdy[2] : LOCATION = Pin_47;
+ usbrdy[3] : LOCATION = Pin_48;
+ usbrdy[4] : LOCATION = Pin_49;
+ usbrdy[5] : LOCATION = Pin_50;
+ clear_status : LOCATION = Pin_99;
+}
diff --git a/toplevel/usrp_std/usrp_std.esf b/toplevel/usrp_std/usrp_std.esf
new file mode 100644
index 000000000..b88c15994
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.esf
@@ -0,0 +1,14 @@
+SIMULATOR_SETTINGS
+{
+ ESTIMATE_POWER_CONSUMPTION = OFF;
+ GLITCH_INTERVAL = 1NS;
+ GLITCH_DETECTION = OFF;
+ SIMULATION_COVERAGE = ON;
+ CHECK_OUTPUTS = OFF;
+ SETUP_HOLD_DETECTION = OFF;
+ POWER_ESTIMATION_START_TIME = "0 NS";
+ ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
+ SIMULATION_MODE = TIMING;
+ START_TIME = 0NS;
+ USE_COMPILER_SETTINGS = usrp_std;
+}
diff --git a/toplevel/usrp_std/usrp_std.psf b/toplevel/usrp_std/usrp_std.psf
new file mode 100644
index 000000000..506c81b6a
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.psf
@@ -0,0 +1,312 @@
+DEFAULT_DESIGN_ASSISTANT_SETTINGS
+{
+ HCPY_ALOAD_SIGNALS = OFF;
+ HCPY_VREF_PINS = OFF;
+ HCPY_CAT = OFF;
+ HCPY_ILLEGAL_HC_DEV_PKG = OFF;
+ ACLK_RULE_IMSZER_ADOMAIN = OFF;
+ ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
+ ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
+ ACLK_CAT = OFF;
+ SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
+ SIGNALRACE_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
+ NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_DLATCH = OFF;
+ NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
+ NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
+ NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
+ NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
+ NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
+ NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
+ NONSYNCHSTRUCT_CAT = OFF;
+ NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
+ TIMING_RULE_COIN_CLKEDGE = OFF;
+ TIMING_RULE_SHIFT_REG = OFF;
+ TIMING_RULE_HIGH_FANOUTS = OFF;
+ TIMING_CAT = OFF;
+ RESET_RULE_ALL = OFF;
+ RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
+ RESET_RULE_REG_ASNYCH = OFF;
+ RESET_RULE_COMB_ASYNCH_RESET = OFF;
+ RESET_RULE_IMSYNCH_EXRESET = OFF;
+ RESET_RULE_UNSYNCH_EXRESET = OFF;
+ RESET_RULE_INPINS_RESETNET = OFF;
+ RESET_CAT = OFF;
+ CLK_RULE_ALL = OFF;
+ CLK_RULE_MIX_EDGES = OFF;
+ CLK_RULE_CLKNET_CLKSPINES = OFF;
+ CLK_RULE_INPINS_CLKNET = OFF;
+ CLK_RULE_GATING_SCHEME = OFF;
+ CLK_RULE_INV_CLOCK = OFF;
+ CLK_RULE_COMB_CLOCK = OFF;
+ CLK_CAT = OFF;
+ HCPY_EXCEED_USER_IO_USAGE = OFF;
+ HCPY_EXCEED_RAM_USAGE = OFF;
+ NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
+ SIGNALRACE_RULE_TRISTATE = OFF;
+ ASSG_RULE_MISSING_TIMING = OFF;
+ ASSG_RULE_MISSING_FMAX = OFF;
+ ASSG_CAT = OFF;
+}
+SYNTHESIS_FITTING_SETTINGS
+{
+ AUTO_SHIFT_REGISTER_RECOGNITION = ON;
+ AUTO_DSP_RECOGNITION = ON;
+ AUTO_RAM_RECOGNITION = ON;
+ REMOVE_DUPLICATE_LOGIC = ON;
+ AUTO_TURBO_BIT = ON;
+ AUTO_MERGE_PLLS = ON;
+ AUTO_OPEN_DRAIN_PINS = ON;
+ AUTO_PARALLEL_EXPANDERS = ON;
+ AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
+ AUTO_FAST_OUTPUT_REGISTERS = OFF;
+ AUTO_FAST_INPUT_REGISTERS = OFF;
+ AUTO_CASCADE_CHAINS = ON;
+ AUTO_CARRY_CHAINS = ON;
+ AUTO_DELAY_CHAINS = ON;
+ MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
+ PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
+ CASCADE_CHAIN_LENGTH = 2;
+ STRATIX_CARRY_CHAIN_LENGTH = 70;
+ MERCURY_CARRY_CHAIN_LENGTH = 48;
+ FLEX10K_CARRY_CHAIN_LENGTH = 32;
+ FLEX6K_CARRY_CHAIN_LENGTH = 32;
+ CARRY_CHAIN_LENGTH = 48;
+ CARRY_OUT_PINS_LCELL_INSERT = ON;
+ NORMAL_LCELL_INSERT = ON;
+ AUTO_LCELL_INSERTION = ON;
+ ALLOW_XOR_GATE_USAGE = ON;
+ AUTO_PACKED_REGISTERS_STRATIX = NORMAL;
+ AUTO_PACKED_REGISTERS = OFF;
+ AUTO_PACKED_REG_CYCLONE = NORMAL;
+ FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
+ MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
+ APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
+ MAX7000_OPTIMIZATION_TECHNIQUE = SPEED;
+ STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
+ CYCLONE_OPTIMIZATION_TECHNIQUE = AREA;
+ FLEX10K_TECHNOLOGY_MAPPER = LUT;
+ FLEX6K_TECHNOLOGY_MAPPER = LUT;
+ MERCURY_TECHNOLOGY_MAPPER = LUT;
+ APEX20K_TECHNOLOGY_MAPPER = LUT;
+ MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
+ STRATIX_TECHNOLOGY_MAPPER = LUT;
+ AUTO_IMPLEMENT_IN_ROM = OFF;
+ AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
+ AUTO_GLOBAL_REGISTER_CONTROLS = ON;
+ AUTO_GLOBAL_OE = ON;
+ AUTO_GLOBAL_CLOCK = ON;
+ USE_LPM_FOR_AHDL_OPERATORS = ON;
+ LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
+ ENABLE_BUS_HOLD_CIRCUITRY = OFF;
+ WEAK_PULL_UP_RESISTOR = OFF;
+ TURBO_BIT = ON;
+ MAX7000_IGNORE_SOFT_BUFFERS = OFF;
+ IGNORE_SOFT_BUFFERS = ON;
+ MAX7000_IGNORE_LCELL_BUFFERS = AUTO;
+ IGNORE_LCELL_BUFFERS = OFF;
+ IGNORE_ROW_GLOBAL_BUFFERS = OFF;
+ IGNORE_GLOBAL_BUFFERS = OFF;
+ IGNORE_CASCADE_BUFFERS = OFF;
+ IGNORE_CARRY_BUFFERS = OFF;
+ REMOVE_DUPLICATE_REGISTERS = ON;
+ REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
+ ALLOW_POWER_UP_DONT_CARE = ON;
+ PCI_IO = OFF;
+ NOT_GATE_PUSH_BACK = ON;
+ SLOW_SLEW_RATE = OFF;
+ DSP_BLOCK_BALANCING = AUTO;
+ STATE_MACHINE_PROCESSING = AUTO;
+}
+DEFAULT_HARDCOPY_SETTINGS
+{
+ HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
+}
+DEFAULT_TIMING_REQUIREMENTS
+{
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ RUN_ALL_TIMING_ANALYSES = ON;
+ IGNORE_CLOCK_SETTINGS = OFF;
+ DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
+ CUT_OFF_IO_PIN_FEEDBACK = ON;
+ CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+ CUT_OFF_READ_DURING_WRITE_PATHS = ON;
+ CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
+ DO_MIN_ANALYSIS = ON;
+ DO_MIN_TIMING = OFF;
+ NUMBER_OF_PATHS_TO_REPORT = 200;
+ NUMBER_OF_DESTINATION_TO_REPORT = 10;
+ NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
+ MAX_SCC_SIZE = 50;
+}
+HDL_SETTINGS
+{
+ VERILOG_INPUT_VERSION = VERILOG_2001;
+ ENABLE_IP_DEBUG = OFF;
+ VHDL_INPUT_VERSION = VHDL93;
+ VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
+}
+PROJECT_INFO(usrp_std)
+{
+ ORIGINAL_QUARTUS_VERSION = 3.0;
+ PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003";
+ LAST_QUARTUS_VERSION = 3.0;
+ SHOW_REGISTRATION_MESSAGE = ON;
+ USER_LIBRARIES = "e:\usrp\fpga\megacells";
+}
+THIRD_PARTY_EDA_TOOLS(usrp_std)
+{
+ EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
+ EDA_SIMULATION_TOOL = "<NONE>";
+ EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
+ EDA_BOARD_DESIGN_TOOL = "<NONE>";
+ EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
+ EDA_RESYNTHESIS_TOOL = "<NONE>";
+}
+EDA_TOOL_SETTINGS(eda_design_synthesis)
+{
+ EDA_INPUT_GND_NAME = GND;
+ EDA_INPUT_VCC_NAME = VCC;
+ EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_INPUT_DATA_FORMAT = EDIF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_simulation)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_timing_analysis)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ EDA_LAUNCH_CMD_LINE_TOOL = OFF;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_board_design)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_formal_verification)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ RESYNTHESIS_RETIMING = FULL;
+}
+EDA_TOOL_SETTINGS(eda_palace)
+{
+ EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
+ EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
+ EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
+ EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
+ EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
+ EDA_FLATTEN_BUSES = OFF;
+ EDA_MAP_ILLEGAL_CHARACTERS = OFF;
+ EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
+ EDA_RUN_TOOL_AUTOMATICALLY = OFF;
+ EDA_OUTPUT_DATA_FORMAT = NONE;
+ RESYNTHESIS_RETIMING = FULL;
+ RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
+ RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
+ USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
+}
+CLOCK(clk_120mhz)
+{
+ FMAX_REQUIREMENT = "120.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(usbclk)
+{
+ FMAX_REQUIREMENT = "48.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(SCLK)
+{
+ FMAX_REQUIREMENT = "1.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk0)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
+CLOCK(adclk1)
+{
+ FMAX_REQUIREMENT = "60.0 MHz";
+ INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
+ DUTY_CYCLE = 50;
+ DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
+ MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
+ INVERT_BASE_CLOCK = OFF;
+}
diff --git a/toplevel/usrp_std/usrp_std.qpf b/toplevel/usrp_std/usrp_std.qpf
new file mode 100644
index 000000000..e8b27505c
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.qpf
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.0"
+DATE = "17:10:11 December 20, 2004"
+
+
+# Active Revisions
+
+PROJECT_REVISION = "usrp_std"
diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf
new file mode 100644
index 000000000..51d7e1ea2
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.qsf
@@ -0,0 +1,406 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# usrp_std_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
+
+# Pin & Location Assignments
+# ==========================
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
+set_location_assignment PIN_29 -to SCLK
+set_location_assignment PIN_117 -to SDI
+set_location_assignment PIN_28 -to usbclk
+set_location_assignment PIN_107 -to usbctl[0]
+set_location_assignment PIN_106 -to usbctl[1]
+set_location_assignment PIN_105 -to usbctl[2]
+set_location_assignment PIN_100 -to usbdata[0]
+set_location_assignment PIN_84 -to usbdata[10]
+set_location_assignment PIN_83 -to usbdata[11]
+set_location_assignment PIN_82 -to usbdata[12]
+set_location_assignment PIN_79 -to usbdata[13]
+set_location_assignment PIN_78 -to usbdata[14]
+set_location_assignment PIN_77 -to usbdata[15]
+set_location_assignment PIN_99 -to usbdata[1]
+set_location_assignment PIN_98 -to usbdata[2]
+set_location_assignment PIN_95 -to usbdata[3]
+set_location_assignment PIN_94 -to usbdata[4]
+set_location_assignment PIN_93 -to usbdata[5]
+set_location_assignment PIN_88 -to usbdata[6]
+set_location_assignment PIN_87 -to usbdata[7]
+set_location_assignment PIN_86 -to usbdata[8]
+set_location_assignment PIN_85 -to usbdata[9]
+set_location_assignment PIN_104 -to usbrdy[0]
+set_location_assignment PIN_101 -to usbrdy[1]
+set_location_assignment PIN_76 -to FX2_1
+set_location_assignment PIN_75 -to FX2_2
+set_location_assignment PIN_74 -to FX2_3
+set_location_assignment PIN_116 -to io_rx_a[0]
+set_location_assignment PIN_115 -to io_rx_a[1]
+set_location_assignment PIN_114 -to io_rx_a[2]
+set_location_assignment PIN_113 -to io_rx_a[3]
+set_location_assignment PIN_108 -to io_rx_a[4]
+set_location_assignment PIN_195 -to io_rx_a[5]
+set_location_assignment PIN_196 -to io_rx_a[6]
+set_location_assignment PIN_197 -to io_rx_a[7]
+set_location_assignment PIN_200 -to io_rx_a[8]
+set_location_assignment PIN_201 -to io_rx_a[9]
+set_location_assignment PIN_202 -to io_rx_a[10]
+set_location_assignment PIN_203 -to io_rx_a[11]
+set_location_assignment PIN_206 -to io_rx_a[12]
+set_location_assignment PIN_207 -to io_rx_a[13]
+set_location_assignment PIN_208 -to io_rx_a[14]
+set_location_assignment PIN_214 -to io_rx_b[0]
+set_location_assignment PIN_215 -to io_rx_b[1]
+set_location_assignment PIN_216 -to io_rx_b[2]
+set_location_assignment PIN_217 -to io_rx_b[3]
+set_location_assignment PIN_218 -to io_rx_b[4]
+set_location_assignment PIN_219 -to io_rx_b[5]
+set_location_assignment PIN_222 -to io_rx_b[6]
+set_location_assignment PIN_223 -to io_rx_b[7]
+set_location_assignment PIN_224 -to io_rx_b[8]
+set_location_assignment PIN_225 -to io_rx_b[9]
+set_location_assignment PIN_226 -to io_rx_b[10]
+set_location_assignment PIN_227 -to io_rx_b[11]
+set_location_assignment PIN_228 -to io_rx_b[12]
+set_location_assignment PIN_233 -to io_rx_b[13]
+set_location_assignment PIN_234 -to io_rx_b[14]
+set_location_assignment PIN_175 -to io_tx_a[0]
+set_location_assignment PIN_176 -to io_tx_a[1]
+set_location_assignment PIN_177 -to io_tx_a[2]
+set_location_assignment PIN_178 -to io_tx_a[3]
+set_location_assignment PIN_179 -to io_tx_a[4]
+set_location_assignment PIN_180 -to io_tx_a[5]
+set_location_assignment PIN_181 -to io_tx_a[6]
+set_location_assignment PIN_182 -to io_tx_a[7]
+set_location_assignment PIN_183 -to io_tx_a[8]
+set_location_assignment PIN_184 -to io_tx_a[9]
+set_location_assignment PIN_185 -to io_tx_a[10]
+set_location_assignment PIN_186 -to io_tx_a[11]
+set_location_assignment PIN_187 -to io_tx_a[12]
+set_location_assignment PIN_188 -to io_tx_a[13]
+set_location_assignment PIN_193 -to io_tx_a[14]
+set_location_assignment PIN_73 -to io_tx_b[0]
+set_location_assignment PIN_68 -to io_tx_b[1]
+set_location_assignment PIN_67 -to io_tx_b[2]
+set_location_assignment PIN_66 -to io_tx_b[3]
+set_location_assignment PIN_65 -to io_tx_b[4]
+set_location_assignment PIN_64 -to io_tx_b[5]
+set_location_assignment PIN_63 -to io_tx_b[6]
+set_location_assignment PIN_62 -to io_tx_b[7]
+set_location_assignment PIN_61 -to io_tx_b[8]
+set_location_assignment PIN_60 -to io_tx_b[9]
+set_location_assignment PIN_59 -to io_tx_b[10]
+set_location_assignment PIN_58 -to io_tx_b[11]
+set_location_assignment PIN_57 -to io_tx_b[12]
+set_location_assignment PIN_56 -to io_tx_b[13]
+set_location_assignment PIN_55 -to io_tx_b[14]
+set_location_assignment PIN_152 -to master_clk
+set_location_assignment PIN_144 -to rx_a_a[0]
+set_location_assignment PIN_143 -to rx_a_a[1]
+set_location_assignment PIN_141 -to rx_a_a[2]
+set_location_assignment PIN_140 -to rx_a_a[3]
+set_location_assignment PIN_139 -to rx_a_a[4]
+set_location_assignment PIN_138 -to rx_a_a[5]
+set_location_assignment PIN_137 -to rx_a_a[6]
+set_location_assignment PIN_136 -to rx_a_a[7]
+set_location_assignment PIN_135 -to rx_a_a[8]
+set_location_assignment PIN_134 -to rx_a_a[9]
+set_location_assignment PIN_133 -to rx_a_a[10]
+set_location_assignment PIN_132 -to rx_a_a[11]
+set_location_assignment PIN_23 -to rx_a_b[0]
+set_location_assignment PIN_21 -to rx_a_b[1]
+set_location_assignment PIN_20 -to rx_a_b[2]
+set_location_assignment PIN_19 -to rx_a_b[3]
+set_location_assignment PIN_18 -to rx_a_b[4]
+set_location_assignment PIN_17 -to rx_a_b[5]
+set_location_assignment PIN_16 -to rx_a_b[6]
+set_location_assignment PIN_15 -to rx_a_b[7]
+set_location_assignment PIN_14 -to rx_a_b[8]
+set_location_assignment PIN_13 -to rx_a_b[9]
+set_location_assignment PIN_12 -to rx_a_b[10]
+set_location_assignment PIN_11 -to rx_a_b[11]
+set_location_assignment PIN_131 -to rx_b_a[0]
+set_location_assignment PIN_128 -to rx_b_a[1]
+set_location_assignment PIN_127 -to rx_b_a[2]
+set_location_assignment PIN_126 -to rx_b_a[3]
+set_location_assignment PIN_125 -to rx_b_a[4]
+set_location_assignment PIN_124 -to rx_b_a[5]
+set_location_assignment PIN_123 -to rx_b_a[6]
+set_location_assignment PIN_122 -to rx_b_a[7]
+set_location_assignment PIN_121 -to rx_b_a[8]
+set_location_assignment PIN_120 -to rx_b_a[9]
+set_location_assignment PIN_119 -to rx_b_a[10]
+set_location_assignment PIN_118 -to rx_b_a[11]
+set_location_assignment PIN_8 -to rx_b_b[0]
+set_location_assignment PIN_7 -to rx_b_b[1]
+set_location_assignment PIN_6 -to rx_b_b[2]
+set_location_assignment PIN_5 -to rx_b_b[3]
+set_location_assignment PIN_4 -to rx_b_b[4]
+set_location_assignment PIN_3 -to rx_b_b[5]
+set_location_assignment PIN_2 -to rx_b_b[6]
+set_location_assignment PIN_240 -to rx_b_b[7]
+set_location_assignment PIN_239 -to rx_b_b[8]
+set_location_assignment PIN_238 -to rx_b_b[9]
+set_location_assignment PIN_237 -to rx_b_b[10]
+set_location_assignment PIN_236 -to rx_b_b[11]
+set_location_assignment PIN_156 -to SDO
+set_location_assignment PIN_153 -to SEN_FPGA
+set_location_assignment PIN_159 -to tx_a[0]
+set_location_assignment PIN_160 -to tx_a[1]
+set_location_assignment PIN_161 -to tx_a[2]
+set_location_assignment PIN_162 -to tx_a[3]
+set_location_assignment PIN_163 -to tx_a[4]
+set_location_assignment PIN_164 -to tx_a[5]
+set_location_assignment PIN_165 -to tx_a[6]
+set_location_assignment PIN_166 -to tx_a[7]
+set_location_assignment PIN_167 -to tx_a[8]
+set_location_assignment PIN_168 -to tx_a[9]
+set_location_assignment PIN_169 -to tx_a[10]
+set_location_assignment PIN_170 -to tx_a[11]
+set_location_assignment PIN_173 -to tx_a[12]
+set_location_assignment PIN_174 -to tx_a[13]
+set_location_assignment PIN_38 -to tx_b[0]
+set_location_assignment PIN_39 -to tx_b[1]
+set_location_assignment PIN_41 -to tx_b[2]
+set_location_assignment PIN_42 -to tx_b[3]
+set_location_assignment PIN_43 -to tx_b[4]
+set_location_assignment PIN_44 -to tx_b[5]
+set_location_assignment PIN_45 -to tx_b[6]
+set_location_assignment PIN_46 -to tx_b[7]
+set_location_assignment PIN_47 -to tx_b[8]
+set_location_assignment PIN_48 -to tx_b[9]
+set_location_assignment PIN_49 -to tx_b[10]
+set_location_assignment PIN_50 -to tx_b[11]
+set_location_assignment PIN_53 -to tx_b[12]
+set_location_assignment PIN_54 -to tx_b[13]
+set_location_assignment PIN_158 -to TXSYNC_A
+set_location_assignment PIN_37 -to TXSYNC_B
+set_location_assignment PIN_235 -to io_rx_b[15]
+set_location_assignment PIN_24 -to io_tx_b[15]
+set_location_assignment PIN_213 -to io_rx_a[15]
+set_location_assignment PIN_194 -to io_tx_a[15]
+set_location_assignment PIN_1 -to MYSTERY_SIGNAL
+
+# Timing Assignments
+# ==================
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name TOP_LEVEL_ENTITY usrp_std
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name MAX_SCC_SIZE 50
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name START_TIME "0 ns"
+set_global_assignment -name GLITCH_INTERVAL "1 ns"
+
+# Design Assistant Assignments
+# ============================
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT OFF
+set_global_assignment -name HCPY_VREF_PINS OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
+set_global_assignment -name ENABLE_SIGNALTAP Off
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# -----------------
+# start CLOCK(SCLK)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+ set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
+
+# end CLOCK(SCLK)
+# ---------------
+
+# -----------------------
+# start CLOCK(master_clk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+ set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
+
+# end CLOCK(master_clk)
+# ---------------------
+
+# -------------------
+# start CLOCK(usbclk)
+
+ # Timing Assignments
+ # ==================
+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+ set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk
+ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
+
+# end CLOCK(usbclk)
+# -----------------
+
+# ----------------------
+# start ENTITY(usrp_std)
+
+ # Timing Assignments
+ # ==================
+ set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+ set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+
+# end ENTITY(usrp_std)
+# --------------------
+
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE usrp_std.vh
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
+set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE usrp_std.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v \ No newline at end of file
diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v
new file mode 100644
index 000000000..9ba8c7c65
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.v
@@ -0,0 +1,324 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003,2004 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// Top level module for a full setup with DUCs and DDCs
+
+// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
+// for debugging info. NB, This can kill the m'board and/or d'board if you
+// have anything except basic d'boards installed.
+
+// Uncomment the following to include optional circuitry
+
+`include "usrp_std.vh"
+`include "../../../firmware/include/fpga_regs_common.v"
+`include "../../../firmware/include/fpga_regs_standard.v"
+
+module usrp_std
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ input wire [11:0] rx_a_b,
+ input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ output wire TXSYNC_B,
+
+ // USB interface
+ input usbclk,
+ input wire [2:0] usbctl,
+ output wire [1:0] usbrdy,
+ inout [15:0] usbdata, // NB Careful, inout
+
+ // These are the general purpose i/o's that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ inout wire [15:0] io_rx_b
+ );
+ wire [15:0] debugdata,debugctrl;
+ assign MYSTERY_SIGNAL = 1'b0;
+
+ wire clk64,clk128;
+
+ wire WR = usbctl[0];
+ wire RD = usbctl[1];
+ wire OE = usbctl[2];
+
+ wire have_space, have_pkt_rdy;
+ assign usbrdy[0] = have_space;
+ assign usbrdy[1] = have_pkt_rdy;
+
+ wire tx_underrun, rx_overrun;
+ wire clear_status = FX2_1;
+ assign FX2_2 = rx_overrun;
+ assign FX2_3 = tx_underrun;
+
+ wire [15:0] usbdata_out;
+
+ wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
+
+ wire tx_realsignals;
+ wire [3:0] rx_numchan;
+ wire [2:0] tx_numchan;
+
+ wire [7:0] interp_rate, decim_rate;
+ wire [15:0] tx_debugbus, rx_debugbus;
+
+ wire enable_tx, enable_rx;
+ wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+ wire [7:0] settings;
+
+ // Tri-state bus macro
+ bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+ assign clk64 = master_clk;
+
+ wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
+ wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+
+ // TX
+ wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
+ wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
+
+ wire strobe_interp, tx_sample_strobe;
+ wire tx_empty;
+
+ wire serial_strobe;
+ wire [6:0] serial_addr;
+ wire [31:0] serial_data;
+
+ reg [15:0] debug_counter;
+ reg [15:0] loopback_i_0,loopback_q_0;
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Transmit Side
+`ifdef TX_ON
+ assign bb_tx_i0 = ch0tx;
+ assign bb_tx_q0 = ch1tx;
+ assign bb_tx_i1 = ch2tx;
+ assign bb_tx_q1 = ch3tx;
+
+ tx_buffer tx_buffer
+ ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+ .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+ .channels({tx_numchan,1'b0}),
+ .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+ .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+ .tx_i_2(),.tx_q_2(),
+ .tx_i_3(),.tx_q_3(),
+ .txclk(clk64),.txstrobe(strobe_interp),
+ .clear_status(clear_status),
+ .tx_empty(tx_empty),
+ .debugbus(tx_debugbus) );
+
+ tx_chain tx_chain_0
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+
+ tx_chain tx_chain_1
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+ .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+ .interpolator_strobe(strobe_interp),.freq(),
+ .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+
+ setting_reg #(`FR_TX_MUX)
+ sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+ .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+
+ wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+ wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
+
+ wire txsync = tx_sample_strobe;
+ assign TXSYNC_A = txsync;
+ assign TXSYNC_B = txsync;
+
+ assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
+ assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
+`endif // `ifdef TX_ON
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Receive Side
+`ifdef RX_ON
+ wire rx_sample_strobe,strobe_decim,hb_strobe;
+ wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
+ bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
+
+ wire loopback = settings[0];
+ wire counter = settings[1];
+
+ always @(posedge clk64)
+ if(rx_dsp_reset)
+ debug_counter <= #1 16'd0;
+ else if(~enable_rx)
+ debug_counter <= #1 16'd0;
+ else if(hb_strobe)
+ debug_counter <=#1 debug_counter + 16'd2;
+
+ always @(posedge clk64)
+ if(strobe_interp)
+ begin
+ loopback_i_0 <= #1 ch0tx;
+ loopback_q_0 <= #1 ch1tx;
+ end
+
+ assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
+ assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
+ assign ch2rx = bb_rx_i1;
+ assign ch3rx = bb_rx_q1;
+ assign ch4rx = bb_rx_i2;
+ assign ch5rx = bb_rx_q2;
+ assign ch6rx = bb_rx_i3;
+ assign ch7rx = bb_rx_q3;
+
+ wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
+ wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
+
+ adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
+ .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
+ .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
+ .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
+ .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
+ .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
+
+ rx_buffer rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ .reset_regs(rx_dsp_reset),
+ .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(ch0rx),.ch_1(ch1rx),
+ .ch_2(ch2rx),.ch_3(ch3rx),
+ .ch_4(ch4rx),.ch_5(ch5rx),
+ .ch_6(ch6rx),.ch_7(ch7rx),
+ .rxclk(clk64),.rxstrobe(hb_strobe),
+ .clear_status(clear_status),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .debugbus(rx_debugbus) );
+
+ `ifdef RX_EN_0
+ rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
+ `else
+ assign bb_rx_i0=16'd0;
+ assign bb_rx_q0=16'd0;
+ `endif
+
+ `ifdef RX_EN_1
+ rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
+ `else
+ assign bb_rx_i1=16'd0;
+ assign bb_rx_q1=16'd0;
+ `endif
+
+ `ifdef RX_EN_2
+ rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
+ `else
+ assign bb_rx_i2=16'd0;
+ assign bb_rx_q2=16'd0;
+ `endif
+
+ `ifdef RX_EN_3
+ rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
+ ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
+ .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
+ `else
+ assign bb_rx_i3=16'd0;
+ assign bb_rx_q3=16'd0;
+ `endif
+
+`endif // `ifdef RX_ON
+
+ ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Control Functions
+
+ wire [31:0] capabilities;
+ assign capabilities[7] = `TX_CAP_HB;
+ assign capabilities[6:4] = `TX_CAP_NCHAN;
+ assign capabilities[3] = `RX_CAP_HB;
+ assign capabilities[2:0] = `RX_CAP_NCHAN;
+
+
+ serial_io serial_io
+ ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+ .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
+ .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
+ );
+
+ wire [15:0] reg_0,reg_1,reg_2,reg_3;
+ master_control master_control
+ ( .master_clk(clk64),.usbclk(usbclk),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+ .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+ .enable_tx(enable_tx),.enable_rx(enable_rx),
+ .interp_rate(interp_rate),.decim_rate(decim_rate),
+ .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+ .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+ .tx_empty(tx_empty),
+ //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+ .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+ io_pins io_pins
+ (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+ .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Misc Settings
+ setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
+
+endmodule // usrp_std
diff --git a/toplevel/usrp_std/usrp_std.vh b/toplevel/usrp_std/usrp_std.vh
new file mode 100644
index 000000000..65aed9b43
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std.vh
@@ -0,0 +1,119 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// ====================================================================
+// User control over what parts get included
+//
+// >>>> EDIT ONLY THIS SECTION <<<<
+//
+// ====================================================================
+
+// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
+ `include "usrp_std_config_2rxhb_2tx.vh"
+
+// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
+//`include "usrp_std_config_4rx_0tx.vh"
+
+// Add other "known to fit" configurations here...
+
+// ====================================================================
+//
+// >>>> DO NOT EDIT BELOW HERE <<<<
+//
+// [The stuff from here down is derived from the stuff included above]
+//
+// N.B., *all* the remainder of the code should be conditionalized
+// only in terms of:
+//
+// TX_ON, TX_EN_0, TX_EN_1, TX_EN_2, TX_EN_3, TX_CAP_NCHAN, TX_CAP_HB,
+// RX_ON, RX_EN_0, RX_EN_1, RX_EN_2, RX_EN_3, RX_CAP_NCHAN, RX_CAP_HB,
+// RX_NCO_ON, RX_CIC_ON
+// ====================================================================
+
+`ifdef TX_ON
+
+ `ifdef TX_SINGLE
+ `define TX_EN_0
+ `define TX_CAP_NCHAN 3'd1
+ `endif
+
+ `ifdef TX_DUAL
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_CAP_NCHAN 3'd2
+ `endif
+
+ `ifdef TX_QUAD
+ `define TX_EN_0
+ `define TX_EN_1
+ `define TX_EN_2
+ `define TX_EN_3
+ `define TX_CAP_NCHAN 3'd4
+ `endif
+
+ `ifdef TX_HB_ON
+ `define TX_CAP_HB 1
+ `else
+ `define TX_CAP_HB 0
+ `endif
+
+`else // !ifdef TX_ON
+
+ `define TX_CAP_NCHAN 3'd0
+ `define TX_CAP_HB 0
+
+`endif // !ifdef TX_ON
+
+// --------------------------------------------------------------------
+
+`ifdef RX_ON
+
+ `ifdef RX_SINGLE
+ `define RX_EN_0
+ `define RX_CAP_NCHAN 3'd1
+ `endif
+
+ `ifdef RX_DUAL
+ `define RX_EN_0
+ `define RX_EN_1
+ `define RX_CAP_NCHAN 3'd2
+ `endif
+
+ `ifdef RX_QUAD
+ `define RX_EN_0
+ `define RX_EN_1
+ `define RX_EN_2
+ `define RX_EN_3
+ `define RX_CAP_NCHAN 3'd4
+ `endif
+
+ `ifdef RX_HB_ON
+ `define RX_CAP_HB 1
+ `else
+ `define RX_CAP_HB 0
+ `endif
+
+`else // !ifdef RX_ON
+
+ `define RX_CAP_NCHAN 3'd0
+ `define RX_CAP_HB 0
+
+`endif // !ifdef RX_ON
diff --git a/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh
new file mode 100644
index 000000000..74f1bfd1c
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std_config_2rxhb_2tx.vh
@@ -0,0 +1,61 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+ `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+ `define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+ `define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+ `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON
diff --git a/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh
new file mode 100644
index 000000000..0bd188778
--- /dev/null
+++ b/toplevel/usrp_std/usrp_std_config_4rx_0tx.vh
@@ -0,0 +1,61 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2006 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+// `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_DUAL is currently valid]
+//`define TX_SINGLE
+//`define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* transmit circuitry built
+ `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+//`define RX_DUAL
+ `define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+//`define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+ `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+ `define RX_CIC_ON