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-rw-r--r--usrp2/top/u1e/u1e_core.v3
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 71b9b8712..48b5bd010 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -361,7 +361,8 @@ module u1e_core
// Debug circuitry
assign debug_clk = { EM_CLK, clk_fpga };
- assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun },
+ { EM_A[8:1] },
{ EM_D } };
//assign debug = { phase[23:8], txsync, txblank, tx };